N32G455VEL7

Nations Technologies Inc · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

N32G455VEL7 from Nations Technologies Inc, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	PE2	bidirectional	GPIO PE2, FT I/O (5 V tolerant, fail-safe); alternate functions TRACECK and UART6_TX.
2	PE3	bidirectional	GPIO PE3, FT I/O (5 V tolerant, fail-safe); alternate functions TRACED0 and UART6_RX.
3	PE4	bidirectional	GPIO PE4, FT I/O (5 V tolerant, fail-safe); alternate function TRACED1.
4	PE5	bidirectional	GPIO PE5, FT I/O (5 V tolerant, fail-safe); alternate function TRACED2.
5	PE6	bidirectional	GPIO PE6, FT I/O (5 V tolerant, fail-safe); alternate function TRACED3.
6	VBAT	power_in	Backup-domain supply, 1.8 to 3.6 V, powers the RTC, the 32.768 kHz oscillator and the backup registers when VDD is off.
7	PC13-TAMPER-RTC	bidirectional	TC I/O (standard 3.3 V) powered through a power switch limited to about 3 mA; as an output it is limited to one pin at a time, 2 MHz mode, 30 pF load and no current-source use; alternate function TAMPER-RTC.
8	PC14-OSC32_IN	bidirectional	TC I/O (standard 3.3 V) powered through a power switch limited to about 3 mA, with the same output restrictions as PC13 (one output at a time, 2 MHz, 30 pF, no LED drive); alternate function OSC32_IN.
9	PC15-OSC32_OUT	bidirectional	TC I/O (standard 3.3 V) powered through a power switch limited to about 3 mA, with the same output restrictions as PC13 (one output at a time, 2 MHz, 30 pF, no LED drive); alternate function OSC32_OUT.
10	VSS_5	power_in	Digital ground pin; all VSS pins must be connected to the external ground system.
11	VDD_5	power_in	I/O and internal regulator supply, 1.8 to 3.6 V.
12	OSC_IN	input	HSE oscillator input for a 4 to 32 MHz crystal/resonator or external clock; also FT/TC level pin (OSC_IN).
13	OSC_OUT	output	HSE oscillator output for the 4 to 32 MHz crystal/resonator circuit.
14	NRST	input	Active-low external reset input with an internal pull-up of 30 to 70 kOhm; a 100 ns input filter pulse is specified.
15	PC0	bidirectional	TTa I/O (3.3 V tolerant, analog-capable); alternate functions ADC12_IN6, I2C3_SCL, COMP7_INM and UART6_TX.
16	PC1	bidirectional	TTa I/O (3.3 V tolerant, analog-capable); alternate functions ADC12_IN7, I2C3_SDA, COMP7_INP and UART6_RX.
17	PC2	bidirectional	TTa I/O (3.3 V tolerant, analog-capable); alternate functions ADC12_IN8, COMP7_OUT, UART7_TX, SPI3_NSS and I2S3_WS.
18	PC3	bidirectional	TTa I/O (3.3 V tolerant, analog-capable); alternate functions ADC12_IN9, UART7_RX, SPI3_SCK, I2S3_CK, OPAMP3_VINP, OPAMP4_VINP and COMP5_INP.
19	VSSA	power_in	Ground for the analog section (ADC, DAC, OPAMP, COMP, TSC); VSSA must be connected to VSS.
20	VREF-	power_in	Negative reference input for the ADC; the ADC input range is VREF- ≤ VIN ≤ VREF+.
21	VREF+	power_in	Positive reference voltage input for the ADC and DAC; VREF+ must always be lower than VDDA.
22	VDDA	power_in	Analog supply for ADC, DAC, OPAMP, COMP and TSC, 1.8 to 3.6 V, and it must be the same supply as VDD (up to 300 mV difference).
23	PA0-WKUP	bidirectional	TTa I/O (3.3 V tolerant, analog-capable); WKUP wake-up input (rising edge wakes from STANDBY); alternate functions include ADC1_IN1, USART2_CTS, TIM2_CH1_ETR, TIM5_CH1, TIM8_ETR, COMP1_OUT, COMP1_INM and SPI3_MISO.
24	PA1	bidirectional	TTa I/O (3.3 V tolerant, analog-capable); alternate functions USART2_RTS, ADC1_IN2, TIM5_CH2, TIM2_CH2, COMP1_INP, OPAMP1_VINP, OPAMP3_VINP, SPI3_MOSI and I2S3_SD.
25	PA2	bidirectional	TTa I/O (3.3 V tolerant, analog-capable); alternate functions USART2_TX, TIM5_CH3, ADC12_IN11, TIM2_CH3, COMP2_OUT, OPAMP1_INM and OPAMP2_INM.
26	PA3	bidirectional	TTa I/O (3.3 V tolerant, analog-capable); alternate functions USART2_RX, TIM5_CH4, ADC1_IN4, TIM2_CH4, OPAMP1_VINM, OPAMP1_VINP and COMP5_INP.
27	VSS_4	power_in	Digital ground pin; all VSS pins must be connected to the external ground system.
28	VDD_4	power_in	I/O and internal regulator supply, 1.8 to 3.6 V.
29	PA4	bidirectional	TTa I/O (3.3 V tolerant, analog-capable); alternate functions SPI1_NSS, USART2_CK, DAC_OUT1, ADC2_IN1, QSPI_NSS, TSC_CHN0, several COMP inverting inputs, OPAMP4_VINP and I2C2_SCL.
30	PA5	bidirectional	TTa I/O (3.3 V tolerant, analog-capable); alternate functions SPI1_SCK, DAC_OUT2, ADC2_IN2, QSPI_SCK, TSC_CHN1, several COMP inverting inputs, OPAMP1_VINP, OPAMP2_VINM, OPAMP3_VINP and I2C2_SDA.
31	PA6	bidirectional	TTa I/O (3.3 V tolerant, analog-capable); alternate functions SPI1_MISO, TIM8_BKIN, ADC1_IN3, TIM3_CH1, COMP1_OUT, QSPI_IO0, TIM1_BKIN, OPAMP1_VOUT and COMP2_OUT.
32	PA7	bidirectional	TTa I/O (3.3 V tolerant, analog-capable); alternate functions SPI1_MOSI, TIM8_CH1N, ADC2_IN4, TIM3_CH2, QSPI_IO1, COMP2_OUT, TIM1_CH1N, COMP2_INP, OPAMP1_VINP, OPAMP2_VINP and COMP6_INM.
33	PC4	bidirectional	TTa I/O (3.3 V tolerant, analog-capable); alternate functions ADC2_IN5, QSPI_IO2, UART7_TX, I2C3_SCL, OPAMP3_VINM, COMP4_INM and COMP5_INP.
34	PC5	bidirectional	TTa I/O (3.3 V tolerant, analog-capable); alternate functions ADC2_IN12, QSPI_IO3, UART7_RX, I2C3_SDA, OPAMP4_VINP, COMP4_OUT and COMP6_INP.
35	PB0	bidirectional	TTa I/O (3.3 V tolerant, analog-capable); alternate functions ADC3_IN12, TIM3_CH3, TIM8_CH2N, TIM1_CH2N, UART6_TX, OPAMP2_VINP, COMP3_INP and COMP5_OUT.
36	PB1	bidirectional	TTa I/O (3.3 V tolerant, analog-capable); alternate functions ADC2_IN3, TIM3_CH4, TIM8_CH3N, COMP4_OUT, TIM1_CH3N, OPAMP2_VOUT, UART6_RX, COMP2_INM and COMP1_OUT.
37	PB2/BOOT1	bidirectional	TTa I/O (3.3 V tolerant, analog-capable); BOOT1 boot-mode function; alternate functions ADC2_IN13, UART4_TX and SPI1_NSS.
38	PE7	bidirectional	TTa I/O (3.3 V tolerant, analog-capable); alternate functions ADC3_IN13, TIM1_ETR, UART4_RX, SPI1_SCK and COMP3_INM.
39	PE8	bidirectional	TTa I/O (3.3 V tolerant, analog-capable); alternate functions ADC34_IN6, TIM1_CH1N, UART5_TX, SDIO_D0, SPI1_MISO, OPAMP2_INP and COMP2_INM.
40	PE9	bidirectional	TTa I/O (3.3 V tolerant, analog-capable); alternate functions ADC3_IN2, TIM1_CH1, UART5_RX, SDIO_D1 and SPI1_MOSI.
41	PE10	bidirectional	TTa I/O (3.3 V tolerant, analog-capable); alternate functions ADC3_IN14, TIM1_CH2N, SDIO_D2, SPI2_NSS and I2S2_WS.
42	PE11	bidirectional	TTa I/O (3.3 V tolerant, analog-capable); alternate functions ADC3_IN15, TIM1_CH2, SDIO_D3, SPI2_SCK and I2S2_CK.
43	PE12	bidirectional	TTa I/O (3.3 V tolerant, analog-capable); alternate functions ADC3_IN4, TIM1_CH3N, SDIO_CK and SPI2_MISO.
44	PE13	bidirectional	TTa I/O (3.3 V tolerant, analog-capable); alternate functions ADC3_IN3, TIM1_CH3, SPI2_MOSI, I2S2_SD and SDIO_CMD.
45	PE14	bidirectional	TTa I/O (3.3 V tolerant, analog-capable); alternate functions ADC4_IN1 and TIM1_CH4.
46	PE15	bidirectional	TTa I/O (3.3 V tolerant, analog-capable); alternate functions ADC4_IN2 and TIM1_BKIN.
47	PB10	bidirectional	TTa I/O (3.3 V tolerant, analog-capable) with Yes fail-safe; alternate functions I2C2_SCL, USART3_TX, TIM2_CH3, COMP5_INM, OPAMP3_VINM, OPAMP4_VINM, COMP1_INP and COMP3_OUT.
48	PB11	bidirectional	TTa I/O (3.3 V tolerant, analog-capable); alternate functions I2C2_SDA, USART3_RX, ADC3_IN1, TIM2_CH4, OPAMP3_VOUT, COMP2_INP and COMP5_OUT.
49	VSS_1	power_in	Digital ground pin; all VSS pins must be connected to the external ground system.
50	VDD_1	power_in	I/O and internal regulator supply, 1.8 to 3.6 V.
51	PB12	bidirectional	TTa I/O (3.3 V tolerant, analog-capable); alternate functions SPI2_NSS, I2S2_WS, I2C2_SMBA, USART3_CK, TIM1_BKIN, CAN2_RX, ADC4_IN3, COMP3_INM, OPAMP4_VOUT and COMP4_OUT.
52	PB13	bidirectional	TTa I/O (3.3 V tolerant, analog-capable); alternate functions SPI2_SCK, I2S2_CK, USART3_CTS, TIM1_CH1N, CAN2_TX, ADC3_IN5, UART5_TX and COMP4_INM.
53	PB14	bidirectional	TTa I/O (3.3 V tolerant, analog-capable); alternate functions SPI2_MISO, TIM1_CH2N, USART3_RTS, ADC4_IN4, TSC_CHN2, COMP3_INP and UART5_RX.
54	PB15	bidirectional	TTa I/O (3.3 V tolerant, analog-capable); alternate functions SPI2_MOSI, I2S2_SD, TIM1_CH3N, ADC4_IN5, TSC_CHN3 and COMP4_INP.
55	PD8	bidirectional	TTa I/O (3.3 V tolerant, analog-capable); alternate functions ADC4_IN12, TSC_CHN4, USART3_TX, OPAMP4_VINM, SPI3_NSS, I2S3_WS, CAN1_RX, and COMP6_INM.
56	PD9	bidirectional	TTa I/O (3.3 V tolerant, analog-capable); alternate functions ADC4_IN13, TSC_CHN5, USART3_RX, SPI3_SCK, I2S3_CK, CAN1_TX and COMP6_INP.
57	PD10	bidirectional	TTa I/O (3.3 V tolerant, analog-capable); alternate functions ADC34_IN7, USART3_CK, CAN2_RX and COMP5_INM.
58	PD11	bidirectional	TTa I/O (3.3 V tolerant, analog-capable); alternate functions ADC34_IN8, TSC_CHN6, USART3_CTS, CAN2_TX and SPI3_MISO.
59	PD12	bidirectional	TTa I/O (3.3 V tolerant, analog-capable); alternate functions ADC34_IN9, TSC_CHN7, TIM4_CH1, USART3_RTS, SPI3_MOSI, I2S3_SD and COMP7_OUT.
60	PD13	bidirectional	TTa I/O (3.3 V tolerant, analog-capable); alternate functions ADC34_IN10 and TIM4_CH2.
61	PD14	bidirectional	TTa I/O (3.3 V tolerant, analog-capable); alternate functions ADC34_IN11, TIM4_CH3, I2C4_SCL and TIM8_CH1.
62	PD15	bidirectional	FT I/O (5 V tolerant, fail-safe); alternate functions TIM4_CH4, I2C4_SDA and TIM8_CH2.
63	PC6	bidirectional	TTa I/O (3.3 V tolerant, analog-capable) with fail-safe; alternate functions I2S2_MCK, TIM3_CH1, TIM8_CH1, SDIO_D6, I2C4_SCL, TSC_CHN8, SPI2_NSS, I2S2_WS and USART2_CTS.
64	PC7	bidirectional	TTa I/O (3.3 V tolerant, analog-capable) with fail-safe; alternate functions I2S3_MCK, TIM8_CH2, SDIO_D7, I2C4_SDA, TSC_CHN9, TIM3_CH2, SPI2_SCK, I2S2_CK and USART2_RTS.
65	PC8	bidirectional	TTa I/O (3.3 V tolerant, analog-capable) with fail-safe; alternate functions TIM8_CH3, SDIO_D0, TSC_CHN10, TIM3_CH3, SPI2_MISO and USART2_TX.
66	PC9	bidirectional	TTa I/O (3.3 V tolerant, analog-capable) with fail-safe; alternate functions TIM8_CH4, SDIO_D1, TSC_CHN11, TIM3_CH4, SPI2_MOSI, I2S2_SD, USART2_RX, COMP6_OUT, OPAMP3_INP, OPAMP4_INM and COMP3_INP4.
67	PA8	bidirectional	FT I/O (5 V tolerant, fail-safe); alternate functions USART1_CK, TIM1_CH1 and MCO.
68	PA9	bidirectional	FT I/O (5 V tolerant, fail-safe); alternate functions USART1_TX, TIM1_CH2, TSC_DOUT and I2C4_SCL.
69	PA10	bidirectional	FT I/O (5 V tolerant, fail-safe); alternate functions USART1_RX, TIM1_CH3 and I2C4_SDA.
70	PA11	bidirectional	FT I/O (5 V tolerant, fail-safe); alternate functions USART1_CTS, USBDM, CAN1_RX, TIM1_CH4, COMP1_OUT and COMP5_OUT.
71	PA12	bidirectional	FT I/O (5 V tolerant, fail-safe); alternate functions USART1_RTS, USBDP, CAN1_TX, TIM1_ETR, COMP2_OUT and COMP6_OUT.
72	PA13	bidirectional	FT I/O (5 V tolerant, fail-safe); default function JTMS-SWDIO (reset state) with alternate function UART4_TX.
73	NC	unconnected	Pin marked 'Not Connect' in the LQFP100 pin definition table.
74	VSS_2	power_in	Digital ground pin; all VSS pins must be connected to the external ground system.
75	VDD_2	power_in	I/O and internal regulator supply, 1.8 to 3.6 V.
76	PA14	bidirectional	FT I/O (5 V tolerant, fail-safe); default function JTCK-SWCLK (reset state) with alternate function UART4_RX.
77	PA15	bidirectional	FT I/O (5 V tolerant, fail-safe); default function JTDI (reset state, pull-up) with alternate functions SPI3_NSS, I2S3_WS, TIM2_CH1_ETR, SPI1_NSS, USART2_CTS and TIM8_CH1N.
78	PC10	bidirectional	TTa I/O (3.3 V tolerant, analog-capable) with fail-safe; alternate functions UART4_TX, SDIO_D2, TSC_CHN12, USART3_TX, SPI3_SCK, I2S3_CK, QSPI_NSS and COMP3_OUT.
79	PC11	bidirectional	TTa I/O (3.3 V tolerant, analog-capable) with fail-safe; alternate functions UART4_RX, SDIO_D3, TSC_CHN13, USART3_RX, SPI3_MISO, QSPI_SCK and COMP4_OUT.
80	PC12	bidirectional	TTa I/O (3.3 V tolerant, analog-capable) with fail-safe; alternate functions UART5_TX, SDIO_CK, TSC_CHN14, USART3_CK, SPI3_MOSI, I2S3_SD, QSPI_IO0 and TIM8_CH2N.
81	PD0	bidirectional	FT I/O (5 V tolerant, fail-safe); inherent PD0 function on LQFP100 (no remap needed); alternate functions CAN1_RX, UART4_TX and QSPI_IO1.
82	PD1	bidirectional	FT I/O (5 V tolerant, fail-safe); inherent PD1 function on LQFP100 (no remap needed); alternate functions CAN1_TX, UART4_RX and QSPI_IO2.
83	PD2	bidirectional	TTa I/O (3.3 V tolerant, analog-capable) with fail-safe; alternate functions TIM3_ETR, UART5_RX, SDIO_CMD, TSC_CHN15, SPI3_NSS, I2S3_WS, QSPI_IO3 and TIM8_CH3N.
84	PD3	bidirectional	FT I/O (5 V tolerant, fail-safe); alternate function USART2_CTS.
85	PD4	bidirectional	TTa I/O (3.3 V tolerant, analog-capable) with fail-safe; alternate functions TSC_CHN16 and USART2_RTS.
86	PD5	bidirectional	TTa I/O (3.3 V tolerant, analog-capable) with fail-safe; alternate functions TSC_CHN17 and USART2_TX.
87	PD6	bidirectional	TTa I/O (3.3 V tolerant, analog-capable) with fail-safe; alternate functions TSC_CHN18 and USART2_RX.
88	PD7	bidirectional	TTa I/O (3.3 V tolerant, analog-capable) with fail-safe; alternate functions TSC_CHN19 and USART2_CK.
89	PB3	bidirectional	FT I/O (5 V tolerant, fail-safe); default function JTDO (reset state) with remap PB3, TRACESWO, TIM2_CH2, SPI1_SCK, USART2_RTS and TIM8_BKIN.
90	PB4	bidirectional	FT I/O (5 V tolerant, fail-safe); default function NJTRST (reset state) with remap PB4, TIM3_CH1, SPI1_MISO, USART2_TX and TIM8_ETR.
91	PB5	bidirectional	FT I/O (5 V tolerant, fail-safe); alternate functions I2C1_SMBA, SPI3_MOSI, I2S3_SD, TIM3_CH2, SPI1_MOSI, CAN2_RX, USART2_RX and TIM1_BKIN.
92	PB6	bidirectional	TTa I/O (3.3 V tolerant, analog-capable) with fail-safe; alternate functions I2C1_SCL, TIM4_CH1, TSC_CHN20, USART1_TX, CAN2_TX and COMP5_OUT.
93	PB7	bidirectional	TTa I/O (3.3 V tolerant, analog-capable) with fail-safe; alternate functions I2C1_SDA, TIM4_CH2, TSC_CHN21, USART1_RX and COMP6_OUT.
94	BOOT0	input	Boot-mode selection input (with BOOT1/PB2) read at start-up to choose Flash, system memory or internal SRAM boot.
95	PB8	bidirectional	TTa I/O (3.3 V tolerant, analog-capable) with fail-safe; alternate functions TIM4_CH3, SDIO_D4, COMP1_OUT, TSC_CN22, I2C1_SCL, CAN1_RX and UART5_TX.
96	PB9	bidirectional	TTa I/O (3.3 V tolerant, analog-capable) with fail-safe; alternate functions TIM4_CH4, SDIO_D5, COMP2_OUT, TSC_CHN23, I2C1_SDA, CAN1_TX and UART5_RX.
97	PE0	bidirectional	FT I/O (5 V tolerant, fail-safe); alternate function TIM4_ETR.
98	PE1	bidirectional	FT I/O (5 V tolerant, fail-safe); no alternate function listed in the pin table.
99	VSS_3	power_in	Digital ground pin; all VSS pins must be connected to the external ground system.
100	VDD_3	power_in	I/O and internal regulator supply, 1.8 to 3.6 V.

Key specifications

Parameter	Value
Manufacturer	Nations Technologies Inc
Package	LQFP-100(14x14)
Category	Embedded Processors & Controllers
Pins	100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Input low-level voltage	VIL			0.8	V	VDD=3.3V	58
Input low-level voltage	VIL			0.7	V	VDD=2.5V	58
Input low-level voltage	VIL			0.3	*VDD	VDD=1.8V	58
Input high-level voltage	VIH	2			V	VDD=3.3V	58
Input high-level voltage	VIH	1.7			V	VDD=2.5V	58
Input high-level voltage	VIH	0.7			*VDD	VDD=1.8V	58
Schmitt trigger voltage hysteresis	Vhys	200			mV	VDD=3.3V	58
Schmitt trigger voltage hysteresis	Vhys	0.1			*VDD	VDD=1.8V; at least 100mV	58
Input leakage current	Ilkg	-1		1	μA	VDD=Maximum; VPAD=0 or VPAD=VDD	58
Weak pull-up equivalent resistance	RPU	100		160	kΩ	VDD=3.3V; VIN=VSS	58
Weak pull-down equivalent resistance	RPD	100		160	kΩ	VDD=3.3V; VIN=VDD; PA11, PA12, PA14, PB2 excluded	58
I/O pin capacitance	CIO			0.1	pF		58
Output low-level voltage	VOL			0.4	V	VDD=3.3V; IOL=2/4/8/12	59
Output low-level voltage	VOL			0.2	*VDD	VDD=1.8V; IOL=2/4/8/12	59
Output high-level voltage	VOH	2.4			V	VDD=3.3V; IOH=2/4/8/12; PC13, PC14, PC15 excluded	59
Output high-level voltage	VOH	1.8			V	VDD=2.5V; IOH=2/4/8/12; PC13, PC14, PC15 excluded	59
Output high-level voltage	VOH	0.8			*VDD	VDD=1.8V; IOH=2/4/8/12	59
NRST input low-level voltage	VIL(NRST)			0.8	V	VDD=3.3V	60
NRST input high-level voltage	VIH(NRST)	2			V	VDD=3.3V	60
NRST weak pull-up equivalent resistance	RPU	30	50	70	kΩ	VIN=VIH	60
NRST input filtered pulse	VF(NRST)			100	ns		60
NRST input non-filtered pulse	VNF(NRST)	300			ns		60
Timer resolution time	tres(TIM)	1			tTIMxCLK		61
Timer resolution time	tres(TIM)	6.95			ns	fTIMxCLK=144MHz	61
Timer external clock frequency on CH1 to CH4	fEXT	0			MHz		61
Timer external clock frequency on CH1 to CH4	fEXT	0		72	MHz	fTIMxCLK=144MHz	61
Timer resolution	ResTIM			16	位		61
16-bit counter clock period (internal clock selected)	tCOUNTER	1		65536	tTIMxCLK	internal clock selected	61
16-bit counter clock period (internal clock selected)	tCOUNTER	0.00695		455	μs	fTIMxCLK=144MHz	61
Maximum possible count	tMAX_COUNT			29.8	s	fTIMxCLK=144MHz	61
SPI clock frequency	fSCLK			36	MHz	Master mode	63
I2C interface frequency	fSCL	0		100	KHz	Standard mode	61
I2C interface frequency	fSCL	0		400	KHz	Fast mode	61
I2C interface frequency	fSCL	0		1000	KHz	Fast+ mode	61
ADC supply voltage	VDDA	1.8		3.6	V		73
ADC positive reference voltage	VREF+	1.8			V		73
ADC clock frequency	fADC			72	MHz		73
ADC sampling rate	fs			5	MHz		73
ADC sampling switch resistance	RADC			70	ohm	Fast channel, 3.3V	73
ADC sampling switch resistance	RADC			0.25	kΩ	Slow channel, 3.3V	73
ADC sampling time	tS	0.0208		8.35	us	fADC=72 MHz (fast channel)	73
ADC sampling time	tS	0.0625		8.35	us	fADC=72 MHz (slow channel)	73
ADC power-up time	tSTAB	0	0	20	μs		73
ADC total composite error	ET	-5	1.3	5	LSB	fHCLK=72MHz, fADC=72MHz, sample rate=1.75M sps, VDDA=3.3V, TA=25°C, VREF+=VDDA; measured after calibration	73
ADC offset error	EO	-2	1	2	LSB	Same as ET; measured after calibration	73
ADC differential linearity error	ED	-1	0.7	1	LSB	Same as ET; measured after calibration	73
ADC integral linearity error	EL	-2	0.8	2	LSB	Same as ET; measured after calibration	73
SD/MMC data transfer clock frequency	fPP			48	MHz	CL ≤ 30pF	71
USB transceiver startup time	tSTARTUP			1	μs		71
USB operating voltage	VDD	3		3.6	V		71
USB static output low-level voltage	VOL			0.3	V	RL of 1.5kΩ to 3.6V	71
USB static output high-level voltage	VOH	2.8		3.6	V	RL of 15kΩ to VSS	71
USB differential input sensitivity	VDI	0.2			V	I(USBDP, USBDM)	71
USB differential common-mode range	VCM	0.8		2.5	V	Includes VDI range	71
USB rise time	tr	4		20	ns	CL ≤ 50pF	72
USB fall time	tf	4		20	ns	CL ≤ 50pF	72
USB output series matching resistance	Rs	27		39	Ohm	Matching resistor external, placed near chip pin	72

CAD (KiCad official)

Symbol: N32G455VEL7
Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
3D model files: n32g455vel7-etched.step / n32g455vel7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); n32g455vel7.step / n32g455vel7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Nations Technologies Inc datasheet (87 pp, sha256 d7532f973fd1b7fb, retrieved 2026-10-18, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# N32G455VEL7

**Nations Technologies Inc** · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

N32G455VEL7 from Nations Technologies Inc, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PE2 | bidirectional | GPIO PE2, FT I/O (5 V tolerant, fail-safe); alternate functions TRACECK and UART6_TX. |
| 2 | PE3 | bidirectional | GPIO PE3, FT I/O (5 V tolerant, fail-safe); alternate functions TRACED0 and UART6_RX. |
| 3 | PE4 | bidirectional | GPIO PE4, FT I/O (5 V tolerant, fail-safe); alternate function TRACED1. |
| 4 | PE5 | bidirectional | GPIO PE5, FT I/O (5 V tolerant, fail-safe); alternate function TRACED2. |
| 5 | PE6 | bidirectional | GPIO PE6, FT I/O (5 V tolerant, fail-safe); alternate function TRACED3. |
| 6 | VBAT | power_in | Backup-domain supply, 1.8 to 3.6 V, powers the RTC, the 32.768 kHz oscillator and the backup registers when VDD is off. |
| 7 | PC13-TAMPER-RTC | bidirectional | TC I/O (standard 3.3 V) powered through a power switch limited to about 3 mA; as an output it is limited to one pin at a time, 2 MHz mode, 30 pF load and no current-source use; alternate function TAMPER-RTC. |
| 8 | PC14-OSC32_IN | bidirectional | TC I/O (standard 3.3 V) powered through a power switch limited to about 3 mA, with the same output restrictions as PC13 (one output at a time, 2 MHz, 30 pF, no LED drive); alternate function OSC32_IN. |
| 9 | PC15-OSC32_OUT | bidirectional | TC I/O (standard 3.3 V) powered through a power switch limited to about 3 mA, with the same output restrictions as PC13 (one output at a time, 2 MHz, 30 pF, no LED drive); alternate function OSC32_OUT. |
| 10 | VSS_5 | power_in | Digital ground pin; all VSS pins must be connected to the external ground system. |
| 11 | VDD_5 | power_in | I/O and internal regulator supply, 1.8 to 3.6 V. |
| 12 | OSC_IN | input | HSE oscillator input for a 4 to 32 MHz crystal/resonator or external clock; also FT/TC level pin (OSC_IN). |
| 13 | OSC_OUT | output | HSE oscillator output for the 4 to 32 MHz crystal/resonator circuit. |
| 14 | NRST | input | Active-low external reset input with an internal pull-up of 30 to 70 kOhm; a 100 ns input filter pulse is specified. |
| 15 | PC0 | bidirectional | TTa I/O (3.3 V tolerant, analog-capable); alternate functions ADC12_IN6, I2C3_SCL, COMP7_INM and UART6_TX. |
| 16 | PC1 | bidirectional | TTa I/O (3.3 V tolerant, analog-capable); alternate functions ADC12_IN7, I2C3_SDA, COMP7_INP and UART6_RX. |
| 17 | PC2 | bidirectional | TTa I/O (3.3 V tolerant, analog-capable); alternate functions ADC12_IN8, COMP7_OUT, UART7_TX, SPI3_NSS and I2S3_WS. |
| 18 | PC3 | bidirectional | TTa I/O (3.3 V tolerant, analog-capable); alternate functions ADC12_IN9, UART7_RX, SPI3_SCK, I2S3_CK, OPAMP3_VINP, OPAMP4_VINP and COMP5_INP. |
| 19 | VSSA | power_in | Ground for the analog section (ADC, DAC, OPAMP, COMP, TSC); VSSA must be connected to VSS. |
| 20 | VREF- | power_in | Negative reference input for the ADC; the ADC input range is VREF- ≤ VIN ≤ VREF+. |
| 21 | VREF+ | power_in | Positive reference voltage input for the ADC and DAC; VREF+ must always be lower than VDDA. |
| 22 | VDDA | power_in | Analog supply for ADC, DAC, OPAMP, COMP and TSC, 1.8 to 3.6 V, and it must be the same supply as VDD (up to 300 mV difference). |
| 23 | PA0-WKUP | bidirectional | TTa I/O (3.3 V tolerant, analog-capable); WKUP wake-up input (rising edge wakes from STANDBY); alternate functions include ADC1_IN1, USART2_CTS, TIM2_CH1_ETR, TIM5_CH1, TIM8_ETR, COMP1_OUT, COMP1_INM and SPI3_MISO. |
| 24 | PA1 | bidirectional | TTa I/O (3.3 V tolerant, analog-capable); alternate functions USART2_RTS, ADC1_IN2, TIM5_CH2, TIM2_CH2, COMP1_INP, OPAMP1_VINP, OPAMP3_VINP, SPI3_MOSI and I2S3_SD. |
| 25 | PA2 | bidirectional | TTa I/O (3.3 V tolerant, analog-capable); alternate functions USART2_TX, TIM5_CH3, ADC12_IN11, TIM2_CH3, COMP2_OUT, OPAMP1_INM and OPAMP2_INM. |
| 26 | PA3 | bidirectional | TTa I/O (3.3 V tolerant, analog-capable); alternate functions USART2_RX, TIM5_CH4, ADC1_IN4, TIM2_CH4, OPAMP1_VINM, OPAMP1_VINP and COMP5_INP. |
| 27 | VSS_4 | power_in | Digital ground pin; all VSS pins must be connected to the external ground system. |
| 28 | VDD_4 | power_in | I/O and internal regulator supply, 1.8 to 3.6 V. |
| 29 | PA4 | bidirectional | TTa I/O (3.3 V tolerant, analog-capable); alternate functions SPI1_NSS, USART2_CK, DAC_OUT1, ADC2_IN1, QSPI_NSS, TSC_CHN0, several COMP inverting inputs, OPAMP4_VINP and I2C2_SCL. |
| 30 | PA5 | bidirectional | TTa I/O (3.3 V tolerant, analog-capable); alternate functions SPI1_SCK, DAC_OUT2, ADC2_IN2, QSPI_SCK, TSC_CHN1, several COMP inverting inputs, OPAMP1_VINP, OPAMP2_VINM, OPAMP3_VINP and I2C2_SDA. |
| 31 | PA6 | bidirectional | TTa I/O (3.3 V tolerant, analog-capable); alternate functions SPI1_MISO, TIM8_BKIN, ADC1_IN3, TIM3_CH1, COMP1_OUT, QSPI_IO0, TIM1_BKIN, OPAMP1_VOUT and COMP2_OUT. |
| 32 | PA7 | bidirectional | TTa I/O (3.3 V tolerant, analog-capable); alternate functions SPI1_MOSI, TIM8_CH1N, ADC2_IN4, TIM3_CH2, QSPI_IO1, COMP2_OUT, TIM1_CH1N, COMP2_INP, OPAMP1_VINP, OPAMP2_VINP and COMP6_INM. |
| 33 | PC4 | bidirectional | TTa I/O (3.3 V tolerant, analog-capable); alternate functions ADC2_IN5, QSPI_IO2, UART7_TX, I2C3_SCL, OPAMP3_VINM, COMP4_INM and COMP5_INP. |
| 34 | PC5 | bidirectional | TTa I/O (3.3 V tolerant, analog-capable); alternate functions ADC2_IN12, QSPI_IO3, UART7_RX, I2C3_SDA, OPAMP4_VINP, COMP4_OUT and COMP6_INP. |
| 35 | PB0 | bidirectional | TTa I/O (3.3 V tolerant, analog-capable); alternate functions ADC3_IN12, TIM3_CH3, TIM8_CH2N, TIM1_CH2N, UART6_TX, OPAMP2_VINP, COMP3_INP and COMP5_OUT. |
| 36 | PB1 | bidirectional | TTa I/O (3.3 V tolerant, analog-capable); alternate functions ADC2_IN3, TIM3_CH4, TIM8_CH3N, COMP4_OUT, TIM1_CH3N, OPAMP2_VOUT, UART6_RX, COMP2_INM and COMP1_OUT. |
| 37 | PB2/BOOT1 | bidirectional | TTa I/O (3.3 V tolerant, analog-capable); BOOT1 boot-mode function; alternate functions ADC2_IN13, UART4_TX and SPI1_NSS. |
| 38 | PE7 | bidirectional | TTa I/O (3.3 V tolerant, analog-capable); alternate functions ADC3_IN13, TIM1_ETR, UART4_RX, SPI1_SCK and COMP3_INM. |
| 39 | PE8 | bidirectional | TTa I/O (3.3 V tolerant, analog-capable); alternate functions ADC34_IN6, TIM1_CH1N, UART5_TX, SDIO_D0, SPI1_MISO, OPAMP2_INP and COMP2_INM. |
| 40 | PE9 | bidirectional | TTa I/O (3.3 V tolerant, analog-capable); alternate functions ADC3_IN2, TIM1_CH1, UART5_RX, SDIO_D1 and SPI1_MOSI. |
| 41 | PE10 | bidirectional | TTa I/O (3.3 V tolerant, analog-capable); alternate functions ADC3_IN14, TIM1_CH2N, SDIO_D2, SPI2_NSS and I2S2_WS. |
| 42 | PE11 | bidirectional | TTa I/O (3.3 V tolerant, analog-capable); alternate functions ADC3_IN15, TIM1_CH2, SDIO_D3, SPI2_SCK and I2S2_CK. |
| 43 | PE12 | bidirectional | TTa I/O (3.3 V tolerant, analog-capable); alternate functions ADC3_IN4, TIM1_CH3N, SDIO_CK and SPI2_MISO. |
| 44 | PE13 | bidirectional | TTa I/O (3.3 V tolerant, analog-capable); alternate functions ADC3_IN3, TIM1_CH3, SPI2_MOSI, I2S2_SD and SDIO_CMD. |
| 45 | PE14 | bidirectional | TTa I/O (3.3 V tolerant, analog-capable); alternate functions ADC4_IN1 and TIM1_CH4. |
| 46 | PE15 | bidirectional | TTa I/O (3.3 V tolerant, analog-capable); alternate functions ADC4_IN2 and TIM1_BKIN. |
| 47 | PB10 | bidirectional | TTa I/O (3.3 V tolerant, analog-capable) with Yes fail-safe; alternate functions I2C2_SCL, USART3_TX, TIM2_CH3, COMP5_INM, OPAMP3_VINM, OPAMP4_VINM, COMP1_INP and COMP3_OUT. |
| 48 | PB11 | bidirectional | TTa I/O (3.3 V tolerant, analog-capable); alternate functions I2C2_SDA, USART3_RX, ADC3_IN1, TIM2_CH4, OPAMP3_VOUT, COMP2_INP and COMP5_OUT. |
| 49 | VSS_1 | power_in | Digital ground pin; all VSS pins must be connected to the external ground system. |
| 50 | VDD_1 | power_in | I/O and internal regulator supply, 1.8 to 3.6 V. |
| 51 | PB12 | bidirectional | TTa I/O (3.3 V tolerant, analog-capable); alternate functions SPI2_NSS, I2S2_WS, I2C2_SMBA, USART3_CK, TIM1_BKIN, CAN2_RX, ADC4_IN3, COMP3_INM, OPAMP4_VOUT and COMP4_OUT. |
| 52 | PB13 | bidirectional | TTa I/O (3.3 V tolerant, analog-capable); alternate functions SPI2_SCK, I2S2_CK, USART3_CTS, TIM1_CH1N, CAN2_TX, ADC3_IN5, UART5_TX and COMP4_INM. |
| 53 | PB14 | bidirectional | TTa I/O (3.3 V tolerant, analog-capable); alternate functions SPI2_MISO, TIM1_CH2N, USART3_RTS, ADC4_IN4, TSC_CHN2, COMP3_INP and UART5_RX. |
| 54 | PB15 | bidirectional | TTa I/O (3.3 V tolerant, analog-capable); alternate functions SPI2_MOSI, I2S2_SD, TIM1_CH3N, ADC4_IN5, TSC_CHN3 and COMP4_INP. |
| 55 | PD8 | bidirectional | TTa I/O (3.3 V tolerant, analog-capable); alternate functions ADC4_IN12, TSC_CHN4, USART3_TX, OPAMP4_VINM, SPI3_NSS, I2S3_WS, CAN1_RX, and COMP6_INM. |
| 56 | PD9 | bidirectional | TTa I/O (3.3 V tolerant, analog-capable); alternate functions ADC4_IN13, TSC_CHN5, USART3_RX, SPI3_SCK, I2S3_CK, CAN1_TX and COMP6_INP. |
| 57 | PD10 | bidirectional | TTa I/O (3.3 V tolerant, analog-capable); alternate functions ADC34_IN7, USART3_CK, CAN2_RX and COMP5_INM. |
| 58 | PD11 | bidirectional | TTa I/O (3.3 V tolerant, analog-capable); alternate functions ADC34_IN8, TSC_CHN6, USART3_CTS, CAN2_TX and SPI3_MISO. |
| 59 | PD12 | bidirectional | TTa I/O (3.3 V tolerant, analog-capable); alternate functions ADC34_IN9, TSC_CHN7, TIM4_CH1, USART3_RTS, SPI3_MOSI, I2S3_SD and COMP7_OUT. |
| 60 | PD13 | bidirectional | TTa I/O (3.3 V tolerant, analog-capable); alternate functions ADC34_IN10 and TIM4_CH2. |
| 61 | PD14 | bidirectional | TTa I/O (3.3 V tolerant, analog-capable); alternate functions ADC34_IN11, TIM4_CH3, I2C4_SCL and TIM8_CH1. |
| 62 | PD15 | bidirectional | FT I/O (5 V tolerant, fail-safe); alternate functions TIM4_CH4, I2C4_SDA and TIM8_CH2. |
| 63 | PC6 | bidirectional | TTa I/O (3.3 V tolerant, analog-capable) with fail-safe; alternate functions I2S2_MCK, TIM3_CH1, TIM8_CH1, SDIO_D6, I2C4_SCL, TSC_CHN8, SPI2_NSS, I2S2_WS and USART2_CTS. |
| 64 | PC7 | bidirectional | TTa I/O (3.3 V tolerant, analog-capable) with fail-safe; alternate functions I2S3_MCK, TIM8_CH2, SDIO_D7, I2C4_SDA, TSC_CHN9, TIM3_CH2, SPI2_SCK, I2S2_CK and USART2_RTS. |
| 65 | PC8 | bidirectional | TTa I/O (3.3 V tolerant, analog-capable) with fail-safe; alternate functions TIM8_CH3, SDIO_D0, TSC_CHN10, TIM3_CH3, SPI2_MISO and USART2_TX. |
| 66 | PC9 | bidirectional | TTa I/O (3.3 V tolerant, analog-capable) with fail-safe; alternate functions TIM8_CH4, SDIO_D1, TSC_CHN11, TIM3_CH4, SPI2_MOSI, I2S2_SD, USART2_RX, COMP6_OUT, OPAMP3_INP, OPAMP4_INM and COMP3_INP4. |
| 67 | PA8 | bidirectional | FT I/O (5 V tolerant, fail-safe); alternate functions USART1_CK, TIM1_CH1 and MCO. |
| 68 | PA9 | bidirectional | FT I/O (5 V tolerant, fail-safe); alternate functions USART1_TX, TIM1_CH2, TSC_DOUT and I2C4_SCL. |
| 69 | PA10 | bidirectional | FT I/O (5 V tolerant, fail-safe); alternate functions USART1_RX, TIM1_CH3 and I2C4_SDA. |
| 70 | PA11 | bidirectional | FT I/O (5 V tolerant, fail-safe); alternate functions USART1_CTS, USBDM, CAN1_RX, TIM1_CH4, COMP1_OUT and COMP5_OUT. |
| 71 | PA12 | bidirectional | FT I/O (5 V tolerant, fail-safe); alternate functions USART1_RTS, USBDP, CAN1_TX, TIM1_ETR, COMP2_OUT and COMP6_OUT. |
| 72 | PA13 | bidirectional | FT I/O (5 V tolerant, fail-safe); default function JTMS-SWDIO (reset state) with alternate function UART4_TX. |
| 73 | NC | unconnected | Pin marked 'Not Connect' in the LQFP100 pin definition table. |
| 74 | VSS_2 | power_in | Digital ground pin; all VSS pins must be connected to the external ground system. |
| 75 | VDD_2 | power_in | I/O and internal regulator supply, 1.8 to 3.6 V. |
| 76 | PA14 | bidirectional | FT I/O (5 V tolerant, fail-safe); default function JTCK-SWCLK (reset state) with alternate function UART4_RX. |
| 77 | PA15 | bidirectional | FT I/O (5 V tolerant, fail-safe); default function JTDI (reset state, pull-up) with alternate functions SPI3_NSS, I2S3_WS, TIM2_CH1_ETR, SPI1_NSS, USART2_CTS and TIM8_CH1N. |
| 78 | PC10 | bidirectional | TTa I/O (3.3 V tolerant, analog-capable) with fail-safe; alternate functions UART4_TX, SDIO_D2, TSC_CHN12, USART3_TX, SPI3_SCK, I2S3_CK, QSPI_NSS and COMP3_OUT. |
| 79 | PC11 | bidirectional | TTa I/O (3.3 V tolerant, analog-capable) with fail-safe; alternate functions UART4_RX, SDIO_D3, TSC_CHN13, USART3_RX, SPI3_MISO, QSPI_SCK and COMP4_OUT. |
| 80 | PC12 | bidirectional | TTa I/O (3.3 V tolerant, analog-capable) with fail-safe; alternate functions UART5_TX, SDIO_CK, TSC_CHN14, USART3_CK, SPI3_MOSI, I2S3_SD, QSPI_IO0 and TIM8_CH2N. |
| 81 | PD0 | bidirectional | FT I/O (5 V tolerant, fail-safe); inherent PD0 function on LQFP100 (no remap needed); alternate functions CAN1_RX, UART4_TX and QSPI_IO1. |
| 82 | PD1 | bidirectional | FT I/O (5 V tolerant, fail-safe); inherent PD1 function on LQFP100 (no remap needed); alternate functions CAN1_TX, UART4_RX and QSPI_IO2. |
| 83 | PD2 | bidirectional | TTa I/O (3.3 V tolerant, analog-capable) with fail-safe; alternate functions TIM3_ETR, UART5_RX, SDIO_CMD, TSC_CHN15, SPI3_NSS, I2S3_WS, QSPI_IO3 and TIM8_CH3N. |
| 84 | PD3 | bidirectional | FT I/O (5 V tolerant, fail-safe); alternate function USART2_CTS. |
| 85 | PD4 | bidirectional | TTa I/O (3.3 V tolerant, analog-capable) with fail-safe; alternate functions TSC_CHN16 and USART2_RTS. |
| 86 | PD5 | bidirectional | TTa I/O (3.3 V tolerant, analog-capable) with fail-safe; alternate functions TSC_CHN17 and USART2_TX. |
| 87 | PD6 | bidirectional | TTa I/O (3.3 V tolerant, analog-capable) with fail-safe; alternate functions TSC_CHN18 and USART2_RX. |
| 88 | PD7 | bidirectional | TTa I/O (3.3 V tolerant, analog-capable) with fail-safe; alternate functions TSC_CHN19 and USART2_CK. |
| 89 | PB3 | bidirectional | FT I/O (5 V tolerant, fail-safe); default function JTDO (reset state) with remap PB3, TRACESWO, TIM2_CH2, SPI1_SCK, USART2_RTS and TIM8_BKIN. |
| 90 | PB4 | bidirectional | FT I/O (5 V tolerant, fail-safe); default function NJTRST (reset state) with remap PB4, TIM3_CH1, SPI1_MISO, USART2_TX and TIM8_ETR. |
| 91 | PB5 | bidirectional | FT I/O (5 V tolerant, fail-safe); alternate functions I2C1_SMBA, SPI3_MOSI, I2S3_SD, TIM3_CH2, SPI1_MOSI, CAN2_RX, USART2_RX and TIM1_BKIN. |
| 92 | PB6 | bidirectional | TTa I/O (3.3 V tolerant, analog-capable) with fail-safe; alternate functions I2C1_SCL, TIM4_CH1, TSC_CHN20, USART1_TX, CAN2_TX and COMP5_OUT. |
| 93 | PB7 | bidirectional | TTa I/O (3.3 V tolerant, analog-capable) with fail-safe; alternate functions I2C1_SDA, TIM4_CH2, TSC_CHN21, USART1_RX and COMP6_OUT. |
| 94 | BOOT0 | input | Boot-mode selection input (with BOOT1/PB2) read at start-up to choose Flash, system memory or internal SRAM boot. |
| 95 | PB8 | bidirectional | TTa I/O (3.3 V tolerant, analog-capable) with fail-safe; alternate functions TIM4_CH3, SDIO_D4, COMP1_OUT, TSC_CN22, I2C1_SCL, CAN1_RX and UART5_TX. |
| 96 | PB9 | bidirectional | TTa I/O (3.3 V tolerant, analog-capable) with fail-safe; alternate functions TIM4_CH4, SDIO_D5, COMP2_OUT, TSC_CHN23, I2C1_SDA, CAN1_TX and UART5_RX. |
| 97 | PE0 | bidirectional | FT I/O (5 V tolerant, fail-safe); alternate function TIM4_ETR. |
| 98 | PE1 | bidirectional | FT I/O (5 V tolerant, fail-safe); no alternate function listed in the pin table. |
| 99 | VSS_3 | power_in | Digital ground pin; all VSS pins must be connected to the external ground system. |
| 100 | VDD_3 | power_in | I/O and internal regulator supply, 1.8 to 3.6 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Nations Technologies Inc |
| Package | LQFP-100(14x14) |
| Category | Embedded Processors & Controllers |
| Pins | 100 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input low-level voltage | VIL |  |  | 0.8 | V | VDD=3.3V | 58 |
| Input low-level voltage | VIL |  |  | 0.7 | V | VDD=2.5V | 58 |
| Input low-level voltage | VIL |  |  | 0.3 | *VDD | VDD=1.8V | 58 |
| Input high-level voltage | VIH | 2 |  |  | V | VDD=3.3V | 58 |
| Input high-level voltage | VIH | 1.7 |  |  | V | VDD=2.5V | 58 |
| Input high-level voltage | VIH | 0.7 |  |  | *VDD | VDD=1.8V | 58 |
| Schmitt trigger voltage hysteresis | Vhys | 200 |  |  | mV | VDD=3.3V | 58 |
| Schmitt trigger voltage hysteresis | Vhys | 0.1 |  |  | *VDD | VDD=1.8V; at least 100mV | 58 |
| Input leakage current | Ilkg | -1 |  | 1 | μA | VDD=Maximum; VPAD=0 or VPAD=VDD | 58 |
| Weak pull-up equivalent resistance | RPU | 100 |  | 160 | kΩ | VDD=3.3V; VIN=VSS | 58 |
| Weak pull-down equivalent resistance | RPD | 100 |  | 160 | kΩ | VDD=3.3V; VIN=VDD; PA11, PA12, PA14, PB2 excluded | 58 |
| I/O pin capacitance | CIO |  |  | 0.1 | pF |  | 58 |
| Output low-level voltage | VOL |  |  | 0.4 | V | VDD=3.3V; IOL=2/4/8/12 | 59 |
| Output low-level voltage | VOL |  |  | 0.2 | *VDD | VDD=1.8V; IOL=2/4/8/12 | 59 |
| Output high-level voltage | VOH | 2.4 |  |  | V | VDD=3.3V; IOH=2/4/8/12; PC13, PC14, PC15 excluded | 59 |
| Output high-level voltage | VOH | 1.8 |  |  | V | VDD=2.5V; IOH=2/4/8/12; PC13, PC14, PC15 excluded | 59 |
| Output high-level voltage | VOH | 0.8 |  |  | *VDD | VDD=1.8V; IOH=2/4/8/12 | 59 |
| NRST input low-level voltage | VIL(NRST) |  |  | 0.8 | V | VDD=3.3V | 60 |
| NRST input high-level voltage | VIH(NRST) | 2 |  |  | V | VDD=3.3V | 60 |
| NRST weak pull-up equivalent resistance | RPU | 30 | 50 | 70 | kΩ | VIN=VIH | 60 |
| NRST input filtered pulse | VF(NRST) |  |  | 100 | ns |  | 60 |
| NRST input non-filtered pulse | VNF(NRST) | 300 |  |  | ns |  | 60 |
| Timer resolution time | tres(TIM) | 1 |  |  | tTIMxCLK |  | 61 |
| Timer resolution time | tres(TIM) | 6.95 |  |  | ns | fTIMxCLK=144MHz | 61 |
| Timer external clock frequency on CH1 to CH4 | fEXT | 0 |  |  | MHz |  | 61 |
| Timer external clock frequency on CH1 to CH4 | fEXT | 0 |  | 72 | MHz | fTIMxCLK=144MHz | 61 |
| Timer resolution | ResTIM |  |  | 16 | 位 |  | 61 |
| 16-bit counter clock period (internal clock selected) | tCOUNTER | 1 |  | 65536 | tTIMxCLK | internal clock selected | 61 |
| 16-bit counter clock period (internal clock selected) | tCOUNTER | 0.00695 |  | 455 | μs | fTIMxCLK=144MHz | 61 |
| Maximum possible count | tMAX_COUNT |  |  | 29.8 | s | fTIMxCLK=144MHz | 61 |
| SPI clock frequency | fSCLK |  |  | 36 | MHz | Master mode | 63 |
| I2C interface frequency | fSCL | 0 |  | 100 | KHz | Standard mode | 61 |
| I2C interface frequency | fSCL | 0 |  | 400 | KHz | Fast mode | 61 |
| I2C interface frequency | fSCL | 0 |  | 1000 | KHz | Fast+ mode | 61 |
| ADC supply voltage | VDDA | 1.8 |  | 3.6 | V |  | 73 |
| ADC positive reference voltage | VREF+ | 1.8 |  |  | V |  | 73 |
| ADC clock frequency | fADC |  |  | 72 | MHz |  | 73 |
| ADC sampling rate | fs |  |  | 5 | MHz |  | 73 |
| ADC sampling switch resistance | RADC |  |  | 70 | ohm | Fast channel, 3.3V | 73 |
| ADC sampling switch resistance | RADC |  |  | 0.25 | kΩ | Slow channel, 3.3V | 73 |
| ADC sampling time | tS | 0.0208 |  | 8.35 | us | fADC=72 MHz (fast channel) | 73 |
| ADC sampling time | tS | 0.0625 |  | 8.35 | us | fADC=72 MHz (slow channel) | 73 |
| ADC power-up time | tSTAB | 0 | 0 | 20 | μs |  | 73 |
| ADC total composite error | ET | -5 | 1.3 | 5 | LSB | fHCLK=72MHz, fADC=72MHz, sample rate=1.75M sps, VDDA=3.3V, TA=25°C, VREF+=VDDA; measured after calibration | 73 |
| ADC offset error | EO | -2 | 1 | 2 | LSB | Same as ET; measured after calibration | 73 |
| ADC differential linearity error | ED | -1 | 0.7 | 1 | LSB | Same as ET; measured after calibration | 73 |
| ADC integral linearity error | EL | -2 | 0.8 | 2 | LSB | Same as ET; measured after calibration | 73 |
| SD/MMC data transfer clock frequency | fPP |  |  | 48 | MHz | CL ≤ 30pF | 71 |
| USB transceiver startup time | tSTARTUP |  |  | 1 | μs |  | 71 |
| USB operating voltage | VDD | 3 |  | 3.6 | V |  | 71 |
| USB static output low-level voltage | VOL |  |  | 0.3 | V | RL of 1.5kΩ to 3.6V | 71 |
| USB static output high-level voltage | VOH | 2.8 |  | 3.6 | V | RL of 15kΩ to VSS | 71 |
| USB differential input sensitivity | VDI | 0.2 |  |  | V | I(USBDP, USBDM) | 71 |
| USB differential common-mode range | VCM | 0.8 |  | 2.5 | V | Includes VDI range | 71 |
| USB rise time | tr | 4 |  | 20 | ns | CL ≤ 50pF | 72 |
| USB fall time | tf | 4 |  | 20 | ns | CL ≤ 50pF | 72 |
| USB output series matching resistance | Rs | 27 |  | 39 | Ohm | Matching resistor external, placed near chip pin | 72 |

## CAD (KiCad official)

- Symbol: `N32G455VEL7`
- Footprint: `Package_QFP:LQFP-100_14x14mm_P0.5mm`
- 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
- 3D model files: `n32g455vel7-etched.step` / `n32g455vel7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `n32g455vel7.step` / `n32g455vel7.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Nations Technologies Inc datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589040480792793088) (87 pp, sha256 `d7532f973fd1b7fb`, retrieved 2026-10-18, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/n32g455vel7-datasheet.pdf)