component

N32G452VEL7

Public Made by Adom

by adom

Nations Technologies Inc Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersn32g452vel7factory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 7d ago
viewers n32g452vel7: viewers · Ray 7d ago
n32g452vel7-etched.glb Publish 0.1.0 · Ray 7d ago
n32g452vel7-etched.step n32g452vel7: factory component page (tier=lcsc) · Ray 7d ago
n32g452vel7-hero.glb n32g452vel7: hero GLB from the etched model (keeps the MPN mark) · Ray 7d ago
n32g452vel7-hero.overlay.json Publish 0.1.0 · Ray 7d ago
n32g452vel7.glb Publish 0.1.0 · Ray 7d ago
n32g452vel7.kicad_mod Publish 0.1.0 · Ray 7d ago
n32g452vel7.kicad_sym Publish 0.1.0 · Ray 7d ago
n32g452vel7.lbr Publish 0.1.0 · Ray 7d ago
n32g452vel7.step Publish 0.1.0 · Ray 7d ago
package.json Publish 0.1.0 · Ray 7d ago
page.json Set visibility: public · Ray 7d ago
README.md Publish 0.1.0 · Ray 7d ago

N32G452VEL7

Nations Technologies Inc · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

N32G452VEL7 from Nations Technologies Inc, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PE2 bidirectional GPIO with FT (5 V tolerant) level; reset default PE2, alternate functions TRACECK, XFMC_A23, UART6_TX.
2 PE3 bidirectional GPIO with FT (5 V tolerant) level; reset default PE3, alternate functions TRACED0, XFMC_A19, UART6_RX.
3 PE4 bidirectional GPIO with FT (5 V tolerant) level; reset default PE4, alternate functions TRACED1, XFMC_A20.
4 PE5 bidirectional GPIO with FT (5 V tolerant) level; reset default PE5, alternate functions TRACED2, XFMC_A21.
5 PE6 bidirectional GPIO with FT (5 V tolerant) level; reset default PE6, alternate functions TRACED3, XFMC_A22.
6 VBAT power_in Backup supply 1.8 V to 3.6 V for the RTC, the 32 kHz oscillator and backup registers when VDD is off.
7 PC13-TAMPER-RTC bidirectional GPIO (TC level) powered through a power switch limited to about 3 mA; when used as output only one of PC13/PC14/PC15 may toggle at a time, at 2 MHz max, 30 pF max load, and it cannot drive LEDs as a current source; alternate function TAMPER-RTC.
8 PC14-OSC32_IN bidirectional GPIO (TC level) with the same 3 mA power-switch and output limits as PC13; alternate function OSC32_IN for the 32.768 kHz LSE crystal.
9 PC15-OSC32_OUT bidirectional GPIO (TC level) with the same 3 mA power-switch and output limits as PC13; alternate function OSC32_OUT for the 32.768 kHz LSE crystal.
10 VSS_5 power_in Ground pin; all VSS pins must be connected to the ground of the supply system.
11 VDD_5 power_in Digital I/O and internal regulator supply, 1.8 V to 3.6 V.
12 OSC_IN input HSE oscillator input for a 4 MHz to 32 MHz crystal or external clock (OSC_IN input high level at least 0.7VDD).
13 OSC_OUT output HSE oscillator output for the 4 MHz to 32 MHz crystal or resonator.
14 NRST bidirectional Active-low reset pin with internal pull-up of 20 kΩ to 50 kΩ; a noise filter is recommended per the NRST protection figure.
15 PC0 bidirectional GPIO (TTa level); reset default PC0, alternate functions ADC12_IN6, I2C3_SCL, UART6_TX.
16 PC1 bidirectional GPIO (TTa level); reset default PC1, alternate functions ADC12_IN7, I2C3_SDA, UART6_RX.
17 PC2 bidirectional GPIO (TTa level); reset default PC2, alternate functions ADC12_IN8, UART7_TX, SPI3_NSS, I2S3_WS.
18 PC3 bidirectional GPIO (TTa level); reset default PC3, alternate functions ADC12_IN9, UART7_RX, SPI3_SCK, I2S3_CK.
19 VSSA power_in Analog ground for ADC, DAC, reset block, RC oscillators and PLL; must be connected to VSS.
20 VREF- power_in Negative ADC reference voltage input; ADC input range is VREF- ≤ VIN ≤ VREF+.
21 VREF+ power_in Positive ADC and DAC reference voltage input; ADC reference range 1.8 V to VDDA and VREF+ must always be lower than VDDA for the DAC.
22 VDDA power_in Analog supply 1.8 V to 3.6 V for ADC, DAC, reset block, RC oscillators and PLL; must be connected to VDD (up to 300 mV difference allowed).
23 PA0-WKUP bidirectional GPIO (TTa level); reset default PA0, WKUP wake-up input, alternate functions USART2_CTS, ADC1_IN1, TIM2_CH1_ETR, TIM5_CH1, TIM8_ETR, SPI3_MISO.
24 PA1 bidirectional GPIO (TTa level); reset default PA1, alternate functions USART2_RTS, ADC1_IN2, TIM5_CH2, TIM2_CH2, SPI3_MOSI, I2S3_SD.
25 PA2 bidirectional GPIO (TTa level); reset default PA2, alternate functions USART2_TX, TIM5_CH3, ADC12_IN11, TIM2_CH3.
26 PA3 bidirectional GPIO (TTa level); reset default PA3, alternate functions USART2_RX, TIM5_CH4, ADC1_IN4, TIM2_CH4.
27 VSS_4 power_in Ground pin; all VSS pins must be connected to the ground of the supply system.
28 VDD_4 power_in Digital I/O and internal regulator supply, 1.8 V to 3.6 V.
29 PA4 bidirectional GPIO (TTa level); reset default PA4, alternate functions SPI1_NSS, USART2_CK, DAC_OUT1, ADC2_IN1, QSPI_NSS, I2C2_SCL.
30 PA5 bidirectional GPIO (TTa level); reset default PA5, alternate functions SPI1_SCK, DAC_OUT2, ADC2_IN2, QSPI_SCK, I2C2_SDA.
31 PA6 bidirectional GPIO (TTa level); reset default PA6, alternate functions SPI1_MISO, TIM8_BKIN, ADC1_IN3, TIM3_CH1, QSPI_IO0, TIM1_BKIN.
32 PA7 bidirectional GPIO (TTa level); reset default PA7, alternate functions SPI1_MOSI, TIM8_CH1N, ADC2_IN4, TIM3_CH2, QSPI_IO1, TIM1_CH1N.
33 PC4 bidirectional GPIO (TTa level); reset default PC4, alternate functions ADC2_IN5, QSPI_IO2, UART7_TX, I2C3_SCL.
34 PC5 bidirectional GPIO (TTa level); reset default PC5, alternate functions ADC2_IN12, QSPI_IO3, UART7_RX, I2C3_SDA.
35 PB0 bidirectional GPIO (TTa level); reset default PB0, alternate functions TIM3_CH3, TIM8_CH2N, TIM1_CH2N, UART6_TX.
36 PB1 bidirectional GPIO (TTa level); reset default PB1, alternate functions ADC2_IN3, TIM3_CH4, TIM8_CH3N, TIM1_CH3N, UART6_RX.
37 PB2-BOOT1 bidirectional GPIO (TTa level); reset default PB2 (BOOT1 boot-mode select), alternate functions ADC2_IN13, UART4_TX, SPI1_NSS.
38 PE7 bidirectional GPIO (TTa level); reset default PE7, alternate functions XFMC_D4, TIM1_ETR, UART4_RX, SPI1_SCK.
39 PE8 bidirectional GPIO (TTa level); reset default PE8, alternate functions XFMC_D5, TIM1_CH1N, UART5_TX, SDIO_D0, SPI1_MISO.
40 PE9 bidirectional GPIO (TTa level); reset default PE9, alternate functions XFMC_D6, TIM1_CH1, UART5_RX, SDIO_D1, SPI1_MOSI.
41 PE10 bidirectional GPIO (TTa level); reset default PE10, alternate functions XFMC_D7, TIM1_CH2N, SDIO_D2, SPI2_NSS, I2S2_WS.
42 PE11 bidirectional GPIO (TTa level); reset default PE11, alternate functions XFMC_D8, TIM1_CH2, SDIO_D3, SPI2_SCK, I2S2_CK.
43 PE12 bidirectional GPIO (TTa level); reset default PE12, alternate functions XFMC_D9, TIM1_CH3N, SDIO_CK, SPI2_MISO.
44 PE13 bidirectional GPIO (TTa level); reset default PE13, alternate functions XFMC_D10, TIM1_CH3, SPI2_MOSI, I2S2_SD, SDIO_CMD.
45 PE14 bidirectional GPIO (TTa level); reset default PE14, alternate functions XFMC_D11, TIM1_CH4.
46 PE15 bidirectional GPIO (TTa level); reset default PE15, alternate functions XFMC_D12, TIM1_BKIN.
47 PB10 bidirectional GPIO (TTa level); reset default PB10, alternate functions I2C2_SCL, USART3_TX, TIM2_CH3, XFMC_D11.
48 PB11 bidirectional GPIO (TTa level); reset default PB11, alternate functions I2C2_SDA, USART3_RX, TIM2_CH4, XFMC_D12.
49 VSS_1 power_in Ground pin; all VSS pins must be connected to the ground of the supply system.
50 VDD_1 power_in Digital I/O and internal regulator supply, 1.8 V to 3.6 V.
51 PB12 bidirectional GPIO (TTa level); reset default PB12, alternate functions SPI2_NSS, I2S2_WS, I2C2_SMBA, USART3_CK, TIM1_BKIN, CAN2_RX.
52 PB13 bidirectional GPIO (TTa level); reset default PB13, alternate functions SPI2_SCK, I2S2_CK, USART3_CTS, TIM1_CH1N, CAN2_TX, UART5_TX.
53 PB14 bidirectional GPIO (TTa level); reset default PB14, alternate functions SPI2_MISO, TIM1_CH2N, USART3_RTS, UART5_RX.
54 PB15 bidirectional GPIO (TTa level); reset default PB15, alternate functions SPI2_MOSI, I2S2_SD, TIM1_CH3N.
55 PD8 bidirectional GPIO (TTa level); reset default PD8, alternate functions XFMC_D13, USART3_TX, SPI3_NSS, I2S3_WS, CAN1_RX.
56 PD9 bidirectional GPIO (TTa level); reset default PD9, alternate functions XFMC_D14, USART3_RX, SPI3_SCK, I2S3_CK, CAN1_TX.
57 PD10 bidirectional GPIO (TTa level); reset default PD10, alternate functions XFMC_D15, USART3_CK, CAN2_RX.
58 PD11 bidirectional GPIO (TTa level); reset default PD11, alternate functions XFMC_A16, USART3_CTS, CAN2_TX, SPI3_MISO.
59 PD12 bidirectional GPIO (TTa level); reset default PD12, alternate functions XFMC_A17, TIM4_CH1, USART3_RTS, SPI3_MOSI, I2S3_SD.
60 PD13 bidirectional GPIO (TTa level); reset default PD13, alternate functions XFMC_A18, TIM4_CH2.
61 PD14 bidirectional GPIO (TTa level); reset default PD14, alternate functions XFMC_D0, TIM4_CH3, I2C4_SCL, TIM8_CH1.
62 PD15 bidirectional GPIO with FT (5 V tolerant) level; reset default PD15, alternate functions XFMC_D1, TIM4_CH4, I2C4_SDA, TIM8_CH2.
63 PC6 bidirectional GPIO (TTa level); reset default PC6, alternate functions I2S2_MCK, TIM8_CH1, SDIO_D6, I2C4_SCL, TIM3_CH1, SPI2_NSS, I2S2_WS, USART2_CTS, XFMC_A16.
64 PC7 bidirectional GPIO (TTa level); reset default PC7, alternate functions I2S3_MCK, TIM8_CH2, SDIO_D7, I2C4_SDA, TIM3_CH2, SPI2_SCK, I2S2_CK, USART2_RTS, XFMC_A17.
65 PC8 bidirectional GPIO (TTa level); reset default PC8, alternate functions TIM8_CH3, SDIO_D0, TIM3_CH3, SPI2_MISO, USART2_TX.
66 PC9 bidirectional GPIO (TTa level); reset default PC9, alternate functions TIM8_CH4, SDIO_D1, TIM3_CH4, SPI2_MOSI, I2S2_SD, USART2_RX, XFMC_NOE.
67 PA8 bidirectional GPIO with FT (5 V tolerant) level; reset default PA8, alternate functions USART1_CK, TIM1_CH1, MCO.
68 PA9 bidirectional GPIO with FT (5 V tolerant) level; reset default PA9, alternate functions USART1_TX, TIM1_CH2, I2C4_SCL.
69 PA10 bidirectional GPIO with FT (5 V tolerant) level; reset default PA10, alternate functions USART1_RX, TIM1_CH3, I2C4_SDA, XFMC_MWE.
70 PA11 bidirectional GPIO with FT (5 V tolerant) level; reset default PA11, alternate functions USART1_CTS, USBDM, CAN1_RX, TIM1_CH4.
71 PA12 bidirectional GPIO with FT (5 V tolerant) level; reset default PA12, alternate functions USART1_RTS, USBDP, CAN1_TX, TIM1_ETR.
72 PA13 bidirectional GPIO with FT (5 V tolerant) level; reset default function JTMS/SWDIO (SWD data I/O), alternate function UART4_TX.
73 NC unconnected Not connected; no internal connection on the LQFP100 package.
74 VSS_2 power_in Ground pin; all VSS pins must be connected to the ground of the supply system.
75 VDD_2 power_in Digital I/O and internal regulator supply, 1.8 V to 3.6 V.
76 PA14 bidirectional GPIO with FT (5 V tolerant) level; reset default function JTCK/SWCLK (SWD clock), alternate function UART4_RX.
77 PA15 bidirectional GPIO with FT (5 V tolerant) level; reset default function JTDI, alternate functions SPI3_NSS, I2S3_WS, TIM2_CH1_ETR, SPI1_NSS, USART2_CTS, TIM8_CH1N.
78 PC10 bidirectional GPIO (TTa level); reset default PC10, alternate functions UART4_TX, SDIO_D2, USART3_TX, SPI3_SCK, I2S3_CK, QSPI_NSS.
79 PC11 bidirectional GPIO (TTa level); reset default PC11, alternate functions UART4_RX, SDIO_D3, USART3_RX, SPI3_MISO, QSPI_SCK.
80 PC12 bidirectional GPIO (TTa level); reset default PC12, alternate functions UART5_TX, SDIO_CK, USART3_CK, SPI3_MOSI, I2S3_SD, QSPI_IO0, TIM8_CH2N.
81 PD0 bidirectional GPIO with FT (5 V tolerant) level; reset default PD0, alternate functions XFMC_D2, CAN1_RX, UART4_TX, QSPI_IO1.
82 PD1 bidirectional GPIO with FT (5 V tolerant) level; reset default PD1, alternate functions XFMC_D3, CAN1_TX, UART4_RX, QSPI_IO2.
83 PD2 bidirectional GPIO (TTa level); reset default PD2, alternate functions TIM3_ETR, UART5_RX, SDIO_CMD, SPI3_NSS, I2S3_WS, QSPI_IO3, TIM8_CH3N.
84 PD3 bidirectional GPIO with FT (5 V tolerant) level; reset default PD3, alternate functions XFMC_CLK, USART2_CTS.
85 PD4 bidirectional GPIO (TTa level); reset default PD4, alternate functions XFMC_NOE, USART2_RTS.
86 PD5 bidirectional GPIO (TTa level); reset default PD5, alternate functions XFMC_NWE, USART2_TX.
87 PD6 bidirectional GPIO (TTa level); reset default PD6, alternate functions XFMC_NWAIT, USART2_RX.
88 PD7 bidirectional GPIO (TTa level); reset default PD7, alternate functions XFMC_NE1, XFMC_NCE2, USART2_CK.
89 PB3 bidirectional GPIO with FT (5 V tolerant) level; reset default function JTDO/TRACESWO, alternate functions SPI3_SCK, I2S3_CK, TIM2_CH2, SPI1_SCK, USART2_RTS, TIM8_BKIN.
90 PB4 bidirectional GPIO with FT (5 V tolerant) level; reset default function NJTRST, alternate functions SPI3_MISO, TIM3_CH1, SPI1_MISO, USART2_TX, TIM8_ETR.
91 PB5 bidirectional GPIO with FT (5 V tolerant) level; reset default PB5, alternate functions I2C1_SMBA, SPI3_MOSI, I2S3_SD, TIM3_CH2, SPI1_MOSI, CAN2_RX, USART2_RX, TIM1_BKIN.
92 PB6 bidirectional GPIO (TTa level); reset default PB6, alternate functions I2C1_SCL, TIM4_CH1, USART1_TX, CAN2_TX, XFMC_NE2 (XFMC_NCE3 also listed).
93 PB7 bidirectional GPIO (TTa level); reset default PB7, alternate functions I2C1_SDA, XFMC_NADV, TIM4_CH2, USART1_RX.
94 BOOT0 input Boot mode select input; the datasheet states BOOT0 and BOOT1 are input pull-down pins after reset.
95 PB8 bidirectional GPIO (TTa level); reset default PB8, alternate functions TIM4_CH3, SDIO_D4, I2C1_SCL, CAN1_RX, UART5_TX, XFMC_NWAIT.
96 PB9 bidirectional GPIO (TTa level); reset default PB9, alternate functions TIM4_CH4, SDIO_D5, I2C1_SDA, CAN1_TX, UART5_RX, XFMC_NE1, XFMC_NCE2.
97 PE0 bidirectional GPIO with FT (5 V tolerant) level; reset default PE0, alternate functions TIM4_ETR, XFMC_NBL0.
98 PE1 bidirectional GPIO with FT (5 V tolerant) level; reset default PE1, alternate function XFMC_NBL1.
99 VSS_3 power_in Ground pin; all VSS pins must be connected to the ground of the supply system.
100 VDD_3 power_in Digital I/O and internal regulator supply, 1.8 V to 3.6 V; the 4.7 µF decoupling capacitor in the supply scheme must be connected to VDD3.

Key specifications

Parameter Value
Manufacturer Nations Technologies Inc
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Data transfer mode clock frequency fPP 0 48 MHz CL ≤ 30pF 83
Clock low time tW(CKL) 32 ns fPP = 16 MHz, CL ≤ 30pF 83
Clock high time tW(CKH) 30 ns CL ≤ 30pF 83
Clock rise time tr 6 ns CL ≤ 30pF 83
Clock fall time tf 6 ns CL ≤ 30pF 83
CMD, D input setup time (referenced to CK) tISU 2 ns CL ≤ 30pF 83
CMD, D input hold time (referenced to CK) tIH 2 ns CL ≤ 30pF 83
Output valid time, MMC and SD high-speed mode (referenced to CK) tOV 14 ns CL ≤ 30pF 83
Output hold time, MMC and SD high-speed mode (referenced to CK) tOH 2.5 ns CL ≤ 30pF 83
Output valid default time, SD default mode (referenced to CK) tOVD 9 ns CL ≤ 30pF 84
Output hold default time, SD default mode (referenced to CK) tOHD -2 ns CL ≤ 30pF 84
USB transceiver startup time tSTARTUP 1 μs 84
USB operating voltage VDD 3 3.6 V 84
Differential input sensitivity VDI 0.2 V I(USBDP, USBDM) 84
Differential common-mode range VCM 0.8 2.5 V includes VDI range 84
Single-ended receiver threshold VSE 1.3 2 V 84
Static output low level VOL 0.3 V 1.5kΩ RL to 3.6V 84
Static output high level VOH 2.8 3.6 V 15kΩ RL to VSS 84
USB full-speed rise time tr 4 20 ns CL ≤ 50pF 84
USB full-speed fall time tf 4 20 ns CL ≤ 50pF 84
USB rise/fall time matching trfm 90 110 % tr / tf 84
Output signal crossover voltage VCRS 1.3 2 V 84
Output series matching resistance Rs 27 39 Ohm external matching resistor required, placed near chip pins 85
ADC supply voltage VDDA 1.8 3.6 V 85
ADC positive reference voltage VREF+ 1.8 V 85
ADC clock frequency fADC 72 MHz 85
ADC sampling rate fs 5 MHz 85
ADC conversion voltage range VAIN 0 V VSSA or VREF- connected to ground 85
ADC sampling time tS 1.5 239.5 1/fADC 85
ADC power-up time tSTAB 0 0 20 μs 85
ADC total conversion time (including sampling time) tCONV 14 252 1/fADC sampling tS + successive approximation 12.5 85
ADC total unadjusted error ET -5 1.3 5 LSB fHCLK = 72 MHz, fADC = 72 MHz, sample rate = 1.75 Msps, VDDA = 3.3 V, TA = 25 °C, after ADC calibration, VREF+ = VDDA 85
ADC offset error EO -2 1 2 LSB fHCLK = 72 MHz, fADC = 72 MHz, sample rate = 1.75 Msps, VDDA = 3.3 V, TA = 25 °C, after ADC calibration, VREF+ = VDDA 85
ADC differential linearity error ED -1 0.7 1 LSB fHCLK = 72 MHz, fADC = 72 MHz, sample rate = 1.75 Msps, VDDA = 3.3 V, TA = 25 °C, after ADC calibration, VREF+ = VDDA 85
ADC integral linearity error EL -2 0.8 2 LSB fHCLK = 72 MHz, fADC = 72 MHz, sample rate = 1.75 Msps, VDDA = 3.3 V, TA = 25 °C, after ADC calibration, VREF+ = VDDA 85

CAD (KiCad official)

  • Symbol: N32G452VEL7
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: n32g452vel7-etched.step / n32g452vel7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); n32g452vel7.step / n32g452vel7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nations Technologies Inc datasheet (96 pp, sha256 64263c0a0ef9dd52, retrieved 2026-10-18, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF