N32G452REL7

Nations Technologies Inc · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

N32G452REL7 from Nations Technologies Inc, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VBAT	power_in	Backup-domain supply, 1.8-3.6 V, powers the RTC, the external 32.768 kHz oscillator and the backup registers when VDD is off.
2	PC13-TAMPER-RTC	bidirectional	Standard 3.3 V I/O (default PC13, alternate TAMPER-RTC) fed through a power switch that sources only 3 mA total for PC13-PC15; as output it is limited to 2 MHz mode, 30 pF load and 3 mA combined.
3	PC14-OSC32_IN	bidirectional	Standard 3.3 V I/O (default PC14, alternate OSC32_IN) under the same 3 mA combined output limit as PC13-PC15 (2 MHz mode, 30 pF max load).
4	PC15-OSC32_OUT	bidirectional	Standard 3.3 V I/O (default PC15, alternate OSC32_OUT) under the same 3 mA combined output limit as PC13-PC15 (2 MHz mode, 30 pF max load).
5	OSC_IN	input	High-speed external oscillator input for a 4-32 MHz crystal/resonator or bypass clock; on LQFP64 it can be remapped to PD0 by software.
6	OSC_OUT	output	High-speed external oscillator output for a 4-32 MHz crystal/resonator; on LQFP64 it can be remapped to PD1 by software.
7	NRST	input	CMOS reset input with a non-disconnectable internal pull-up (30-70 kΩ at 3.3 V); input pulses shorter than 100 ns are filtered.
8	PC0	bidirectional	3.3 V tolerant analog-capable I/O with ADC12_IN6, I2C3_SCL and UART6_TX alternate functions.
9	PC1	bidirectional	3.3 V tolerant analog-capable I/O with ADC12_IN7, I2C3_SDA and UART6_RX alternate functions.
10	PC2	bidirectional	3.3 V tolerant analog-capable I/O with ADC12_IN8, UART7_TX, SPI3_NSS and I2S3_WS alternate functions.
11	PC3	bidirectional	3.3 V tolerant analog-capable I/O with ADC12_IN9, UART7_RX, SPI3_SCK and I2S3_CK alternate functions.
12	VSSA	power_in	Analog ground for the ADC and DAC, must be connected to VSS.
13	VDDA	power_in	Analog supply for the ADC and DAC, 1.8-3.6 V, must be the same supply as VDD (at most 300 mV difference during power-up and normal operation).
14	PA0-WKUP	bidirectional	3.3 V tolerant analog-capable I/O with WKUP wake-up input, ADC1_IN1, USART2_CTS, TIM2_CH1_ETR, TIM5_CH1, TIM8_ETR and SPI3_MISO alternate functions.
15	PA1	bidirectional	3.3 V tolerant analog-capable I/O with ADC1_IN2, USART2_RTS, TIM5_CH2, TIM2_CH2, SPI3_MOSI and I2S3_SD alternate functions.
16	PA2	bidirectional	3.3 V tolerant analog-capable I/O with USART2_TX, TIM5_CH3, ADC12_IN11 and TIM2_CH3 alternate functions.
17	PA3	bidirectional	3.3 V tolerant analog-capable I/O with USART2_RX, TIM5_CH4, ADC1_IN4 and TIM2_CH4 alternate functions.
18	VSS_4	power_in	Ground pin for the digital core and I/O ring.
19	VDD_4	power_in	Digital supply for the I/O pins and internal voltage regulator, 1.8-3.6 V.
20	PA4	bidirectional	3.3 V tolerant analog-capable I/O with SPI1_NSS, USART2_CK, DAC_OUT1, ADC2_IN1, QSPI_NSS and I2C2_SCL alternate functions.
21	PA5	bidirectional	3.3 V tolerant analog-capable I/O with SPI1_SCK, DAC_OUT2, ADC2_IN2, QSPI_SCK and I2C2_SDA alternate functions.
22	PA6	bidirectional	3.3 V tolerant analog-capable I/O with SPI1_MISO, TIM8_BKIN, ADC1_IN3, TIM3_CH1, QSPI_IO0 and TIM1_BKIN alternate functions.
23	PA7	bidirectional	3.3 V tolerant analog-capable I/O with SPI1_MOSI, TIM8_CH1N, ADC2_IN4, TIM3_CH2, QSPI_IO1 and TIM1_CH1N alternate functions.
24	PC4	bidirectional	3.3 V tolerant analog-capable I/O with ADC2_IN5, QSPI_IO2, UART7_TX and I2C3_SCL alternate functions.
25	PC5	bidirectional	3.3 V tolerant analog-capable I/O with ADC2_IN12, QSPI_IO3, UART7_RX and I2C3_SDA alternate functions.
26	PB0	bidirectional	Standard 3.3 V I/O with TIM3_CH3, TIM8_CH2N, TIM1_CH2N and UART6_TX alternate functions.
27	PB1	bidirectional	3.3 V tolerant analog-capable I/O with ADC2_IN3, TIM3_CH4, TIM8_CH3N, TIM1_CH3N and UART6_RX alternate functions.
28	PB2-BOOT1	bidirectional	3.3 V tolerant analog-capable I/O (default BOOT1, boot-mode select together with BOOT0) with ADC2_IN13, UART4_TX and SPI1_NSS alternate functions.
29	PB10	bidirectional	Standard 3.3 V I/O (fail-safe supported) with I2C2_SCL, USART3_TX and TIM2_CH3 alternate functions.
30	PB11	bidirectional	Standard 3.3 V I/O with I2C2_SDA, USART3_RX and TIM2_CH4 alternate functions.
31	VSS_1	power_in	Ground pin for the digital core and I/O ring.
32	VDD_1	power_in	Digital supply for the I/O pins and internal voltage regulator, 1.8-3.6 V.
33	PB12	bidirectional	Standard 3.3 V I/O with SPI2_NSS, I2S2_WS, I2C2_SMBA, USART3_CK, TIM1_BKIN and CAN2_RX alternate functions.
34	PB13	bidirectional	Standard 3.3 V I/O with SPI2_SCK, I2S2_CK, USART3_CTS, TIM1_CH1N, CAN2_TX and UART5_TX alternate functions.
35	PB14	bidirectional	Standard 3.3 V I/O with SPI2_MISO, TIM1_CH2N, USART3_RTS and UART5_RX alternate functions.
36	PB15	bidirectional	Standard 3.3 V I/O with SPI2_MOSI, I2S2_SD and TIM1_CH3N alternate functions.
37	PC6	bidirectional	Standard 3.3 V I/O (fail-safe supported) with I2S2_MCK, TIM8_CH1, SDIO_DAT6, I2C4_SCL, TIM3_CH1, SPI2_NSS, I2S2_WS and USART2_CTS alternate functions.
38	PC7	bidirectional	Standard 3.3 V I/O (fail-safe supported) with I2S3_MCK, TIM8_CH2, SDIO_DAT7, I2C4_SDA, TIM3_CH2, SPI2_SCK, I2S2_CK and USART2_RTS alternate functions.
39	PC8	bidirectional	Standard 3.3 V I/O (fail-safe supported) with TIM8_CH3, SDIO_DAT0, TIM3_CH3, SPI2_MISO and USART2_TX alternate functions.
40	PC9	bidirectional	Standard 3.3 V I/O (fail-safe supported) with TIM8_CH4, SDIO_DAT1, TIM3_CH4, SPI2_MOSI, I2S2_SD and USART2_RX alternate functions.
41	PA8	bidirectional	5 V tolerant I/O with USART1_CK, TIM1_CH1 and MCO clock output alternate functions.
42	PA9	bidirectional	5 V tolerant I/O with USART1_TX, TIM1_CH2 and I2C4_SCL alternate functions.
43	PA10	bidirectional	5 V tolerant I/O with USART1_RX, TIM1_CH3 and I2C4_SDA alternate functions.
44	PA11	bidirectional	5 V tolerant I/O with USART1_CTS, USBDM, CAN1_RX and TIM1_CH4 alternate functions.
45	PA12	bidirectional	5 V tolerant I/O with USART1_RTS, USBDP, CAN1_TX and TIM1_ETR alternate functions.
46	PA13	bidirectional	5 V tolerant I/O whose default function after reset is JTMS-SWDIO (SWD data), with UART4_TX as alternate function.
47	VSS_2	power_in	Ground pin for the digital core and I/O ring.
48	VDD_2	power_in	Digital supply for the I/O pins and internal voltage regulator, 1.8-3.6 V.
49	PA14	bidirectional	5 V tolerant I/O whose default function after reset is JTCK-SWCLK (SWD clock), with UART4_RX as alternate function.
50	PA15	bidirectional	5 V tolerant I/O whose default function after reset is JTDI, with SPI3_NSS, I2S3_WS, TIM2_CH1_ETR, SPI1_NSS, USART2_CTS and TIM8_CH1N alternate functions.
51	PC10	bidirectional	Standard 3.3 V I/O with UART4_TX, SDIO_DAT2, USART3_TX, SPI3_SCK, I2S3_CK and QSPI_NSS alternate functions.
52	PC11	bidirectional	Standard 3.3 V I/O with UART4_RX, SDIO_DAT3, USART3_RX, SPI3_MISO and QSPI_SCK alternate functions.
53	PC12	bidirectional	Standard 3.3 V I/O with UART5_TX, SDIO_CLK, USART3_CK, SPI3_MOSI, I2S3_SD, QSPI_IO0 and TIM8_CH2N alternate functions.
54	PD2	bidirectional	Standard 3.3 V I/O (fail-safe supported) with TIM3_ETR, UART5_RX, SPI3_NSS, I2S3_WS, SDIO_CMD, QSPI_IO3 and TIM8_CH3N alternate functions.
55	PB3	bidirectional	5 V tolerant I/O whose default function after reset is JTDO, with TRACESWO, TIM2_CH2, SPI1_SCK, USART2_RTS, TIM8_BKIN, SPI3_SCK and I2S3_CK alternate functions.
56	PB4	bidirectional	5 V tolerant I/O whose default function after reset is NJTRST (JTAG reset), with TIM3_CH1, SPI1_MISO, USART2_TX, TIM8_ETR and SPI3_MISO alternate functions.
57	PB5	bidirectional	5 V tolerant I/O with I2C1_SMBA, SPI3_MOSI, I2S3_SD, TIM3_CH2, SPI1_MOSI, CAN2_RX, USART2_RX and TIM1_BKIN alternate functions.
58	PB6	bidirectional	Standard 3.3 V I/O with I2C1_SCL, TIM4_CH1, USART1_TX and CAN2_TX alternate functions.
59	PB7	bidirectional	Standard 3.3 V I/O with I2C1_SDA, TIM4_CH2 and USART1_RX alternate functions.
60	BOOT0	input	Boot mode select input (with BOOT1) for startup from main Flash, system memory or internal SRAM; configured as input pull-down after reset.
61	PB8	bidirectional	Standard 3.3 V I/O with TIM4_CH3, SDIO_DAT4, I2C1_SCL, CAN1_RX and UART5_TX alternate functions.
62	PB9	bidirectional	Standard 3.3 V I/O with TIM4_CH4, SDIO_DAT5, I2C1_SDA, CAN1_TX and UART5_RX alternate functions.
63	VSS_3	power_in	Ground pin for the digital core and I/O ring.
64	VDD_3	power_in	Digital supply for the I/O pins and internal voltage regulator, 1.8-3.6 V.

Key specifications

Parameter	Value
Manufacturer	Nations Technologies Inc
Package	LQFP-64(10x10)
Category	Embedded Processors & Controllers
Pins	64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Output low-level voltage, VDD=3.3V	VOL			0.4	V	VDD = 3.3 V, IOL= 2mA, 4mA, 8mA, and 12mA	55
Output low-level voltage, VDD=2.5V	VOL			0.4	V	VDD = 2.5 V, IOL= 1.5mA,3mA, 7mA, and 11mA	55
Output high-level voltage, VDD=3.3V	VOH	2.4			V	VDD = 3.3 V, IOH= -2mA, -4mA, -8mA, and -12mA	55
Output high-level voltage, VDD=2.5V	VOH	1.8			V	VDD = 2.5 V, IOH= -1.5mA, -3mA, -7mA, and -11mA	55
Maximum output frequency, 2mA drive, VDD=3.3V	fmax(IO)out			75	MHz	DS_CFGy=0, PMODEy[1:0]=xx (2mA); CL=5pF, VDD=3.3V	56
Maximum output frequency, 2mA drive, VDD=2.5V	fmax(IO)out			50	MHz	DS_CFGy=0, PMODEy[1:0]=xx (2mA); CL=5pF, VDD=2.5V	56
Maximum output frequency, 2mA drive, VDD=1.8V	fmax(IO)out			30	MHz	DS_CFGy=0, PMODEy[1:0]=xx (2mA); CL=5pF, VDD=1.8V	56
Maximum output frequency, 4mA drive, VDD=3.3V	fmax(IO)out			90	MHz	DS_CFGy=1, PMODEy[1:0]=00/01 (4mA); CL=10pF, VDD=3.3V	56
Maximum output frequency, 4mA drive, VDD=2.5V	fmax(IO)out			60	MHz	DS_CFGy=1, PMODEy[1:0]=00/01 (4mA); CL=10pF, VDD=2.5V	56
Maximum output frequency, 4mA drive, VDD=1.8V	fmax(IO)out			40	MHz	DS_CFGy=1, PMODEy[1:0]=00/01 (4mA); CL=10pF, VDD=1.8V	56
Maximum output frequency, 8mA drive, VDD=3.3V	fmax(IO)out			100	MHz	DS_CFGy=1, PMODEy[1:0]=10 (8mA); CL=20pF, VDD=3.3V	56
Maximum output frequency, 8mA drive, VDD=2.5V	fmax(IO)out			75	MHz	DS_CFGy=1, PMODEy[1:0]=10 (8mA); CL=20pF, VDD=2.5V	56
Maximum output frequency, 8mA drive, VDD=1.8V	fmax(IO)out			50	MHz	DS_CFGy=1, PMODEy[1:0]=10 (8mA); CL=20pF, VDD=1.8V	56
Maximum output frequency, 12mA drive, VDD=3.3V	fmax(IO)out			120	MHz	DS_CFGy=1, PMODEy[1:0]=11 (12mA); CL=30pF, VDD=3.3V	56
Maximum output frequency, 12mA drive, VDD=2.5V	fmax(IO)out			90	MHz	DS_CFGy=1, PMODEy[1:0]=11 (12mA); CL=30pF, VDD=2.5V	56
Maximum output frequency, 12mA drive, VDD=1.8V	fmax(IO)out			60	MHz	DS_CFGy=1, PMODEy[1:0]=11 (12mA); CL=30pF, VDD=1.8V	56
Output delay, 2mA drive, VDD=3.3V	t(IO)out			3.66	ns	DS_CFGy=0, PMODEy[1:0]=xx (2mA); CL=5pF, VDD=3.3V	56
Output delay, 4mA drive, VDD=3.3V	t(IO)out			3.5	ns	DS_CFGy=1, PMODEy[1:0]=00/01 (4mA); CL=10pF, VDD=3.3V	56
Output delay, 8mA drive, VDD=3.3V	t(IO)out			3.42	ns	DS_CFGy=1, PMODEy[1:0]=10 (8mA); CL=20pF, VDD=3.3V	56
Output delay, 12mA drive, VDD=3.3V	t(IO)out			3.34	ns	DS_CFGy=1, PMODEy[1:0]=11 (12mA); CL=30pF, VDD=3.3V	56
NRST input high-level voltage, VDD=3.3V	VIH(NRST)	2			V	VDD = 3.3 V	57
NRST Schmitt trigger hysteresis, VDD=3.3V	Vhys(NRST)	200			mV	VDD = 3.3 V	57
NRST weak pull-up equivalent resistance, VDD=3.3V	RPU	30	50	70	KΩ	VDD = 3.3 V	57
NRST input filtered pulse	VF(NRST)			100	ns		57
NRST input non-filtered pulse	VNF(NRST)	300			ns		58
TIM1/8 timer resolution time	tres(TIM)	6.95			ns	fTIMxCLK= 144MHz	58
TIM1/8 timer external clock frequency, CH1 to CH4	fEXT	0		72	MHz	fTIMxCLK= 144MHz	58
TIM1/8 16-bit counter clock period, internal clock	tCOUNTER	0.00695		455	μs	fTIMxCLK= 144MHz	58
TIM1/8 maximum possible count	tMAX_COUNT			29.8	s	fTIMxCLK= 144MHz	58
TIM2/3/4/5 timer resolution time	tres(TIM)	13.9			ns	fTIMxCLK= 72MHz	58
TIM2/3/4/5 timer external clock frequency, CH1 to CH4	fEXT	0		36	MHz	fTIMxCLK= 72MHz	58
TIM2/3/4/5 16-bit counter clock period, internal clock	tCOUNTER	0.0139		910	μs	fTIMxCLK= 72MHz	58
TIM2/3/4/5 maximum possible count	tMAX_COUNT			59.6	s	fTIMxCLK= 72MHz	58
USB transceiver startup time	tSTARTUP			1	μs		68
USB operating voltage	VDD	3		3.6	V		68
USB differential input sensitivity	VDI	0.2			V	I(USBDP, USBDM)	68
USB differential common-mode range	VCM	0.8		2.5	V	包含VDI范围	68
USB single-ended receiver threshold	VSE	1.3		2	V		68
USB static output low level	VOL			0.3	V	1.5kΩ的RL接至3.6V	68
USB static output high level	VOH	2.8		3.6	V	15kΩ的RL接至VSS	68
USB full-speed rise time	tr	4		20	ns	CL ≤ 50pF	68
USB full-speed fall time	tf	4		20	ns	CL ≤ 50pF	68
USB rise/fall time matching	trfm	90		110	%	tr / tf	68
USB output signal crossover voltage	VCRS	1.3		2	V		68
USB output series matching resistance	Rs	27		39	Ω	需匹配电阻外置,靠近芯片引脚	68
ADC supply voltage	VDDA	1.8		3.6	V		69
ADC positive reference voltage	VREF+	1.8			V		69
ADC clock frequency	fADC			80	MHz		69
ADC sampling rate, 12-bit resolution	fs	0.01		4.7	MHz	1.8V ≤ VDD ≤ 3.6V，分辨率12bit	69
ADC sampling rate, 10-bit resolution	fs	0.012		6.1	MHz	1.8V ≤ VDD ≤ 3.6V，分辨率10bit	69
ADC sampling rate, 8-bit resolution	fs	0.014		7.3	MHz	1.8V ≤ VDD ≤ 3.6V，分辨率8bit	69
ADC sampling rate, 6-bit resolution	fs	0.0175		8.9	MHz	1.8V ≤ VDD ≤ 3.6V，分辨率6bit	69
ADC conversion voltage range	VAIN	0			V	min: VSSA或VREF-连接到地	69
ADC sampling switch resistance, fast channel	RADC			137.6	Ω	快速通道，3.6V电压条件下	69
ADC sampling switch resistance, slow channel	RADC			147	Ω	慢速通道，3.6V电压条件下	69
ADC sampling time, 12-bit, fast channel	tS	0.056		8.35	μs	fADC = 80 MHz, 快速通道, 分辨率12bit	69
ADC sampling period, 12-bit, fast channel	Ts	4.5		601.5	1/fADC	fADC = 80 MHz, 快速通道, 分辨率12bit	69
ADC power-on time	tSTAB	6	10	20	μs		69
ADC total conversion time including sampling	tCONV	8		614	1/fADC	(采样 TS + 逐步逼近6.5/8.5/10.5/12.5)	69

CAD (KiCad official)

Symbol: N32G452REL7
Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
3D model files: n32g452rel7-etched.step / n32g452rel7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); n32g452rel7.step / n32g452rel7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Nations Technologies Inc datasheet (84 pp, sha256 d029c2b36655fb32, retrieved 2026-10-18, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# N32G452REL7

**Nations Technologies Inc** · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

N32G452REL7 from Nations Technologies Inc, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBAT | power_in | Backup-domain supply, 1.8-3.6 V, powers the RTC, the external 32.768 kHz oscillator and the backup registers when VDD is off. |
| 2 | PC13-TAMPER-RTC | bidirectional | Standard 3.3 V I/O (default PC13, alternate TAMPER-RTC) fed through a power switch that sources only 3 mA total for PC13-PC15; as output it is limited to 2 MHz mode, 30 pF load and 3 mA combined. |
| 3 | PC14-OSC32_IN | bidirectional | Standard 3.3 V I/O (default PC14, alternate OSC32_IN) under the same 3 mA combined output limit as PC13-PC15 (2 MHz mode, 30 pF max load). |
| 4 | PC15-OSC32_OUT | bidirectional | Standard 3.3 V I/O (default PC15, alternate OSC32_OUT) under the same 3 mA combined output limit as PC13-PC15 (2 MHz mode, 30 pF max load). |
| 5 | OSC_IN | input | High-speed external oscillator input for a 4-32 MHz crystal/resonator or bypass clock; on LQFP64 it can be remapped to PD0 by software. |
| 6 | OSC_OUT | output | High-speed external oscillator output for a 4-32 MHz crystal/resonator; on LQFP64 it can be remapped to PD1 by software. |
| 7 | NRST | input | CMOS reset input with a non-disconnectable internal pull-up (30-70 kΩ at 3.3 V); input pulses shorter than 100 ns are filtered. |
| 8 | PC0 | bidirectional | 3.3 V tolerant analog-capable I/O with ADC12_IN6, I2C3_SCL and UART6_TX alternate functions. |
| 9 | PC1 | bidirectional | 3.3 V tolerant analog-capable I/O with ADC12_IN7, I2C3_SDA and UART6_RX alternate functions. |
| 10 | PC2 | bidirectional | 3.3 V tolerant analog-capable I/O with ADC12_IN8, UART7_TX, SPI3_NSS and I2S3_WS alternate functions. |
| 11 | PC3 | bidirectional | 3.3 V tolerant analog-capable I/O with ADC12_IN9, UART7_RX, SPI3_SCK and I2S3_CK alternate functions. |
| 12 | VSSA | power_in | Analog ground for the ADC and DAC, must be connected to VSS. |
| 13 | VDDA | power_in | Analog supply for the ADC and DAC, 1.8-3.6 V, must be the same supply as VDD (at most 300 mV difference during power-up and normal operation). |
| 14 | PA0-WKUP | bidirectional | 3.3 V tolerant analog-capable I/O with WKUP wake-up input, ADC1_IN1, USART2_CTS, TIM2_CH1_ETR, TIM5_CH1, TIM8_ETR and SPI3_MISO alternate functions. |
| 15 | PA1 | bidirectional | 3.3 V tolerant analog-capable I/O with ADC1_IN2, USART2_RTS, TIM5_CH2, TIM2_CH2, SPI3_MOSI and I2S3_SD alternate functions. |
| 16 | PA2 | bidirectional | 3.3 V tolerant analog-capable I/O with USART2_TX, TIM5_CH3, ADC12_IN11 and TIM2_CH3 alternate functions. |
| 17 | PA3 | bidirectional | 3.3 V tolerant analog-capable I/O with USART2_RX, TIM5_CH4, ADC1_IN4 and TIM2_CH4 alternate functions. |
| 18 | VSS_4 | power_in | Ground pin for the digital core and I/O ring. |
| 19 | VDD_4 | power_in | Digital supply for the I/O pins and internal voltage regulator, 1.8-3.6 V. |
| 20 | PA4 | bidirectional | 3.3 V tolerant analog-capable I/O with SPI1_NSS, USART2_CK, DAC_OUT1, ADC2_IN1, QSPI_NSS and I2C2_SCL alternate functions. |
| 21 | PA5 | bidirectional | 3.3 V tolerant analog-capable I/O with SPI1_SCK, DAC_OUT2, ADC2_IN2, QSPI_SCK and I2C2_SDA alternate functions. |
| 22 | PA6 | bidirectional | 3.3 V tolerant analog-capable I/O with SPI1_MISO, TIM8_BKIN, ADC1_IN3, TIM3_CH1, QSPI_IO0 and TIM1_BKIN alternate functions. |
| 23 | PA7 | bidirectional | 3.3 V tolerant analog-capable I/O with SPI1_MOSI, TIM8_CH1N, ADC2_IN4, TIM3_CH2, QSPI_IO1 and TIM1_CH1N alternate functions. |
| 24 | PC4 | bidirectional | 3.3 V tolerant analog-capable I/O with ADC2_IN5, QSPI_IO2, UART7_TX and I2C3_SCL alternate functions. |
| 25 | PC5 | bidirectional | 3.3 V tolerant analog-capable I/O with ADC2_IN12, QSPI_IO3, UART7_RX and I2C3_SDA alternate functions. |
| 26 | PB0 | bidirectional | Standard 3.3 V I/O with TIM3_CH3, TIM8_CH2N, TIM1_CH2N and UART6_TX alternate functions. |
| 27 | PB1 | bidirectional | 3.3 V tolerant analog-capable I/O with ADC2_IN3, TIM3_CH4, TIM8_CH3N, TIM1_CH3N and UART6_RX alternate functions. |
| 28 | PB2-BOOT1 | bidirectional | 3.3 V tolerant analog-capable I/O (default BOOT1, boot-mode select together with BOOT0) with ADC2_IN13, UART4_TX and SPI1_NSS alternate functions. |
| 29 | PB10 | bidirectional | Standard 3.3 V I/O (fail-safe supported) with I2C2_SCL, USART3_TX and TIM2_CH3 alternate functions. |
| 30 | PB11 | bidirectional | Standard 3.3 V I/O with I2C2_SDA, USART3_RX and TIM2_CH4 alternate functions. |
| 31 | VSS_1 | power_in | Ground pin for the digital core and I/O ring. |
| 32 | VDD_1 | power_in | Digital supply for the I/O pins and internal voltage regulator, 1.8-3.6 V. |
| 33 | PB12 | bidirectional | Standard 3.3 V I/O with SPI2_NSS, I2S2_WS, I2C2_SMBA, USART3_CK, TIM1_BKIN and CAN2_RX alternate functions. |
| 34 | PB13 | bidirectional | Standard 3.3 V I/O with SPI2_SCK, I2S2_CK, USART3_CTS, TIM1_CH1N, CAN2_TX and UART5_TX alternate functions. |
| 35 | PB14 | bidirectional | Standard 3.3 V I/O with SPI2_MISO, TIM1_CH2N, USART3_RTS and UART5_RX alternate functions. |
| 36 | PB15 | bidirectional | Standard 3.3 V I/O with SPI2_MOSI, I2S2_SD and TIM1_CH3N alternate functions. |
| 37 | PC6 | bidirectional | Standard 3.3 V I/O (fail-safe supported) with I2S2_MCK, TIM8_CH1, SDIO_DAT6, I2C4_SCL, TIM3_CH1, SPI2_NSS, I2S2_WS and USART2_CTS alternate functions. |
| 38 | PC7 | bidirectional | Standard 3.3 V I/O (fail-safe supported) with I2S3_MCK, TIM8_CH2, SDIO_DAT7, I2C4_SDA, TIM3_CH2, SPI2_SCK, I2S2_CK and USART2_RTS alternate functions. |
| 39 | PC8 | bidirectional | Standard 3.3 V I/O (fail-safe supported) with TIM8_CH3, SDIO_DAT0, TIM3_CH3, SPI2_MISO and USART2_TX alternate functions. |
| 40 | PC9 | bidirectional | Standard 3.3 V I/O (fail-safe supported) with TIM8_CH4, SDIO_DAT1, TIM3_CH4, SPI2_MOSI, I2S2_SD and USART2_RX alternate functions. |
| 41 | PA8 | bidirectional | 5 V tolerant I/O with USART1_CK, TIM1_CH1 and MCO clock output alternate functions. |
| 42 | PA9 | bidirectional | 5 V tolerant I/O with USART1_TX, TIM1_CH2 and I2C4_SCL alternate functions. |
| 43 | PA10 | bidirectional | 5 V tolerant I/O with USART1_RX, TIM1_CH3 and I2C4_SDA alternate functions. |
| 44 | PA11 | bidirectional | 5 V tolerant I/O with USART1_CTS, USBDM, CAN1_RX and TIM1_CH4 alternate functions. |
| 45 | PA12 | bidirectional | 5 V tolerant I/O with USART1_RTS, USBDP, CAN1_TX and TIM1_ETR alternate functions. |
| 46 | PA13 | bidirectional | 5 V tolerant I/O whose default function after reset is JTMS-SWDIO (SWD data), with UART4_TX as alternate function. |
| 47 | VSS_2 | power_in | Ground pin for the digital core and I/O ring. |
| 48 | VDD_2 | power_in | Digital supply for the I/O pins and internal voltage regulator, 1.8-3.6 V. |
| 49 | PA14 | bidirectional | 5 V tolerant I/O whose default function after reset is JTCK-SWCLK (SWD clock), with UART4_RX as alternate function. |
| 50 | PA15 | bidirectional | 5 V tolerant I/O whose default function after reset is JTDI, with SPI3_NSS, I2S3_WS, TIM2_CH1_ETR, SPI1_NSS, USART2_CTS and TIM8_CH1N alternate functions. |
| 51 | PC10 | bidirectional | Standard 3.3 V I/O with UART4_TX, SDIO_DAT2, USART3_TX, SPI3_SCK, I2S3_CK and QSPI_NSS alternate functions. |
| 52 | PC11 | bidirectional | Standard 3.3 V I/O with UART4_RX, SDIO_DAT3, USART3_RX, SPI3_MISO and QSPI_SCK alternate functions. |
| 53 | PC12 | bidirectional | Standard 3.3 V I/O with UART5_TX, SDIO_CLK, USART3_CK, SPI3_MOSI, I2S3_SD, QSPI_IO0 and TIM8_CH2N alternate functions. |
| 54 | PD2 | bidirectional | Standard 3.3 V I/O (fail-safe supported) with TIM3_ETR, UART5_RX, SPI3_NSS, I2S3_WS, SDIO_CMD, QSPI_IO3 and TIM8_CH3N alternate functions. |
| 55 | PB3 | bidirectional | 5 V tolerant I/O whose default function after reset is JTDO, with TRACESWO, TIM2_CH2, SPI1_SCK, USART2_RTS, TIM8_BKIN, SPI3_SCK and I2S3_CK alternate functions. |
| 56 | PB4 | bidirectional | 5 V tolerant I/O whose default function after reset is NJTRST (JTAG reset), with TIM3_CH1, SPI1_MISO, USART2_TX, TIM8_ETR and SPI3_MISO alternate functions. |
| 57 | PB5 | bidirectional | 5 V tolerant I/O with I2C1_SMBA, SPI3_MOSI, I2S3_SD, TIM3_CH2, SPI1_MOSI, CAN2_RX, USART2_RX and TIM1_BKIN alternate functions. |
| 58 | PB6 | bidirectional | Standard 3.3 V I/O with I2C1_SCL, TIM4_CH1, USART1_TX and CAN2_TX alternate functions. |
| 59 | PB7 | bidirectional | Standard 3.3 V I/O with I2C1_SDA, TIM4_CH2 and USART1_RX alternate functions. |
| 60 | BOOT0 | input | Boot mode select input (with BOOT1) for startup from main Flash, system memory or internal SRAM; configured as input pull-down after reset. |
| 61 | PB8 | bidirectional | Standard 3.3 V I/O with TIM4_CH3, SDIO_DAT4, I2C1_SCL, CAN1_RX and UART5_TX alternate functions. |
| 62 | PB9 | bidirectional | Standard 3.3 V I/O with TIM4_CH4, SDIO_DAT5, I2C1_SDA, CAN1_TX and UART5_RX alternate functions. |
| 63 | VSS_3 | power_in | Ground pin for the digital core and I/O ring. |
| 64 | VDD_3 | power_in | Digital supply for the I/O pins and internal voltage regulator, 1.8-3.6 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Nations Technologies Inc |
| Package | LQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output low-level voltage, VDD=3.3V | VOL |  |  | 0.4 | V | VDD = 3.3 V, IOL= 2mA, 4mA, 8mA, and 12mA | 55 |
| Output low-level voltage, VDD=2.5V | VOL |  |  | 0.4 | V | VDD = 2.5 V, IOL= 1.5mA,3mA, 7mA, and 11mA | 55 |
| Output high-level voltage, VDD=3.3V | VOH | 2.4 |  |  | V | VDD = 3.3 V, IOH= -2mA, -4mA, -8mA, and -12mA | 55 |
| Output high-level voltage, VDD=2.5V | VOH | 1.8 |  |  | V | VDD = 2.5 V, IOH= -1.5mA, -3mA, -7mA, and -11mA | 55 |
| Maximum output frequency, 2mA drive, VDD=3.3V | fmax(IO)out |  |  | 75 | MHz | DS_CFGy=0, PMODEy[1:0]=xx (2mA); CL=5pF, VDD=3.3V | 56 |
| Maximum output frequency, 2mA drive, VDD=2.5V | fmax(IO)out |  |  | 50 | MHz | DS_CFGy=0, PMODEy[1:0]=xx (2mA); CL=5pF, VDD=2.5V | 56 |
| Maximum output frequency, 2mA drive, VDD=1.8V | fmax(IO)out |  |  | 30 | MHz | DS_CFGy=0, PMODEy[1:0]=xx (2mA); CL=5pF, VDD=1.8V | 56 |
| Maximum output frequency, 4mA drive, VDD=3.3V | fmax(IO)out |  |  | 90 | MHz | DS_CFGy=1, PMODEy[1:0]=00/01 (4mA); CL=10pF, VDD=3.3V | 56 |
| Maximum output frequency, 4mA drive, VDD=2.5V | fmax(IO)out |  |  | 60 | MHz | DS_CFGy=1, PMODEy[1:0]=00/01 (4mA); CL=10pF, VDD=2.5V | 56 |
| Maximum output frequency, 4mA drive, VDD=1.8V | fmax(IO)out |  |  | 40 | MHz | DS_CFGy=1, PMODEy[1:0]=00/01 (4mA); CL=10pF, VDD=1.8V | 56 |
| Maximum output frequency, 8mA drive, VDD=3.3V | fmax(IO)out |  |  | 100 | MHz | DS_CFGy=1, PMODEy[1:0]=10 (8mA); CL=20pF, VDD=3.3V | 56 |
| Maximum output frequency, 8mA drive, VDD=2.5V | fmax(IO)out |  |  | 75 | MHz | DS_CFGy=1, PMODEy[1:0]=10 (8mA); CL=20pF, VDD=2.5V | 56 |
| Maximum output frequency, 8mA drive, VDD=1.8V | fmax(IO)out |  |  | 50 | MHz | DS_CFGy=1, PMODEy[1:0]=10 (8mA); CL=20pF, VDD=1.8V | 56 |
| Maximum output frequency, 12mA drive, VDD=3.3V | fmax(IO)out |  |  | 120 | MHz | DS_CFGy=1, PMODEy[1:0]=11 (12mA); CL=30pF, VDD=3.3V | 56 |
| Maximum output frequency, 12mA drive, VDD=2.5V | fmax(IO)out |  |  | 90 | MHz | DS_CFGy=1, PMODEy[1:0]=11 (12mA); CL=30pF, VDD=2.5V | 56 |
| Maximum output frequency, 12mA drive, VDD=1.8V | fmax(IO)out |  |  | 60 | MHz | DS_CFGy=1, PMODEy[1:0]=11 (12mA); CL=30pF, VDD=1.8V | 56 |
| Output delay, 2mA drive, VDD=3.3V | t(IO)out |  |  | 3.66 | ns | DS_CFGy=0, PMODEy[1:0]=xx (2mA); CL=5pF, VDD=3.3V | 56 |
| Output delay, 4mA drive, VDD=3.3V | t(IO)out |  |  | 3.5 | ns | DS_CFGy=1, PMODEy[1:0]=00/01 (4mA); CL=10pF, VDD=3.3V | 56 |
| Output delay, 8mA drive, VDD=3.3V | t(IO)out |  |  | 3.42 | ns | DS_CFGy=1, PMODEy[1:0]=10 (8mA); CL=20pF, VDD=3.3V | 56 |
| Output delay, 12mA drive, VDD=3.3V | t(IO)out |  |  | 3.34 | ns | DS_CFGy=1, PMODEy[1:0]=11 (12mA); CL=30pF, VDD=3.3V | 56 |
| NRST input high-level voltage, VDD=3.3V | VIH(NRST) | 2 |  |  | V | VDD = 3.3 V | 57 |
| NRST Schmitt trigger hysteresis, VDD=3.3V | Vhys(NRST) | 200 |  |  | mV | VDD = 3.3 V | 57 |
| NRST weak pull-up equivalent resistance, VDD=3.3V | RPU | 30 | 50 | 70 | KΩ | VDD = 3.3 V | 57 |
| NRST input filtered pulse | VF(NRST) |  |  | 100 | ns |  | 57 |
| NRST input non-filtered pulse | VNF(NRST) | 300 |  |  | ns |  | 58 |
| TIM1/8 timer resolution time | tres(TIM) | 6.95 |  |  | ns | fTIMxCLK= 144MHz | 58 |
| TIM1/8 timer external clock frequency, CH1 to CH4 | fEXT | 0 |  | 72 | MHz | fTIMxCLK= 144MHz | 58 |
| TIM1/8 16-bit counter clock period, internal clock | tCOUNTER | 0.00695 |  | 455 | μs | fTIMxCLK= 144MHz | 58 |
| TIM1/8 maximum possible count | tMAX_COUNT |  |  | 29.8 | s | fTIMxCLK= 144MHz | 58 |
| TIM2/3/4/5 timer resolution time | tres(TIM) | 13.9 |  |  | ns | fTIMxCLK= 72MHz | 58 |
| TIM2/3/4/5 timer external clock frequency, CH1 to CH4 | fEXT | 0 |  | 36 | MHz | fTIMxCLK= 72MHz | 58 |
| TIM2/3/4/5 16-bit counter clock period, internal clock | tCOUNTER | 0.0139 |  | 910 | μs | fTIMxCLK= 72MHz | 58 |
| TIM2/3/4/5 maximum possible count | tMAX_COUNT |  |  | 59.6 | s | fTIMxCLK= 72MHz | 58 |
| USB transceiver startup time | tSTARTUP |  |  | 1 | μs |  | 68 |
| USB operating voltage | VDD | 3 |  | 3.6 | V |  | 68 |
| USB differential input sensitivity | VDI | 0.2 |  |  | V | I(USBDP, USBDM) | 68 |
| USB differential common-mode range | VCM | 0.8 |  | 2.5 | V | 包含VDI范围 | 68 |
| USB single-ended receiver threshold | VSE | 1.3 |  | 2 | V |  | 68 |
| USB static output low level | VOL |  |  | 0.3 | V | 1.5kΩ的RL接至3.6V | 68 |
| USB static output high level | VOH | 2.8 |  | 3.6 | V | 15kΩ的RL接至VSS | 68 |
| USB full-speed rise time | tr | 4 |  | 20 | ns | CL ≤ 50pF | 68 |
| USB full-speed fall time | tf | 4 |  | 20 | ns | CL ≤ 50pF | 68 |
| USB rise/fall time matching | trfm | 90 |  | 110 | % | tr / tf | 68 |
| USB output signal crossover voltage | VCRS | 1.3 |  | 2 | V |  | 68 |
| USB output series matching resistance | Rs | 27 |  | 39 | Ω | 需匹配电阻外置,靠近芯片引脚 | 68 |
| ADC supply voltage | VDDA | 1.8 |  | 3.6 | V |  | 69 |
| ADC positive reference voltage | VREF+ | 1.8 |  |  | V |  | 69 |
| ADC clock frequency | fADC |  |  | 80 | MHz |  | 69 |
| ADC sampling rate, 12-bit resolution | fs | 0.01 |  | 4.7 | MHz | 1.8V ≤ VDD ≤ 3.6V，分辨率12bit | 69 |
| ADC sampling rate, 10-bit resolution | fs | 0.012 |  | 6.1 | MHz | 1.8V ≤ VDD ≤ 3.6V，分辨率10bit | 69 |
| ADC sampling rate, 8-bit resolution | fs | 0.014 |  | 7.3 | MHz | 1.8V ≤ VDD ≤ 3.6V，分辨率8bit | 69 |
| ADC sampling rate, 6-bit resolution | fs | 0.0175 |  | 8.9 | MHz | 1.8V ≤ VDD ≤ 3.6V，分辨率6bit | 69 |
| ADC conversion voltage range | VAIN | 0 |  |  | V | min: VSSA或VREF-连接到地 | 69 |
| ADC sampling switch resistance, fast channel | RADC |  |  | 137.6 | Ω | 快速通道，3.6V电压条件下 | 69 |
| ADC sampling switch resistance, slow channel | RADC |  |  | 147 | Ω | 慢速通道，3.6V电压条件下 | 69 |
| ADC sampling time, 12-bit, fast channel | tS | 0.056 |  | 8.35 | μs | fADC = 80 MHz, 快速通道, 分辨率12bit | 69 |
| ADC sampling period, 12-bit, fast channel | Ts | 4.5 |  | 601.5 | 1/fADC | fADC = 80 MHz, 快速通道, 分辨率12bit | 69 |
| ADC power-on time | tSTAB | 6 | 10 | 20 | μs |  | 69 |
| ADC total conversion time including sampling | tCONV | 8 |  | 614 | 1/fADC | (采样 TS + 逐步逼近6.5/8.5/10.5/12.5) | 69 |

## CAD (KiCad official)

- Symbol: `N32G452REL7`
- Footprint: `Package_QFP:LQFP-64_10x10mm_P0.5mm`
- 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files: `n32g452rel7-etched.step` / `n32g452rel7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `n32g452rel7.step` / `n32g452rel7.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Nations Technologies Inc datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589042181021974528) (84 pp, sha256 `d029c2b36655fb32`, retrieved 2026-10-18, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/n32g452rel7-datasheet.pdf)