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N32G451VCL7

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Nations Technologies Inc Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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N32G451VCL7

Nations Technologies Inc · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

N32G451VCL7 from Nations Technologies Inc, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PE2 bidirectional GPIO PE2, 5 V tolerant (FT) with fail-safe; alternate function UART6_TX.
2 PE3 bidirectional GPIO PE3, 5 V tolerant (FT) with fail-safe; alternate function UART6_RX.
3 PE4 bidirectional GPIO PE4, 5 V tolerant (FT) with fail-safe; no alternate function listed.
4 PE5 bidirectional GPIO PE5, 5 V tolerant (FT) with fail-safe; no alternate function listed.
5 PE6 bidirectional GPIO PE6, 5 V tolerant (FT) with fail-safe; no alternate function listed.
6 VBAT power_in Backup-domain supply, 1.8 V to 3.6 V, powering RTC, 32 kHz oscillator and backup registers when VDD is off.
7 PC13-TAMPER-RTC bidirectional GPIO PC13 (TAMPER-RTC) powered through a switch limited to 3 mA total for PC13 to PC15; as output limited to 2 MHz with 30 pF max load.
8 PC14-OSC32_IN bidirectional GPIO PC14 or LSE oscillator input OSC32_IN; PC13 to PC15 share a 3 mA total output current limit.
9 PC15-OSC32_OUT bidirectional GPIO PC15 or LSE oscillator output OSC32_OUT; PC13 to PC15 share a 3 mA total output current limit.
10 VSS_5 power_in Digital ground pin 5.
11 VDD_5 power_in Digital supply for I/O and internal regulator, 1.8 V to 3.6 V.
12 OSC_IN input HSE oscillator input for a 4 to 32 MHz crystal/resonator; in bypass mode high level 0.8VDD to VDD.
13 OSC_OUT output HSE oscillator output for the 4 to 32 MHz crystal/resonator.
14 NRST bidirectional Active-low reset with internal non-disconnectable pull-up (RPU 30 to 70 kΩ at 3.3 V); pulses below 100 ns are filtered.
15 PC0 bidirectional GPIO PC0, 3.3 V tolerant with analog capability (TTa); alternates ADC12_IN6, I2C3_SCL, UART6_TX.
16 PC1 bidirectional GPIO PC1, 3.3 V tolerant with analog capability (TTa); alternates ADC12_IN7, I2C3_SDA, UART6_RX.
17 PC2 bidirectional GPIO PC2, 3.3 V tolerant with analog capability (TTa); alternates ADC12_IN8, UART7_TX, SPI3_NSS, I2S3_WS.
18 PC3 bidirectional GPIO PC3, 3.3 V tolerant with analog capability (TTa); alternates ADC12_IN9, UART7_RX, SPI3_SCK, I2S3_CK.
19 VSSA power_in Analog ground, to be connected to VSS.
20 VREF- power_in Negative ADC reference voltage; may be connected internally to VSSA depending on package.
21 VREF+ power_in Positive ADC/DAC reference voltage, 1.8 V up to VDDA; DAC VREF+ must always be below VDDA.
22 VDDA power_in Analog supply for ADC/DAC, 1.8 V to 3.6 V, must be the same as VDD (max 300 mV difference).
23 PA0-WKUP bidirectional GPIO PA0 with WKUP wake-up function (TTa, 3.3 V tolerant, analog); alternates USART2_CTS, ADC1_IN1, TIM2_CH1_ETR, TIM5_CH1, TIM8_ETR, SPI3_MISO.
24 PA1 bidirectional GPIO PA1 (TTa, 3.3 V tolerant, analog); alternates USART2_RTS, ADC1_IN2, TIM5_CH2, TIM2_CH2, SPI3_MOSI, I2S3_SD.
25 PA2 bidirectional GPIO PA2 (TTa, 3.3 V tolerant, analog); alternates USART2_TX, TIM5_CH3, ADC12_IN11, TIM2_CH3.
26 PA3 bidirectional GPIO PA3 (TTa, 3.3 V tolerant, analog); alternates USART2_RX, TIM5_CH4, ADC1_IN4, TIM2_CH4.
27 VSS_4 power_in Digital ground pin 4.
28 VDD_4 power_in Digital supply for I/O and internal regulator, 1.8 V to 3.6 V.
29 PA4 bidirectional GPIO PA4 (TTa, 3.3 V tolerant, analog); alternates SPI1_NSS, USART2_CK, DAC_OUT1, ADC2_IN1, I2C2_SCL.
30 PA5 bidirectional GPIO PA5 (TTa, 3.3 V tolerant, analog); alternates SPI1_SCK, DAC_OUT2, ADC2_IN2, I2C2_SDA.
31 PA6 bidirectional GPIO PA6 (TTa, 3.3 V tolerant, analog); alternates SPI1_MISO, TIM8_BKIN, ADC1_IN3, TIM3_CH1, TIM1_BKIN.
32 PA7 bidirectional GPIO PA7 (TTa, 3.3 V tolerant, analog); alternates SPI1_MOSI, TIM8_CH1N, ADC2_IN4, TIM3_CH2, TIM1_CH1N.
33 PC4 bidirectional GPIO PC4 (TTa, 3.3 V tolerant, analog); alternates ADC2_IN5, UART7_TX, I2C3_SCL.
34 PC5 bidirectional GPIO PC5 (TTa, 3.3 V tolerant, analog); alternates ADC2_IN12, UART7_RX, I2C3_SDA.
35 PB0 bidirectional GPIO PB0, standard 3.3 V I/O (TC); alternates TIM3_CH3, TIM8_CH2N, TIM1_CH2N, UART6_TX.
36 PB1 bidirectional GPIO PB1 (TTa, 3.3 V tolerant, analog); alternates ADC2_IN3, TIM3_CH4, TIM8_CH3N, TIM1_CH3N, UART6_RX.
37 PB2-BOOT1 bidirectional GPIO PB2 shared with BOOT1 boot-mode input (TTa); alternates ADC2_IN13, UART4_TX, SPI1_NSS.
38 PE7 bidirectional GPIO PE7, standard 3.3 V I/O (TC); alternates TIM1_ETR, UART4_RX, SPI1_SCK.
39 PE8 bidirectional GPIO PE8, standard 3.3 V I/O (TC); alternates TIM1_CH1N, UART5_TX, SDIO_DAT0, SPI1_MISO.
40 PE9 bidirectional GPIO PE9, standard 3.3 V I/O (TC); alternates TIM1_CH1, UART5_RX, SDIO_DAT1, SPI1_MOSI.
41 PE10 bidirectional GPIO PE10, standard 3.3 V I/O (TC); alternates TIM1_CH2N, SDIO_DAT2, SPI2_NSS, I2S2_WS.
42 PE11 bidirectional GPIO PE11, standard 3.3 V I/O (TC); alternates TIM1_CH2, SDIO_DAT3, SPI2_SCK, I2S2_CK.
43 PE12 bidirectional GPIO PE12, standard 3.3 V I/O (TC); alternates TIM1_CH3N, SDIO_CK, SPI2_MISO.
44 PE13 bidirectional GPIO PE13, standard 3.3 V I/O (TC); alternates TIM1_CH3, SPI2_MOSI, I2S2_SD, SDIO_CMD.
45 PE14 bidirectional GPIO PE14, standard 3.3 V I/O (TC); alternate function TIM1_CH4.
46 PE15 bidirectional GPIO PE15, standard 3.3 V I/O (TC); alternate function TIM1_BKIN.
47 PB10 bidirectional GPIO PB10, standard 3.3 V I/O (TC) with fail-safe; alternates I2C2_SCL, USART3_TX, TIM2_CH3.
48 PB11 bidirectional GPIO PB11, standard 3.3 V I/O (TC); alternates I2C2_SDA, USART3_RX, TIM2_CH4.
49 VSS_1 power_in Digital ground pin 1.
50 VDD_1 power_in Digital supply for I/O and internal regulator, 1.8 V to 3.6 V.
51 PB12 bidirectional GPIO PB12, standard 3.3 V I/O (TC); alternates SPI2_NSS, I2S2_WS, I2C2_SMBA, USART3_CK, TIM1_BKIN.
52 PB13 bidirectional GPIO PB13, standard 3.3 V I/O (TC); alternates SPI2_SCK, I2S2_CK, USART3_CTS, TIM1_CH1N, UART5_TX.
53 PB14 bidirectional GPIO PB14, standard 3.3 V I/O (TC); alternates SPI2_MISO, TIM1_CH2N, USART3_RTS, UART5_RX.
54 PB15 bidirectional GPIO PB15, standard 3.3 V I/O (TC); alternates SPI2_MOSI, I2S2_SD, TIM1_CH3N.
55 PD8 bidirectional GPIO PD8, standard 3.3 V I/O (TC); alternates USART3_TX, SPI3_NSS, I2S3_WS, CAN1_RX.
56 PD9 bidirectional GPIO PD9, standard 3.3 V I/O (TC); alternates USART3_RX, SPI3_SCK, I2S3_CK, CAN1_TX.
57 PD10 bidirectional GPIO PD10, standard 3.3 V I/O (TC); alternate function USART3_CK.
58 PD11 bidirectional GPIO PD11, standard 3.3 V I/O (TC); alternates USART3_CTS, SPI3_MISO.
59 PD12 bidirectional GPIO PD12, standard 3.3 V I/O (TC); alternates TIM4_CH1, USART3_RTS, SPI3_MOSI, I2S3_SD.
60 PD13 bidirectional GPIO PD13, standard 3.3 V I/O (TC); alternate function TIM4_CH2.
61 PD14 bidirectional GPIO PD14, standard 3.3 V I/O (TC); alternates TIM4_CH3, I2C4_SCL, TIM8_CH1.
62 PD15 bidirectional GPIO PD15, 5 V tolerant (FT) with fail-safe; alternates TIM4_CH4, I2C4_SDA, TIM8_CH2.
63 PC6 bidirectional GPIO PC6, standard 3.3 V I/O (TC) with fail-safe; alternates I2S2_MCK, TIM8_CH1, SDIO_DAT6, I2C4_SCL, TIM3_CH1, SPI2_NSS, I2S2_WS, USART2_CTS.
64 PC7 bidirectional GPIO PC7, standard 3.3 V I/O (TC) with fail-safe; alternates I2S3_MCK, TIM8_CH2, SDIO_DAT7, I2C4_SDA, TIM3_CH2, SPI2_SCK, I2S2_CK, USART2_RTS.
65 PC8 bidirectional GPIO PC8, standard 3.3 V I/O (TC) with fail-safe; alternates TIM8_CH3, SDIO_DAT0, TIM3_CH3, SPI2_MISO, USART2_TX.
66 PC9 bidirectional GPIO PC9, standard 3.3 V I/O (TC) with fail-safe; alternates TIM8_CH4, SDIO_DAT1, TIM3_CH4, SPI2_MOSI, I2S2_SD, USART2_RX.
67 PA8 bidirectional GPIO PA8, 5 V tolerant (FT) with fail-safe; alternates USART1_CK, TIM1_CH1, MCO.
68 PA9 bidirectional GPIO PA9, 5 V tolerant (FT) with fail-safe; alternates USART1_TX, TIM1_CH2, I2C4_SCL.
69 PA10 bidirectional GPIO PA10, 5 V tolerant (FT) with fail-safe; alternates USART1_RX, TIM1_CH3, I2C4_SDA.
70 PA11 bidirectional GPIO PA11, 5 V tolerant (FT) with fail-safe; alternates USART1_CTS, USBDM, CAN1_RX, TIM1_CH4.
71 PA12 bidirectional GPIO PA12, 5 V tolerant (FT) with fail-safe; alternates USART1_RTS, USBDP, CAN1_TX, TIM1_ETR.
72 PA13 bidirectional GPIO PA13, 5 V tolerant (FT) with fail-safe; default function JTMS-SWDIO (SWJ debug), alternate UART4_TX.
73 NC unconnected Not connected.
74 VSS_2 power_in Digital ground pin 2.
75 VDD_2 power_in Digital supply for I/O and internal regulator, 1.8 V to 3.6 V.
76 PA14 bidirectional GPIO PA14, 5 V tolerant (FT) with fail-safe; default function JTCK-SWCLK (SWJ debug), alternate UART4_RX.
77 PA15 bidirectional GPIO PA15, 5 V tolerant (FT) with fail-safe; default function JTDI, alternates include SPI1_NSS, USART2_CTS, TIM8_CH1N, TIM2_CH1_ETR.
78 PC10 bidirectional GPIO PC10, standard 3.3 V I/O (TC) with fail-safe; alternates UART4_TX, SDIO_DAT2, USART3_TX, SPI3_SCK, I2S3_CK.
79 PC11 bidirectional GPIO PC11, standard 3.3 V I/O (TC) with fail-safe; alternates UART4_RX, SDIO_DAT3, USART3_RX, SPI3_MISO.
80 PC12 bidirectional GPIO PC12, standard 3.3 V I/O (TC) with fail-safe; alternates UART5_TX, SDIO_CLK, USART3_CK, SPI3_MOSI, I2S3_SD, TIM8_CH2N.
81 PD0 bidirectional GPIO PD0 (fixed function pin on LQFP100), 5 V tolerant (FT) with fail-safe; alternates CAN1_RX, UART4_TX.
82 PD1 bidirectional GPIO PD1 (fixed function pin on LQFP100), 5 V tolerant (FT) with fail-safe; alternates CAN1_TX, UART4_RX.
83 PD2 bidirectional GPIO PD2, standard 3.3 V I/O (TC) with fail-safe; alternates TIM3_ETR, UART5_RX, SDIO_CMD, SPI3_NSS, I2S3_WS, TIM8_CH3N.
84 PD3 bidirectional GPIO PD3, 5 V tolerant (FT) with fail-safe; alternate function USART2_CTS.
85 PD4 bidirectional GPIO PD4, standard 3.3 V I/O (TC) with fail-safe; alternate function USART2_RTS.
86 PD5 bidirectional GPIO PD5, standard 3.3 V I/O (TC) with fail-safe; alternate function USART2_TX.
87 PD6 bidirectional GPIO PD6, standard 3.3 V I/O (TC) with fail-safe; alternate function USART2_RX.
88 PD7 bidirectional GPIO PD7, standard 3.3 V I/O (TC) with fail-safe; alternate function USART2_CK.
89 PB3 bidirectional GPIO PB3, 5 V tolerant (FT) with fail-safe; default function JTDO/TRACESWO (SWJ debug); alternates SPI3_SCK, I2S3_CK, TIM2_CH2, SPI1_SCK, USART2_RTS, TIM8_BKIN.
90 PB4 bidirectional GPIO PB4, 5 V tolerant (FT) with fail-safe; default function NJTRST (SWJ debug); alternates SPI3_MISO, TIM3_CH1, SPI1_MISO, USART2_TX, TIM8_ETR.
91 PB5 bidirectional GPIO PB5, 5 V tolerant (FT) with fail-safe; alternates I2C1_SMBA, SPI3_MOSI, I2S3_SD, TIM3_CH2, SPI1_MOSI, USART2_RX, TIM1_BKIN.
92 PB6 bidirectional GPIO PB6, standard 3.3 V I/O (TC) with fail-safe; alternates I2C1_SCL, TIM4_CH1, USART1_TX.
93 PB7 bidirectional GPIO PB7, standard 3.3 V I/O (TC) with fail-safe; alternates I2C1_SDA, TIM4_CH2, USART1_RX.
94 BOOT0 input Boot mode select input (BOOT0 and BOOT1 are inputs with pull-down, selecting flash, system memory or SRAM boot).
95 PB8 bidirectional GPIO PB8, standard 3.3 V I/O (TC) with fail-safe; alternates TIM4_CH3, SDIO_DAT4, I2C1_SCL, CAN1_RX, UART5_TX.
96 PB9 bidirectional GPIO PB9, standard 3.3 V I/O (TC) with fail-safe; alternates TIM4_CH4, SDIO_DAT5, I2C1_SDA, CAN1_TX, UART5_RX.
97 PE0 bidirectional GPIO PE0, 5 V tolerant (FT) with fail-safe; alternate function TIM4_ETR.
98 PE1 bidirectional GPIO PE1, 5 V tolerant (FT) with fail-safe; no alternate function listed.
99 VSS_3 power_in Digital ground pin 3.
100 VDD_3 power_in Digital supply for I/O and internal regulator, 1.8 V to 3.6 V.

Key specifications

Parameter Value
Manufacturer Nations Technologies Inc
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Output low level VOL, VDD=3.3V VOL 0.4 V VDD = 3.3 V, IOL= 2mA, 4mA, 8mA, and 12mA 52
Output low level VOL, VDD=2.5V VOL 0.4 V VDD = 2.5 V, IOL= 1.5mA,3mA, 7mA, and 11mA 52
Output high level VOH, VDD=3.3V VOH 2.4 V VDD = 3.3 V, IOH= -2mA, -4mA, -8mA, and -12mA 52
Output high level VOH, VDD=2.5V VOH 1.8 V VDD = 2.5 V, IOH= -1.5mA, -3mA, -7mA, and -11mA 52
NRST input high level voltage VIH(NRST) 2 V VDD = 3.3 V 54
NRST Schmitt trigger hysteresis Vhys(NRST) 200 mV VDD = 3.3 V 54
NRST weak pull-up equivalent resistance RPU 30 50 70 KΩ VDD = 3.3 V 54
NRST input filtered pulse VF(NRST) 100 ns 54
NRST input non-filtered pulse VNF(NRST) 300 ns 54
TIM1/8 timer resolution time tres(TIM) 6.95 ns fTIMxCLK= 144MHz 54
TIM1/8 timer external clock frequency fEXT 0 72 MHz fTIMxCLK= 144MHz 54
TIM1/8 16-bit counter clock period tCOUNTER 0.00695 455 μs fTIMxCLK= 144MHz, internal clock selected 54
TIM1/8 maximum possible count tMAX_COUNT 29.8 s fTIMxCLK= 144MHz 54
TIM2/3/4/5 timer resolution time tres(TIM) 13.9 ns fTIMxCLK= 72MHz 54
TIM2/3/4/5 timer external clock frequency fEXT 0 36 MHz fTIMxCLK= 72MHz 54
TIM2/3/4/5 16-bit counter clock period tCOUNTER 0.0139 910 μs fTIMxCLK= 72MHz, internal clock selected 54
I/O max frequency, 2mA drive fmax(IO)out 75 MHz 2mA; CL=5pF,VDD=3.3V 53
I/O max frequency, 2mA drive fmax(IO)out 50 MHz 2mA; CL=5pF,VDD=2.5V 53
I/O max frequency, 2mA drive fmax(IO)out 30 MHz 2mA; CL=5pF,VDD=1.8V 53
I/O output delay, 2mA drive t(IO)out 3.66 ns 2mA; CL=5pF,VDD=3.3V 53
I/O output delay, 2mA drive t(IO)out 4.72 ns 2mA; CL=5pF,VDD=2.5V 53
I/O output delay, 2mA drive t(IO)out 7.12 ns 2mA; CL=5pF,VDD=1.8V 53
I/O input delay, 2mA drive t(IO)in 2 ns 2mA; CL=50fF,VDD=2.97V,VDDD=0.81V 53
I/O max frequency, 4mA drive fmax(IO)out 90 MHz 4mA; CL=10pF,VDD=3.3V 53
I/O max frequency, 4mA drive fmax(IO)out 60 MHz 4mA; CL=10pF,VDD=2.5V 53
I/O max frequency, 4mA drive fmax(IO)out 40 MHz 4mA; CL=10pF,VDD=1.8V 53
I/O output delay, 4mA drive t(IO)out 3.5 ns 4mA; CL=10pF,VDD=3.3V 53
I/O output delay, 4mA drive t(IO)out 4.5 ns 4mA; CL=10pF,VDD=2.5V 53
I/O output delay, 4mA drive t(IO)out 6.74 ns 4mA; CL=10pF,VDD=1.8V 53
I/O input delay, 4mA drive t(IO)in 2 ns 4mA; CL=50fF,VDD=2.97V,VDDD=0.81V 53
I/O max frequency, 8mA drive fmax(IO)out 100 MHz 8mA; CL=20pF,VDD=3.3V 53
I/O max frequency, 8mA drive fmax(IO)out 75 MHz 8mA; CL=20pF,VDD=2.5V 53
I/O max frequency, 8mA drive fmax(IO)out 50 MHz 8mA; CL=20pF,VDD=1.8V 53
I/O output delay, 8mA drive t(IO)out 3.42 ns 8mA; CL=20pF,VDD=3.3V 53
I/O output delay, 8mA drive t(IO)out 4.73 ns 8mA; CL=20pF,VDD=2.5V 53
I/O output delay, 8mA drive t(IO)out 6.53 ns 8mA; CL=20pF,VDD=1.8V 53
I/O input delay, 8mA drive t(IO)in 2 ns 8mA; CL=50fF,VDD=2.97V,VDDD=0.81V 53
I/O max frequency, 12mA drive fmax(IO)out 120 MHz 12mA; CL=30pF,VDD=3.3V 53
I/O max frequency, 12mA drive fmax(IO)out 90 MHz 12mA; CL=30pF,VDD=2.5V 53
I/O max frequency, 12mA drive fmax(IO)out 60 MHz 12mA; CL=30pF,VDD=1.8V 53
I/O output delay, 12mA drive t(IO)out 3.34 ns 12mA; CL=30pF,VDD=3.3V 53
I/O output delay, 12mA drive t(IO)out 4.26 ns 12mA; CL=3pF,VDD=2.5V 53
I/O output delay, 12mA drive t(IO)out 6.34 ns 12mA; CL=3pF,VDD=1.8V 53
I/O input delay, 12mA drive t(IO)in 2 ns 12mA; CL=50fF,VDD=2.97V,VDDD=0.81V 53
Supply voltage VDDA (ADC) VDDA 1.8 3.6 V 65
Positive reference voltage VREF+ VREF+ 1.8 V 65
ADC clock frequency fADC 80 MHz 65
ADC sampling rate, 12-bit fs 0.01 4.7 MHz 1.8V ≤ VDD ≤ 3.6V，分辨率12bit 65
ADC sampling rate, 10-bit fs 0.012 6.1 MHz 1.8V ≤ VDD ≤ 3.6V，分辨率10bit 65
ADC sampling rate, 8-bit fs 0.014 7.3 MHz 1.8V ≤ VDD ≤ 3.6V，分辨率8bit 65
ADC sampling rate, 6-bit fs 0.0175 8.9 MHz 1.8V ≤ VDD ≤ 3.6V，分辨率6bit 65
ADC sampling switch resistance, fast channel RADC 137.6 Ω 快速通道，3.6V电压条件下 65
ADC sampling switch resistance, slow channel RADC 147 Ω 慢速通道，3.6V电压条件下 65
ADC sampling time tS, fast channel tS 0.056 8.35 μs fADC = 80 MHz, 快速通道, 分辨率12bit 65
ADC sampling time tS, slow channel tS 0.056 8.35 μs fADC = 80 MHz, 慢速通道, 分辨率12bit 65
ADC sampling period Ts, fast channel Ts 4.5 601.5 1/fADC fADC = 80 MHz, 快速通道, 分辨率12bit 65
ADC sampling period Ts, slow channel Ts 4.5 601.5 1/fADC fADC = 80 MHz, 慢速通道, 分辨率12bit 65
ADC power-on time tSTAB 6 10 20 μs 65
ADC total conversion time (including sampling) tCONV 8 614 1/fADC 65

CAD (KiCad official)

  • Symbol: N32G451VCL7
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: n32g451vcl7-etched.step / n32g451vcl7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); n32g451vcl7.step / n32g451vcl7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nations Technologies Inc datasheet (76 pp, sha256 dbeae2e3a5d0603f, retrieved 2026-10-20, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF