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N32G451RCL7

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Nations Technologies Inc Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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N32G451RCL7

Nations Technologies Inc · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

N32G451RCL7 from Nations Technologies Inc, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Backup-domain supply, 1.8-3.6V, powers the RTC, the external 32 kHz oscillator and the backup registers when VDD is off.
2 PC13-TAMPER-RTC bidirectional Standard 3.3V I/O (TC) fed through a power switch limited to 3 mA total for PC13-PC15; as an output it is limited to 2 MHz mode with a 30 pF maximum load, and its function is held by backup-region registers after first power-up.
3 PC14-OSC32_IN bidirectional Standard 3.3V I/O (TC) on the same 3 mA power-switch limit as PC13-PC15; it serves as OSC32_IN for the 32.768 kHz LSE crystal.
4 PC15-OSC32_OUT bidirectional Standard 3.3V I/O (TC) on the same 3 mA power-switch limit as PC13-PC15; it serves as OSC32_OUT for the 32.768 kHz LSE crystal.
5 PD0-OSC_IN input Default HSE oscillator input (OSC_IN, 4-32 MHz crystal or bypass clock) after reset, and it can be reassigned in software to PD0 as a general-purpose I/O.
6 PD1-OSC_OUT output Default HSE oscillator output (OSC_OUT) after reset, and it can be reassigned in software to PD1 as a general-purpose I/O.
7 NRST bidirectional Active-low reset pin with an internal pull-up of 30-70 kOhm (50 kOhm typical at 3.3V) that filters input pulses shorter than 100 ns.
8 PC0 bidirectional 3.3V-tolerant analog-capable I/O (TTa) that can be used as ADC12_IN6, with alternate functions I2C3_SCL and UART6_TX.
9 PC1 bidirectional 3.3V-tolerant analog-capable I/O (TTa) that can be used as ADC12_IN7, with alternate functions I2C3_SDA and UART6_RX.
10 PC2 bidirectional 3.3V-tolerant analog-capable I/O (TTa) that can be used as ADC12_IN8, with alternate functions UART7_TX, SPI3_NSS and I2S3_WS.
11 PC3 bidirectional 3.3V-tolerant analog-capable I/O (TTa) that can be used as ADC12_IN9, with alternate functions UART7_RX, SPI3_SCK and I2S3_CK.
12 VSSA power_in Analog ground for the ADC and DAC, which must be connected to VSS.
13 VDDA power_in Analog supply for the ADC and DAC, 1.8-3.6V, which must be the same as VDD (at most 300 mV difference during power-up and operation).
14 PA0-WKUP bidirectional 3.3V-tolerant analog-capable I/O (TTa) that also serves as the WKUP wake-up input and ADC1_IN1, with alternate functions USART2_CTS, TIM2_CH1_ETR, TIM5_CH1, TIM8_ETR and SPI3_MISO.
15 PA1 bidirectional 3.3V-tolerant analog-capable I/O (TTa) that can be used as ADC1_IN2, with alternate functions USART2_RTS, TIM5_CH2, TIM2_CH2, SPI3_MOSI and I2S3_SD.
16 PA2 bidirectional 3.3V-tolerant analog-capable I/O (TTa) that can be used as ADC12_IN11, with alternate functions USART2_TX, TIM5_CH3 and TIM2_CH3.
17 PA3 bidirectional 3.3V-tolerant analog-capable I/O (TTa) that can be used as ADC1_IN4, with alternate functions USART2_RX, TIM5_CH4 and TIM2_CH4.
18 VSS_4 power_in Ground pin for the digital I/O and core, which must be connected to the system ground.
19 VDD_4 power_in Digital supply pin for the I/O and internal regulator, 1.8-3.6V.
20 PA4 bidirectional 3.3V-tolerant analog-capable I/O (TTa) that can be used as DAC_OUT1 or ADC2_IN1, with alternate functions SPI1_NSS, USART2_CK and I2C2_SCL.
21 PA5 bidirectional 3.3V-tolerant analog-capable I/O (TTa) that can be used as DAC_OUT2 or ADC2_IN2, with alternate functions SPI1_SCK and I2C2_SDA.
22 PA6 bidirectional 3.3V-tolerant analog-capable I/O (TTa) that can be used as ADC1_IN3, with alternate functions SPI1_MISO, TIM8_BKIN, TIM3_CH1 and TIM1_BKIN.
23 PA7 bidirectional 3.3V-tolerant analog-capable I/O (TTa) that can be used as ADC2_IN4, with alternate functions SPI1_MOSI, TIM8_CH1N, TIM3_CH2 and TIM1_CH1N.
24 PC4 bidirectional 3.3V-tolerant analog-capable I/O (TTa) that can be used as ADC2_IN5, with alternate functions UART7_TX and I2C3_SCL.
25 PC5 bidirectional 3.3V-tolerant analog-capable I/O (TTa) that can be used as ADC2_IN12, with alternate functions UART7_RX and I2C3_SDA.
26 PB0 bidirectional Standard 3.3V I/O (TC) with alternate functions TIM3_CH3, TIM8_CH2N, TIM1_CH2N and UART6_TX.
27 PB1 bidirectional 3.3V-tolerant analog-capable I/O (TTa) that can be used as ADC2_IN3, with alternate functions TIM3_CH4, TIM8_CH3N, TIM1_CH3N and UART6_RX.
28 PB2/BOOT1 bidirectional 3.3V-tolerant analog-capable I/O (TTa) that is shared with the BOOT1 boot-mode selection, with alternate functions ADC2_IN13, UART4_TX and SPI1_NSS.
29 PB10 bidirectional Standard 3.3V I/O (TC) with fail-safe support, with alternate functions I2C2_SCL, USART3_TX and TIM2_CH3.
30 PB11 bidirectional Standard 3.3V I/O (TC) with alternate functions I2C2_SDA, USART3_RX and TIM2_CH4.
31 VSS_1 power_in Ground pin for the digital I/O and core, which must be connected to the system ground.
32 VDD_1 power_in Digital supply pin for the I/O and internal regulator, 1.8-3.6V.
33 PB12 bidirectional Standard 3.3V I/O (TC) with alternate functions SPI2_NSS, I2S2_WS, I2C2_SMBA, USART3_CK and TIM1_BKIN.
34 PB13 bidirectional Standard 3.3V I/O (TC) with alternate functions SPI2_SCK, I2S2_CK, USART3_CTS, TIM1_CH1N and UART5_TX.
35 PB14 bidirectional Standard 3.3V I/O (TC) with alternate functions SPI2_MISO, TIM1_CH2N, USART3_RTS and UART5_RX.
36 PB15 bidirectional Standard 3.3V I/O (TC) with alternate functions SPI2_MOSI, I2S2_SD and TIM1_CH3N.
37 PC6 bidirectional Standard 3.3V I/O (TC) with fail-safe support, with alternate functions I2S2_MCK, TIM8_CH1, SDIO_DAT6, I2C4_SCL, TIM3_CH1, SPI2_NSS, I2S2_WS and USART2_CTS.
38 PC7 bidirectional Standard 3.3V I/O (TC) with fail-safe support, with alternate functions I2S3_MCK, TIM8_CH2, SDIO_DAT7, I2C4_SDA, TIM3_CH2, SPI2_SCK, I2S2_CK and USART2_RTS.
39 PC8 bidirectional Standard 3.3V I/O (TC) with fail-safe support, with alternate functions TIM8_CH3, SDIO_DAT0, TIM3_CH3, SPI2_MISO and USART2_TX.
40 PC9 bidirectional Standard 3.3V I/O (TC) with fail-safe support, with alternate functions TIM8_CH4, SDIO_DAT1, TIM3_CH4, SPI2_MOSI, I2S2_SD and USART2_RX.
41 PA8 bidirectional 5V-tolerant I/O (FT) with fail-safe support, with alternate functions USART1_CK, TIM1_CH1 and MCO.
42 PA9 bidirectional 5V-tolerant I/O (FT) with fail-safe support, with alternate functions USART1_TX, TIM1_CH2 and I2C4_SCL.
43 PA10 bidirectional 5V-tolerant I/O (FT) with fail-safe support, with alternate functions USART1_RX, TIM1_CH3 and I2C4_SDA.
44 PA11 bidirectional 5V-tolerant I/O (FT) with fail-safe support, with alternate functions USART1_CTS, USBDM, CAN1_RX and TIM1_CH4.
45 PA12 bidirectional 5V-tolerant I/O (FT) with fail-safe support, with alternate functions USART1_RTS, USBDP, CAN1_TX and TIM1_ETR.
46 PA13 bidirectional 5V-tolerant I/O (FT) with fail-safe support; its default function after reset is JTMS-SWDIO, with alternate function UART4_TX.
47 VSS_2 power_in Ground pin for the digital I/O and core, which must be connected to the system ground.
48 VDD_2 power_in Digital supply pin for the I/O and internal regulator, 1.8-3.6V.
49 PA14 bidirectional 5V-tolerant I/O (FT) with fail-safe support; its default function after reset is JTCK-SWCLK, with alternate function UART4_RX.
50 PA15 bidirectional 5V-tolerant I/O (FT) with fail-safe support; its default function after reset is JTDI, with alternate functions SPI3_NSS, I2S3_WS and TIM2_CH1_ETR.
51 PC10 bidirectional Standard 3.3V I/O (TC) with fail-safe support, with alternate functions UART4_TX, SDIO_DAT2, USART3_TX, SPI3_SCK and I2S3_CK.
52 PC11 bidirectional Standard 3.3V I/O (TC) with fail-safe support, with alternate functions UART4_RX, SDIO_DAT3, USART3_RX and SPI3_MISO.
53 PC12 bidirectional Standard 3.3V I/O (TC) with fail-safe support, with alternate functions UART5_TX, SDIO_CLK, USART3_CK, SPI3_MOSI, I2S3_SD and TIM8_CH2N.
54 PD2 bidirectional Standard 3.3V I/O (TC) with fail-safe support, with alternate functions TIM3_ETR, UART5_RX, SDIO_CMD, SPI3_NSS, I2S3_WS and TIM8_CH3N.
55 PB3 bidirectional 5V-tolerant I/O (FT) with fail-safe support; its default function after reset is JTDO, with alternate functions TRACESWO, TIM2_CH2, SPI1_SCK, USART2_RTS and SPI3_SCK.
56 PB4 bidirectional 5V-tolerant I/O (FT) with fail-safe support; its default function after reset is NJTRST, with alternate functions TIM3_CH1, SPI1_MISO, USART2_TX and SPI3_MISO.
57 PB5 bidirectional 5V-tolerant I/O (FT) with fail-safe support, with alternate functions I2C1_SMBA, SPI3_MOSI, I2S3_SD, TIM3_CH2, SPI1_MOSI, USART2_RX and TIM1_BKIN.
58 PB6 bidirectional Standard 3.3V I/O (TC) with fail-safe support, with alternate functions I2C1_SCL, TIM4_CH1 and USART1_TX.
59 PB7 bidirectional Standard 3.3V I/O (TC) with fail-safe support, with alternate functions I2C1_SDA, TIM4_CH2 and USART1_RX.
60 BOOT0 input Boot-mode select input with an internal pull-down, which together with BOOT1 selects flash, system-memory or SRAM boot after reset.
61 PB8 bidirectional Standard 3.3V I/O (TC) with fail-safe support, with alternate functions TIM4_CH3, SDIO_DAT4, I2C1_SCL, CAN1_RX and UART5_TX.
62 PB9 bidirectional Standard 3.3V I/O (TC) with fail-safe support, with alternate functions TIM4_CH4, SDIO_DAT5, I2C1_SDA, CAN1_TX and UART5_RX.
63 VSS_3 power_in Ground pin for the digital I/O and core, which must be connected to the system ground.
64 VDD_3 power_in Digital supply pin for the I/O and internal regulator, 1.8-3.6V.

Key specifications

Parameter Value
Manufacturer Nations Technologies Inc
Package LQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Output low voltage (3.3 V domain) VOL 0.4 V VDD = 3.3 V, IOL = 2, 4, 8, 12 mA; min printed as VSS 52
Output low voltage (2.5 V domain) VOL 0.4 V VDD = 2.5 V, IOL = 1.5, 3, 7, 11 mA; min printed as VSS 52
Output high voltage (3.3 V domain) VOH 2.4 V VDD = 3.3 V, IOH = -2, -4, -8, -12 mA; PC13/PC14/PC15 excluded 52
Output high voltage (2.5 V domain) VOH 1.8 V VDD = 2.5 V, IOH = -1.5, -3, -7, -11 mA; PC13/PC14/PC15 excluded 52
I/O max frequency, drive 2 mA fmax(IO)out 75 MHz CL = 5 pF, VDD = 3.3 V (DS_CFGy 0xx, 2 mA) 53
I/O max frequency, drive 4 mA fmax(IO)out 90 MHz CL = 10 pF, VDD = 3.3 V (4 mA) 53
I/O max frequency, drive 8 mA fmax(IO)out 100 MHz CL = 20 pF, VDD = 3.3 V (8 mA) 53
I/O max frequency, drive 12 mA fmax(IO)out 120 MHz CL = 30 pF, VDD = 3.3 V (12 mA) 53
I/O output delay, drive 2 mA t(IO)out 3.66 ns CL = 5 pF, VDD = 3.3 V (2 mA) 53
I/O output delay, drive 4 mA t(IO)out 3.5 ns CL = 10 pF, VDD = 3.3 V (4 mA) 53
I/O output delay, drive 8 mA t(IO)out 3.42 ns CL = 20 pF, VDD = 3.3 V (8 mA) 53
I/O output delay, drive 12 mA t(IO)out 3.34 ns CL = 30 pF, VDD = 3.3 V (12 mA) 53
I/O input delay t(IO)in 2 ns CL = 50 fF, VDD = 2.97 V, VDDD = 0.81 V 53
NRST input high voltage VIH(NRST) 2 V VDD = 3.3 V 54
NRST Schmitt hysteresis Vhys(NRST) 200 mV VDD = 3.3 V 54
NRST weak pull-up resistance RPU 30 50 70 KΩ VDD = 3.3 V 54
NRST input filtered pulse VF(NRST) 100 ns - 54
NRST input non-filtered pulse VNF(NRST) 300 ns - 55
TIM1/8 timer resolution time tres(TIM) 6.95 ns fTIMxCLK = 144 MHz 55
TIM1/8 external clock frequency fEXT 0 72 MHz CH1 to CH4, fTIMxCLK = 144 MHz 55
TIM1/8 16-bit counter clock period tCOUNTER 0.00695 455 μs Internal clock selected, fTIMxCLK = 144 MHz 55
TIM1/8 maximum count time tMAX_COUNT 29.8 s fTIMxCLK = 144 MHz 55
TIM2/3/4/5 timer resolution time tres(TIM) 13.9 ns fTIMxCLK = 72 MHz 55
TIM2/3/4/5 external clock frequency fEXT 0 36 MHz CH1 to CH4, fTIMxCLK = 72 MHz 55
TIM2/3/4/5 16-bit counter clock period tCOUNTER 0.0139 910 μs Internal clock selected, fTIMxCLK = 72 MHz 55
TIM2/3/4/5 maximum count time tMAX_COUNT 59.6 s fTIMxCLK = 72 MHz 55
ADC supply voltage VDDA 1.8 3.6 V - 65
ADC clock frequency fADC 80 MHz - 65
ADC sampling rate, 12-bit fs 0.01 4.7 MHz 1.8V ≤ VDD ≤ 3.6V, 12-bit resolution 65
ADC sampling rate, 10-bit fs 0.012 6.1 MHz 1.8V ≤ VDD ≤ 3.6V, 10-bit resolution 65
ADC sampling rate, 8-bit fs 0.014 7.3 MHz 1.8V ≤ VDD ≤ 3.6V, 8-bit resolution 65
ADC sampling rate, 6-bit fs 0.0175 8.9 MHz 1.8V ≤ VDD ≤ 3.6V, 6-bit resolution 65
ADC power-up time tSTAB 6 10 20 μs - 65
ADC sampling switch resistance, fast channel RADC 137.6 Ω Fast channel, 3.6 V 65
ADC sampling switch resistance, slow channel RADC 147 Ω Slow channel, 3.6 V 65
ADC sampling time, fast channel tS 0.056 8.35 μs fADC = 80 MHz, fast channel, 12-bit 65
ADC sampling time, slow channel tS 0.056 8.35 μs fADC = 80 MHz, slow channel, 12-bit 65
ADC sampling period, fast channel Ts 4.5 601.5 1/fADC fADC = 80 MHz, fast channel, 12-bit 65
ADC sampling period, slow channel Ts 4.5 601.5 1/fADC fADC = 80 MHz, slow channel, 12-bit 65
ADC reference voltage VREF+ VREF+ 1.8 V max printed as VDDA 65
USB startup time tSTARTUP 1 μs USB transceiver startup 64
USB operating voltage VDD 3 3.6 V USB full-speed operation (correct function guaranteed down to 2.7 V per note 3) 64
USB differential input sensitivity VDI 0.2 V I(USBDP, USBDM) 64
USB differential common-mode range VCM 0.8 2.5 V Includes VDI range 64
USB single-ended receiver threshold VSE 1.3 2 V - 64
USB static output low VOL 0.3 V 1.5 kΩ RL to 3.6 V 64
USB static output high VOH 2.8 3.6 V 15 kΩ RL to VSS 64
USB rise time tr 4 20 ns CL ≤ 50 pF 64
USB fall time tf 4 20 ns CL ≤ 50 pF 64
USB rise/fall time matching trfm 90 110 % tr / tf 64
USB output crossover voltage VCRS 1.3 2 V - 64
USB output series matching resistance Rs 27 39 Ω External matching resistor placed near chip pin 64
I2C clock frequency, standard mode fSCL 0 100 KHz Standard mode 56
I2C clock frequency, fast mode fSCL 0 400 KHz Fast mode 56
I2C clock frequency, fast+ mode fSCL 0 1000 KHz Fast+ mode 56
I2C SDA setup time, standard mode tsu(SDA) 250 ns Standard mode 56
I2C SDA setup time, fast mode tsu(SDA) 100 ns Fast mode 56
I2C SDA setup time, fast+ mode tsu(SDA) 50 ns Fast+ mode 56
SPI1 clock frequency, master fSCLK 36 MHz Master mode 58
SD/SDIO clock frequency, data transfer fPP 0 48 MHz CL ≤ 30 pF 63

CAD (KiCad official)

  • Symbol: N32G451RCL7
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: n32g451rcl7-etched.step / n32g451rcl7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); n32g451rcl7.step / n32g451rcl7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nations Technologies Inc datasheet (76 pp, sha256 dbeae2e3a5d0603f, retrieved 2026-10-18, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF