component
N32G003F5S7
Public Made by Adomby adom
Nations(国民技术) Microcontrollers (MCU/MPU/SOC), TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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Datasheet
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README
markdownN32G003F5S7
Nations(国民技术) · Microcontrollers (MCU/MPU/SOC) · TSSOP-20
N32G003F5S7 from Nations(国民技术), in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PA14 | bidirectional | Standard 5 V I/O (TC) with alternate functions TIM1_CH2, TIM1_ETR, SPI_SCK, UART1_TX, BEEP and analog input AIN6; it is in analog input mode during and just after reset. |
| 2 | PB0 | bidirectional | Standard 5 V I/O (TC) with alternate functions UART1_TX, SPI_MISO, TIM1_CH1, BEEPN, EVENT_OUT, AIN7 and COMP_INP; it is in analog input mode during and just after reset. |
| 3 | PB1 | bidirectional | Standard 5 V I/O (TC) with alternate functions UART1_RX, SPI_MOSI, TIM1_CH4, TIM3_ETR, EVENT_OUT, AIN8 and COMP_INM; it is in analog input mode during and just after reset. |
| 4 | NRST/PA0 | bidirectional | Bidirectional reset pin with embedded weak pull-up (RPU 30 to 70 kΩ for 2 V to 5.5 V) that can be configured by option byte as the NRST pin or as a normal GPIO PA0; NRST input low level must be at or below 0.3 VDD. |
| 5 | PA1 | bidirectional | Standard 5 V I/O (TC) with alternate functions UART2_RX, I2C_SDA, TIM1_CH3, TIM3_CH1, TIM1_BKIN, WKUP0 (Power Down wake-up input), and AIN0; it is in analog input mode during and just after reset. |
| 6 | PA2 | bidirectional | Standard 5 V I/O (TC) with alternate functions UART1_TX, UART2_TX, I2C_SCL, TIM1_CH3N, TIM3_CH2, WKUP1 (Power Down wake-up input), and AIN1; it is in analog input mode during and just after reset. |
| 7 | VSS | power_in | Power ground reference for all voltages; all VSS and VDD pins must stay connected to the supply system within its allowed range, and the difference between ground pins must not exceed 50 mV. |
| 8 | PA8/SWDIO | bidirectional | Standard 5 V I/O (TC) used as the SWD data pin SWDIO, which is set to input pull-up after reset, with alternate functions UART2_TX, I2C_SDA, SPI_NSS, TIM1_CH4 and COMP_OUT. |
| 9 | VDD | power_in | Power supply with a standard operating range of 2 V to 5.5 V; the absolute maximum VDD to VSS is -0.3 V to 5.5 V. |
| 10 | PA3 | bidirectional | Standard 5 V I/O (TC) with alternate functions UART1_RX, SPI_NSS, TIM1_CH3N, TIM3_CH1, TIM3_CH2 and TIM1_CH4; it is in analog input mode during and just after reset. |
| 11 | PA5 | bidirectional | Standard 5 V I/O (TC) with alternate functions I2C_SDA, TIM1_BKIN, TIM1_CH1N, AIN2 and COMP_INP; it is in analog input mode during and just after reset. |
| 12 | PA4 | bidirectional | Standard 5 V I/O (TC) with alternate functions I2C_SCL, TIM1_CH3N, EVENT_OUT and COMP_INM; it is in analog input mode during and just after reset. |
| 13 | PA11 | bidirectional | Standard 5 V I/O (TC) with alternate functions TIM1_CH1, TIM1_CH1N, TIM1_CH3, TIM3_CH1, TIM3_CH2 and TIM1_CH4; it is in analog input mode during and just after reset. |
| 14 | PA13 | bidirectional | Standard 5 V I/O (TC) with alternate functions MCO, TIM1_CH1N, TIM1_CH2N, TIM1_CH4, TIM3_CH1, TIM3_CH2 and AIN5; it is in analog input mode during and just after reset. |
| 15 | PA15 | bidirectional | Standard 5 V I/O (TC) with alternate functions SPI_SCK, TIM1_CH2, TIM1_ETR, TIM3_CH1, TIM3_CH2 and TIM1_CH4; it is in analog input mode during and just after reset. |
| 16 | PA6 | bidirectional | Standard 5 V I/O (TC) with alternate functions SPI_MOSI, TIM1_CH1, TIM1_CH2N, TIM3_CH1, TIM3_CH2, TIM1_CH4 and TIM3_ETR; it is in analog input mode during and just after reset. |
| 17 | PA7 | bidirectional | Standard 5 V I/O (TC) with alternate functions SPI_MISO, TIM1_CH2, TIM1_CH3, TIM3_CH1, TIM3_CH2, TIM1_CH4 and UART2_RX; it is in analog input mode during and just after reset. |
| 18 | PA9/SWCLK | bidirectional | Standard 5 V I/O (TC) used as the SWD clock pin SWCLK, which is set to input pull-down after reset, with alternate functions UART2_TX, I2C_SCL, TIM1_BKIN, TIM3_ETR and UART2_RX (UART2_RX is not supported on A-version chips). |
| 19 | PA10 | bidirectional | Standard 5 V I/O (TC) with alternate functions TIM1_CH3, TIM1_CH3N, TIM3_CH1, TIM3_CH2, TIM1_CH4 and AIN3; it is in analog input mode during and just after reset. |
| 20 | PA12 | bidirectional | Standard 5 V I/O (TC) with alternate functions TIM1_CH2, TIM1_CH2N, TIM3_CH1, TIM3_CH2, TIM1_CH4, UART1_RX and AIN4; it is in analog input mode during and just after reset. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nations(国民技术) |
| Package | TSSOP-20 |
| Category | Embedded Processors & Controllers |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| fSCL I2C接口频率 | fSCL | 0 | 100 | KHz | 标准模式 | 36 | |
| fSCL I2C接口频率 | fSCL | 0 | 400 | KHz | 快速模式 | 36 | |
| fSCL I2C接口频率 | fSCL | 0 | 1000 | KHz | 快速+模式 | 36 | |
| 开始条件保持时间 | th(STA) | 4 | μs | 标准模式 | 36 | ||
| 开始条件保持时间 | th(STA) | 0.6 | μs | 快速模式 | 36 | ||
| 开始条件保持时间 | th(STA) | 0.26 | μs | 快速+模式 | 36 | ||
| SCL时钟低时间 | tw(SCLL) | 4.7 | μs | 标准模式 | 36 | ||
| SCL时钟低时间 | tw(SCLL) | 1.3 | μs | 快速模式 | 36 | ||
| SCL时钟低时间 | tw(SCLL) | 0.5 | μs | 快速+模式 | 36 | ||
| SCL时钟高时间 | tw(SCLH) | 4 | μs | 标准模式 | 36 | ||
| SCL时钟高时间 | tw(SCLH) | 0.6 | μs | 快速模式 | 36 | ||
| SCL时钟高时间 | tw(SCLH) | 0.26 | μs | 快速+模式 | 36 | ||
| 重复的开始条件建立时间 | tsu(STA) | 4.7 | μs | 标准模式 | 36 | ||
| 重复的开始条件建立时间 | tsu(STA) | 0.6 | μs | 快速模式 | 36 | ||
| 重复的开始条件建立时间 | tsu(STA) | 0.26 | μs | 快速+模式 | 36 | ||
| SDA数据保持时间 | th(SDA) | 3.4 | μs | 标准模式 | 36 | ||
| SDA数据保持时间 | th(SDA) | 0.9 | μs | 快速模式 | 36 | ||
| SDA数据保持时间 | th(SDA) | 0.4 | μs | 快速+模式 | 36 | ||
| SDA建立时间 | tsu(SDA) | 250 | ns | 标准模式 | 36 | ||
| SDA建立时间 | tsu(SDA) | 100 | ns | 快速模式 | 36 | ||
| SDA建立时间 | tsu(SDA) | 50 | ns | 快速+模式 | 36 | ||
| SDA和SCL上升时间 | tr(SDA)/tr(SCL) | 1000 | ns | 标准模式 | 36 | ||
| SDA和SCL上升时间 | tr(SDA)/tr(SCL) | 300 | ns | 快速模式 | 36 | ||
| SDA和SCL上升时间 | tr(SDA)/tr(SCL) | 120 | ns | 快速+模式 | 36 | ||
| SDA和SCL下降时间 | tf(SDA)/tf(SCL) | 300 | ns | 标准模式 | 36 | ||
| SDA和SCL下降时间 | tf(SDA)/tf(SCL) | 120 | ns | 快速+模式 | 36 | ||
| 停止条件建立时间 | tsu(STO) | 4 | μs | 标准模式 | 36 | ||
| 停止条件建立时间 | tsu(STO) | 0.6 | μs | 快速模式 | 36 | ||
| 停止条件建立时间 | tsu(STO) | 0.26 | μs | 快速+模式 | 36 | ||
| 停止条件至开始条件的时间(总线空闲) | tw(STO:STA) | 4.7 | μs | 标准模式 | 36 | ||
| 停止条件至开始条件的时间(总线空闲) | tw(STO:STA) | 1.3 | μs | 快速模式 | 36 | ||
| 停止条件至开始条件的时间(总线空闲) | tw(STO:STA) | 0.5 | μs | 快速+模式 | 36 | ||
| 标准和快速模式下由模拟滤波器抑制的尖峰脉冲宽度 | tSP | 0 | 35 | ns | 标准模式 | 36 | |
| 数据有效时间 | tv(SDA) | 3.45 | μs | 标准模式 | 36 | ||
| 数据有效时间 | tv(SDA) | 0.9 | μs | 快速模式 | 36 | ||
| 数据有效时间 | tv(SDA) | 0.45 | μs | 快速+模式 | 36 | ||
| 应答有效时间 | tv(ACK) | 3.45 | μs | 标准模式 | 36 | ||
| 应答有效时间 | tv(ACK) | 0.9 | μs | 快速模式 | 36 | ||
| 应答有效时间 | tv(ACK) | 0.45 | μs | 快速+模式 | 36 | ||
| SPI时钟频率 | fSCLK | 12 | MHz | 主模式 | 37 | ||
| SPI时钟上升和下降时间 | tr(SCLK)tf(SCLK) | 15 | ns | 负载电容：C = 30pF | 37 | ||
| SPI从输入时钟占空比 | DuCy(SCLK) | 30 | 70 | % | SPI从模式 | 37 | |
| 数据输入建立时间 | tsu(MI) | 5 | ns | 主模式 | 37 | ||
| 数据输入保持时间 | th(MI) | 5 | ns | 主模式 | 37 | ||
| 数据输入保持时间 | th(SI) | 4 | ns | 从模式 | 38 | ||
| 数据输出禁止时间 | tdis(SO) | 2 | 10 | ns | 从模式 | 38 | |
| 数据输出有效时间 | tv(SO) | 5 | ns | 从模式(使能边沿之后) | 38 | ||
| 数据输出保持时间 | th(SO) | 15 | ns | 从模式(使能边沿之后) | 38 | ||
| 数据输出保持时间 | th(MO) | 2 | ns | 主模式(使能边沿之后) | 38 | ||
| 工作电压范围 | 2 | 5.5 | V | 2 | |||
| 工作温度范围 | -40 | 105 | ℃ | 2 | |||
| ESD（HBM模型） | -4 | 4 | KV | HBM 模型 | 2 | ||
| ESD（CDM模型） | -1 | 1 | KV | CDM 模型 | 2 | ||
| 最高主频 | 48 | MHz | 1 |
CAD (KiCad official)
- Symbol:
N32G003F5S7 - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files:
n32g003f5s7-etched.step/n32g003f5s7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);n32g003f5s7.step/n32g003f5s7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nations(国民技术) datasheet (47 pp, sha256
13a34fa7564124f5, retrieved 2026-10-17, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).