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N32A455REL7

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Nations Technologies Inc Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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N32A455REL7

Nations Technologies Inc · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

N32A455REL7 from Nations Technologies Inc, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Backup-domain supply, 1.8-3.6 V, powers the RTC, the external 32 kHz oscillator and backup registers when VDD is off.
2 PC13-TAMPER-RTC bidirectional TC-type 3.3 V GPIO with TAMPER-RTC function, fed through a power switch limited to 3 mA, so as an output it is limited to 2 MHz mode, 30 pF load, and 3 mA total together with PC14 and PC15.
3 PC14-OSC32_IN bidirectional TC-type 3.3 V GPIO with OSC32_IN (LSE crystal input) function, subject to the same 3 mA power-switch limit and 2 MHz / 30 pF output restrictions as PC13.
4 PC15-OSC32_OUT bidirectional TC-type 3.3 V GPIO with OSC32_OUT (LSE crystal output) function, subject to the same 3 mA power-switch limit and 2 MHz / 30 pF output restrictions as PC13.
5 OSC_IN input High-speed external oscillator input for a 4-32 MHz crystal or resonator; after reset this pin is OSC_IN and software can remap it to PD0, which then works as a plain GPIO only.
6 OSC_OUT output High-speed external oscillator output for a 4-32 MHz crystal or resonator; after reset this pin is OSC_OUT and software can remap it to PD1, which then works as a plain GPIO only.
7 NRST bidirectional Active-low reset I/O with an internal pull-up (30-70 kOhm, 50 kOhm typical at 3.3 V), with pulses up to 100 ns filtered out.
8 PC0 bidirectional 3.3 V-tolerant analog-capable GPIO with ADC12_IN6, I2C3_SCL, COMP7_INM and UART6_TX alternate functions.
9 PC1 bidirectional 3.3 V-tolerant analog-capable GPIO with ADC12_IN7, I2C3_SDA, COMP7_INP and UART6_RX alternate functions.
10 PC2 bidirectional GPIO with ADC12_IN8, COMP7_OUT, UART7_TX, SPI3_NSS and I2S3_WS alternate functions; the pin table does not state its I/O structure or voltage tolerance.
11 PC3 bidirectional 3.3 V-tolerant analog-capable GPIO with ADC12_IN9, UART7_RX, SPI3_SCK, I2S3_CK, OPAMP3/OPAMP4 VINP and COMP5_INP alternate functions.
12 VSSA power_in Analog ground for the ADC, DAC, OPAMP and COMP blocks, which must be connected to VSS.
13 VDDA power_in Analog supply for the ADC, DAC, OPAMP and COMP blocks, 1.8-3.6 V, which must be connected to VDD (at most 300 mV difference during operation).
14 PA0-WKUP bidirectional 3.3 V-tolerant analog-capable GPIO with WKUP wake-up input, ADC1_IN1, USART2_CTS, TIM2/TIM5/TIM8 and COMP1 alternate functions.
15 PA1 bidirectional 3.3 V-tolerant analog-capable GPIO with USART2_RTS, ADC1_IN2, TIM5_CH2, TIM2_CH2, COMP1_INP, OPAMP1/OPAMP3 VINP and SPI3_MOSI alternate functions.
16 PA2 bidirectional 3.3 V-tolerant analog-capable GPIO with USART2_TX, TIM5_CH3, ADC12_IN11, TIM2_CH3, COMP2_OUT and OPAMP1/OPAMP2 VINM alternate functions.
17 PA3 bidirectional 3.3 V-tolerant analog-capable GPIO with USART2_RX, TIM5_CH4, ADC1_IN4, TIM2_CH4, OPAMP1 VINM/VINP and COMP5_INP alternate functions.
18 VSS_4 power_in Ground pin for the digital I/O and core, to be connected to the board ground.
19 VDD_4 power_in I/O and internal regulator supply, 1.8-3.6 V.
20 PA4 bidirectional 3.3 V-tolerant analog-capable GPIO with DAC_OUT1, SPI1_NSS, USART2_CK, ADC2_IN1, QSPI_NSS, I2C2_SCL and several COMP inverting-input alternate functions.
21 PA5 bidirectional 3.3 V-tolerant analog-capable GPIO with DAC_OUT2, SPI1_SCK, ADC2_IN2, QSPI_SCK, I2C2_SDA and several COMP inverting-input alternate functions.
22 PA6 bidirectional 3.3 V-tolerant analog-capable GPIO with SPI1_MISO, TIM8_BKIN, ADC1_IN3, TIM3_CH1, COMP1_OUT, QSPI_IO0, TIM1_BKIN and OPAMP1_VOUT alternate functions.
23 PA7 bidirectional 3.3 V-tolerant analog-capable GPIO with SPI1_MOSI, TIM8_CH1N, ADC2_IN4, TIM3_CH2, QSPI_IO1, TIM1_CH1N, COMP2_INP and OPAMP1/OPAMP2 VINP alternate functions.
24 PC4 bidirectional 3.3 V-tolerant analog-capable GPIO with ADC2_IN5, QSPI_IO2, UART7_TX, I2C3_SCL, OPAMP3_VINM and COMP4/COMP5 alternate functions.
25 PC5 bidirectional 3.3 V-tolerant analog-capable GPIO with ADC2_IN12, QSPI_IO3, UART7_RX, I2C3_SDA, OPAMP4_VINP, COMP4_OUT and COMP6_INP alternate functions.
26 PB0 bidirectional 3.3 V-tolerant analog-capable GPIO with ADC3_IN12, TIM3_CH3, TIM8_CH2N, TIM1_CH2N, UART6_TX, OPAMP2_VINP, COMP3_INP and COMP5_OUT alternate functions.
27 PB1 bidirectional 3.3 V-tolerant analog-capable GPIO with ADC2_IN3, TIM3_CH4, TIM8_CH3N, COMP4_OUT, TIM1_CH3N, OPAMP2_VOUT, UART6_RX, COMP2_INM and COMP1_OUT alternate functions.
28 PB2/BOOT1 bidirectional 3.3 V-tolerant analog-capable GPIO that also carries the BOOT1 boot-mode select, with ADC2_IN13, UART4_TX and SPI1_NSS alternate functions.
29 PB10 bidirectional Fail-safe 3.3 V-tolerant analog-capable GPIO (no current flows in from this pin when VDD is absent) with I2C2_SCL, USART3_TX, TIM2_CH3, COMP5_INM, OPAMP3/OPAMP4 VINM, COMP1_INP and COMP3_OUT alternate functions.
30 PB11 bidirectional 3.3 V-tolerant analog-capable GPIO with I2C2_SDA, USART3_RX, ADC3_IN1, TIM2_CH4, OPAMP3_VOUT, COMP2_INP and COMP5_OUT alternate functions.
31 VSS_1 power_in Ground pin for the digital I/O and core.
32 VDD_1 power_in I/O and internal regulator supply, 1.8-3.6 V.
33 PB12 bidirectional 3.3 V-tolerant analog-capable GPIO with SPI2_NSS, I2S2_WS, I2C2_SMBA, USART3_CK, TIM1_BKIN, CAN2_RX, ADC4_IN3, COMP3_INM, OPAMP4_VOUT and COMP4_OUT alternate functions.
34 PB13 bidirectional 3.3 V-tolerant analog-capable GPIO with SPI2_SCK, I2S2_CK, USART3_CTS, TIM1_CH1N, CAN2_TX, ADC3_IN5, UART5_TX and COMP4_INM alternate functions.
35 PB14 bidirectional 3.3 V-tolerant analog-capable GPIO with SPI2_MISO, TIM1_CH2N, USART3_RTS, ADC4_IN4, COMP3_INP and UART5_RX alternate functions.
36 PB15 bidirectional 3.3 V-tolerant analog-capable GPIO with SPI2_MOSI, I2S2_SD, TIM1_CH3N, ADC4_IN5 and COMP4_INP alternate functions.
37 PC6 bidirectional Fail-safe 3.3 V-tolerant analog-capable GPIO with I2S2_MCK, TIM8_CH1, SDIO_DAT6, TIM3_CH1, SPI2_NSS and I2S2_WS alternate functions.
38 PC7 bidirectional Fail-safe 3.3 V-tolerant analog-capable GPIO with I2S3_MCK, TIM8_CH2, SDIO_DAT7, I2C4_SDA, TIM3_CH2, SPI2_SCK, I2S2_CK and USART2_RTS alternate functions.
39 PC8 bidirectional Fail-safe 3.3 V-tolerant analog-capable GPIO with TIM8_CH3, SDIO_DAT0, TIM3_CH3, SPI2_MISO and USART2_TX alternate functions.
40 PC9 bidirectional Fail-safe 3.3 V-tolerant analog-capable GPIO with TIM8_CH4, SDIO_DAT1, TIM3_CH4, SPI2_MOSI, I2S2_SD, USART2_RX, COMP6_OUT, OPAMP3/OPAMP4 inputs and COMP4_INP alternate functions.
41 PA8 bidirectional Fail-safe 5 V-tolerant FT GPIO with USART1_CK, TIM1_CH1 and MCO alternate functions; the I/O-to-VDD voltage difference must stay below 3.6 V.
42 PA9 bidirectional Fail-safe 5 V-tolerant FT GPIO with USART1_TX, TIM1_CH2 and I2C4_SCL alternate functions; the I/O-to-VDD voltage difference must stay below 3.6 V.
43 PA10 bidirectional Fail-safe 5 V-tolerant FT GPIO with USART1_RX, TIM1_CH3 and I2C4_SDA alternate functions; the I/O-to-VDD voltage difference must stay below 3.6 V.
44 PA11 bidirectional Fail-safe 5 V-tolerant FT GPIO with USART1_CTS, CAN1_RX, TIM1_CH4, COMP1_OUT and COMP5_OUT alternate functions; the I/O-to-VDD voltage difference must stay below 3.6 V.
45 PA12 bidirectional Fail-safe 5 V-tolerant FT GPIO with USART1_RTS, CAN1_TX, TIM1_ETR, COMP2_OUT and COMP6_OUT alternate functions; the I/O-to-VDD voltage difference must stay below 3.6 V.
46 PA13 bidirectional Fail-safe 5 V-tolerant FT pin whose default function after reset is SWDIO/JTMS debug, with UART4_TX as an alternate function.
47 VSS_2 power_in Ground pin for the digital I/O and core.
48 VDD_2 power_in I/O and internal regulator supply, 1.8-3.6 V.
49 PA14 bidirectional Fail-safe 5 V-tolerant FT pin whose default function after reset is SWCLK/JTCK debug, with UART4_RX as an alternate function.
50 PA15 bidirectional Fail-safe 5 V-tolerant FT pin whose default function after reset is JTDI debug, with SPI3_NSS, I2S3_WS, TIM2_CH1_ETR, SPI1_NSS, USART2_CTS and TIM8_CH1N alternate functions.
51 PC10 bidirectional Fail-safe 3.3 V-tolerant analog-capable GPIO with UART4_TX, SDIO_DAT2, USART3_TX, SPI3_SCK, I2S3_CK, QSPI_NSS and COMP3_OUT alternate functions.
52 PC11 bidirectional Fail-safe 3.3 V-tolerant analog-capable GPIO with UART4_RX, SDIO_DAT3, USART3_RX, SPI3_MISO, QSPI_SCK and COMP4_OUT alternate functions.
53 PC12 bidirectional Fail-safe 3.3 V-tolerant analog-capable GPIO with UART5_TX, SDIO_CK, USART3_CK, SPI3_MOSI, I2S3_SD, QSPI_IO0 and TIM8_CH2N alternate functions.
54 PD2 bidirectional Fail-safe 3.3 V-tolerant analog-capable GPIO with TIM3_ETR, UART5_RX, SDIO_CMD, SPI3_NSS, I2S3_WS, QSPI_IO3 and TIM8_CH3N alternate functions.
55 PB3 bidirectional Fail-safe 5 V-tolerant FT pin whose default function after reset is JTDO debug, with TRACESWO, SPI3_SCK, I2S3_CK, TIM2_CH2, SPI1_SCK, USART2_RTS and TIM8_BKIN alternate functions.
56 PB4 bidirectional Fail-safe 5 V-tolerant FT pin whose default function after reset is NJTRST debug, with SPI3_MISO, TIM3_CH1, SPI1_MISO, USART2_TX and TIM8_ETR alternate functions.
57 PB5 bidirectional Fail-safe 5 V-tolerant FT GPIO with I2C1_SMBA, SPI3_MOSI, I2S3_SD, TIM3_CH2, SPI1_MOSI, CAN2_RX, USART2_RX and TIM1_BKIN alternate functions.
58 PB6 bidirectional Fail-safe 3.3 V-tolerant analog-capable GPIO with I2C1_SCL, TIM4_CH1, USART1_TX, CAN2_TX and COMP5_OUT alternate functions.
59 PB7 bidirectional Fail-safe 3.3 V-tolerant analog-capable GPIO with I2C1_SDA, TIM4_CH2, USART1_RX and COMP6_OUT alternate functions.
60 BOOT0 input Boot-mode select input which, together with BOOT1, chooses between main Flash, system memory or internal SRAM boot; it is an input with pull-down during reset.
61 PB8 bidirectional Fail-safe 3.3 V-tolerant analog-capable GPIO with TIM4_CH3, SDIO_DAT4, COMP1_OUT, I2C1_SCL, CAN1_RX and UART5_TX alternate functions.
62 PB9 bidirectional Fail-safe 3.3 V-tolerant analog-capable GPIO with TIM4_CH4, SDIO_DAT5, COMP2_OUT, I2C1_SDA, CAN1_TX and UART5_RX alternate functions.
63 VSS_3 power_in Ground pin for the digital I/O and core.
64 VDD_3 power_in I/O and internal regulator supply, 1.8-3.6 V; the datasheet requires the 4.7 uF decoupling capacitor on VDD3.

Key specifications

Parameter Value
Manufacturer Nations Technologies Inc
Package LQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Output low voltage, VDD=3.3V VOL 0.55 V VDD=3.3V, drive level 2/4/8/12 55
Output low voltage, VDD=2.5V VOL 0.45 V VDD=2.5V, drive level 2/4/8/12 55
Output low voltage, VDD=1.8V VOL 0.685 V VDD=1.8V, drive level 2/4/8/12 55
Output high voltage, VDD=3.3V VOH 2.4 V VDD=3.3V, drive level 2/4/8/12 55
Output high voltage, VDD=2.5V VOH 1.8 V VDD=2.5V, drive level 2/4/8/12 55
IO max output frequency, 2mA drive fmax(IO)out 75 MHz DS_CFGy=0 (2mA); CL=5pF, VDD=3.3V 56
IO max output frequency, 2mA drive fmax(IO)out 50 MHz DS_CFGy=0 (2mA); CL=5pF, VDD=2.5V 56
IO max output frequency, 2mA drive fmax(IO)out 30 MHz DS_CFGy=0 (2mA); CL=5pF, VDD=1.8V 56
IO output delay, 2mA drive t(IO)out 3.66 ns DS_CFGy=0 (2mA); CL=5pF, VDD=3.3V 56
IO output delay, 2mA drive t(IO)out 4.72 ns DS_CFGy=0 (2mA); CL=5pF, VDD=2.5V 56
IO output delay, 2mA drive t(IO)out 7.12 ns DS_CFGy=0 (2mA); CL=5pF, VDD=1.8V 56
IO input delay, 2mA drive t(IO)in 2 ns DS_CFGy=0 (2mA); CL=50fF, VDD=2.97V, VDDD=0.81V 56
IO max output frequency, 4mA drive fmax(IO)out 90 MHz PMODEy[1:0]=00/01 (4mA); CL=10pF, VDD=3.3V 56
IO max output frequency, 4mA drive fmax(IO)out 60 MHz PMODEy[1:0]=00/01 (4mA); CL=10pF, VDD=2.5V 56
IO max output frequency, 4mA drive fmax(IO)out 40 MHz PMODEy[1:0]=00/01 (4mA); CL=10pF, VDD=1.8V 56
IO output delay, 4mA drive t(IO)out 3.5 ns PMODEy[1:0]=00/01 (4mA); CL=10pF, VDD=3.3V 56
IO output delay, 4mA drive t(IO)out 4.5 ns PMODEy[1:0]=00/01 (4mA); CL=10pF, VDD=2.5V 56
IO output delay, 4mA drive t(IO)out 6.74 ns PMODEy[1:0]=00/01 (4mA); CL=10pF, VDD=1.8V 56
IO input delay, 4mA drive t(IO)in 2 ns PMODEy[1:0]=00/01 (4mA); CL=50fF, VDD=2.97V, VDDD=0.81V 56
IO max output frequency, 8mA drive fmax(IO)out 100 MHz PMODEy[1:0]=10 (8mA); CL=20pF, VDD=3.3V 56
IO max output frequency, 8mA drive fmax(IO)out 75 MHz PMODEy[1:0]=10 (8mA); CL=20pF, VDD=2.5V 56
IO max output frequency, 8mA drive fmax(IO)out 50 MHz PMODEy[1:0]=10 (8mA); CL=20pF, VDD=1.8V 56
IO output delay, 8mA drive t(IO)out 3.42 ns PMODEy[1:0]=10 (8mA); CL=20pF, VDD=3.3V 56
IO output delay, 8mA drive t(IO)out 4.73 ns PMODEy[1:0]=10 (8mA); CL=20pF, VDD=2.5V 56
IO output delay, 8mA drive t(IO)out 6.53 ns PMODEy[1:0]=10 (8mA); CL=20pF, VDD=1.8V 56
IO input delay, 8mA drive t(IO)in 2 ns PMODEy[1:0]=10 (8mA); CL=50fF, VDD=2.97V, VDDD=0.81V 56
IO max output frequency, 12mA drive fmax(IO)out 120 MHz PMODEy[1:0]=11 (12mA); CL=30pF, VDD=3.3V 56
IO max output frequency, 12mA drive fmax(IO)out 90 MHz PMODEy[1:0]=11 (12mA); CL=30pF, VDD=2.5V 56
IO max output frequency, 12mA drive fmax(IO)out 60 MHz PMODEy[1:0]=11 (12mA); CL=30pF, VDD=1.8V 56
IO output delay, 12mA drive t(IO)out 3.34 ns PMODEy[1:0]=11 (12mA); CL=30pF, VDD=3.3V 56
IO output delay, 12mA drive t(IO)out 4.26 ns PMODEy[1:0]=11 (12mA); CL=3pF, VDD=2.5V 56
IO output delay, 12mA drive t(IO)out 6.34 ns PMODEy[1:0]=11 (12mA); CL=3pF, VDD=1.8V 56
IO input delay, 12mA drive t(IO)in 2 ns PMODEy[1:0]=11 (12mA); CL=50fF, VDD=2.97V, VDDD=0.81V 56
NRST input high voltage, VDD=3.3V VIH(NRST) 2 V VDD = 3.3V 57
NRST Schmitt trigger hysteresis, VDD=3.3V Vhys(NRST) 200 mV VDD = 3.3 V 57
NRST weak pull-up equivalent resistance, VDD=3.3V RPU 30 50 70 kΩ VDD = 3.3 V 57
NRST input filtered pulse VF(NRST) 100 ns 57
NRST input non-filtered pulse VNF(NRST) 300 ns 57
TIM1/8 timer resolution time tres(TIM) 6.95 ns fTIMxCLK = 144MHz 58
TIM1/8 external timer clock frequency, CH1 to CH4 fEXT 72 MHz fTIMxCLK = 144MHz 58
TIM1/8 timer resolution ResTIM 16 bit 58
TIM1/8 16-bit counter clock period (internal clock) tCOUNTER 0.00695 455 μs fTIMxCLK = 144MHz 58
TIM1/8 maximum possible count tMAX_COUNT 29.8 s fTIMxCLK = 144MHz 58
TIM2/3/4/5 timer resolution time tres(TIM) 13.9 ns fTIMxCLK = 72MHz 58
TIM2/3/4/5 external timer clock frequency, CH1 to CH4 fEXT 36 MHz fTIMxCLK = 72MHz 58
TIM2/3/4/5 timer resolution ResTIM 16 bit 58
TIM2/3/4/5 16-bit counter clock period (internal clock) tCOUNTER 0.0139 910 μs fTIMxCLK = 72MHz 58
TIM2/3/4/5 maximum possible count tMAX_COUNT 59.6 s fTIMxCLK = 72MHz 58
I2C clock frequency, standard mode fSCL 0 100 KHz 标准模式 (standard mode) 59
I2C clock frequency, fast mode fSCL 0 400 KHz 快速模式 (fast mode) 59
I2C clock frequency, fast-plus mode fSCL 0 1000 KHz 快速+模式 (fast-plus mode) 59
SPI1 clock frequency, master mode fSCLK 18 MHz 主模式 (master mode) 61
SPI1 clock frequency, slave mode fSCLK 18 MHz 从模式 (slave mode) 61
SPI2/3 clock frequency, master mode fSCLK 36 MHz 主模式 (master mode) 61
SPI2/3 clock frequency, slave mode fSCLK 36 MHz 从模式 (slave mode) 61

CAD (KiCad official)

  • Symbol: N32A455REL7
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: n32a455rel7-etched.step / n32a455rel7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); n32a455rel7.step / n32a455rel7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nations Technologies Inc datasheet (80 pp, sha256 4babfe66e96b2640, retrieved 2026-10-20, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF