component
MX25U5121EMI-14G
Public Made by Adomby adom
MXIC Macronix NOR FLASH, SOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMX25U5121EMI-14G
MXIC Macronix · NOR FLASH · SOP-8
MX25U5121EMI-14G from MXIC Macronix, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CS# | input | Chip Select, active-low. Drive low to enable the flash and begin a serial transaction; drive high to deselect the device (puts SO into Hi-Z and forces the internal state machine back to Standby Mode). Must go high at a byte boundary for command execution. |
| 2 | SO/SIO1 | bidirectional | Serial Data Output in single/dual read; also serves as bidirectional Serial Data I/O bit 1 during 2x I/O read (DREAD) and 4x I/O read (4READ) modes. Data shifts out on the SCLK falling edge; Hi-Z when the chip is deselected. |
| 3 | WP#/SIO2 | bidirectional | Hardware Write Protect (active-low) when SRWD=1 in the Status Register - freezes the Status Register bits BP0/BP1/SRWD; also serves as bidirectional Serial Data I/O bit 2 during 4x I/O read (4READ) mode. Tie high through a pull-up if write protection is not used. |
| 4 | GND | power_in | Ground reference for both digital core and I/O. Connect to the system 0V rail. |
| 5 | SI/SIO0 | bidirectional | Serial Data Input for single-I/O mode; bidirectional Serial Data I/O bit 0 during 2x I/O read (DREAD) and 4x I/O read (4READ) modes. Data is latched on the rising edge of SCLK. |
| 6 | SCLK | input | Serial Clock input from the SPI master. Supports Mode 0 (CPOL=0, CPHA=0) and Mode 3 (CPOL=1, CPHA=0) up to 70MHz for fast-read commands. Input data is latched on the rising edge and output data shifts on the falling edge. |
| 7 | HOLD#/SIO3 | bidirectional | HOLD input (active-low): while CS# is low, driving HOLD# low pauses serial communication (SO goes Hi-Z, SI and SCLK are don't-care) without deselecting the chip; it does not stop an in-progress program/erase. Also serves as bidirectional Serial Data I/O bit 3 during 4x I/O read (4READ) mode. Tie high through a pull-up if HOLD is not used. |
| 8 | VCC | power_in | Single-supply power input, 1.65V to 2.0V (nominal 1.8V) for read, erase, and program. Latch-up protected to 100mA from -1V to VCC+1V. Decouple with a 0.1uF ceramic capacitor close to the pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | MXIC Macronix |
| Package | SOP-8 |
| Category | Memory |
| Pins | 8 |
Ordering variants
Same part, different packaging or reel option.
MX25U5121EMI-14GMX25U5121EMI-14GOI-14GMX25U5121EMI-14GZUI-14G
CAD (KiCad official)
- Symbol:
MX25U5121EMI-14G - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
mx25u5121emi-14g-etched.step/mx25u5121emi-14g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mx25u5121emi-14g.step/mx25u5121emi-14g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: MXIC Macronix datasheet (None pp, sha256
730ae0636462f2e9, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).