component
MX25R4035FZUIL0TR
Public Made by Adomby adom
MXIC(Macronix) NOR FLASH, USON-8(2x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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MX25R4035FZUIL0TR
MXIC(Macronix) · NOR FLASH · USON-8(2x3)
MX25R4035FZUIL0TR from MXIC(Macronix), in a USON-8(2x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CS# | input | Chip Select input for the serial interface, as listed in the pin description table (CS# is the only function given for this pin). |
| 2 | SO/SIO1 | bidirectional | Serial Data Output for 1 x I/O mode, and Serial Data Input & Output (SIO1) for 4 x I/O read mode. |
| 3 | WP#/SIO2 | bidirectional | Write Protection, active low, or Serial Data Input & Output (SIO2) for 4 x I/O read mode; the internal pull-up stays active while the pin is not physically connected in the system, and is disabled if the system connects to it. |
| 4 | GND | power_in | Ground. |
| 5 | SI/SIO0 | bidirectional | Serial Data Input for 1 x I/O mode, and Serial Data Input & Output (SIO0) for 4 x I/O read mode. |
| 6 | SCLK | input | Clock Input for the serial interface. |
| 7 | RESET#/SIO3 | bidirectional | Hardware Reset pin, active low, or Serial Data Input & Output (SIO3) for 4 x I/O read mode; for this part number (MX25R4035FZUIL0, RESET# option) the pin is RESET#, and the internal pull-up stays active while the pin is not physically connected. |
| 8 | VCC | power_in | Power Supply; the operating range for this part is 1.65V-3.6V per the ordering information. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | MXIC(Macronix) |
| Package | USON-8(2x3) |
| Category | Memory |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Ambient Operating Temperature | -40 | 85 | °C | Industrial grade | 64 | ||
| Storage Temperature | -65 | 150 | °C | 64 | |||
| Applied Input Voltage | -0.5 | V | 64 | ||||
| Applied Output Voltage | -0.5 | V | 64 | ||||
| VCC to Ground Potential | -0.5 | 4 | V | MX25R (1.65V-3.6V) | 64 | ||
| Device operation range (VCC) | 1.65 | 3.6 | V | Device operation range (Table 16 note 1) | 66 | ||
| Input Load Current | ILI | -2 | 2 | uA | VCC = VCC Max, VIN = VCC or GND | 66 | |
| Output Leakage Current | ILO | -2 | 2 | uA | VCC = VCC Max, VOUT = VCC or GND | 66 | |
| VCC Standby Current | ISB1 | 5 | 24 | uA | VIN = VCC or GND, CS# = VCC | 66 | |
| Deep Power-down Current | ISB2 | 0.007 | 0.35 | uA | VIN = VCC or GND, CS# = VCC | 66 | |
| VCC Read current | ICC1 | 2.8 | 4.5 | mA | f=16MHz (4x I/O) SCLK=0.1VCC/0.9VCC, SO=Open | 66 | |
| VCC Read current | ICC1 | 2.2 | 4 | mA | f=33MHz SCLK=0.1VCC/0.9VCC, SO=Open | 66 | |
| VCC Program Current (PP) | ICC2 | 3.5 | 6 | mA | Program in Progress, CS# = VCC | 66 | |
| VCC Write Status Register (WRSR) Current | ICC3 | 3.1 | 6 | mA | Program status register in progress, CS#=VCC | 66 | |
| VCC Sector/Block (64K) Erase Current (SE/BE) | ICC4 | 3.1 | 6 | mA | Erase in Progress, CS#=VCC | 66 | |
| VCC Chip Erase Current (CE) | ICC5 | 3.1 | 6 | mA | Erase in Progress, CS#=VCC | 66 | |
| High Voltage Applied at WP# pin | Vhv | 7 | 8 | V | Test Condition, VCC=2.0V | 66 | |
| Input Low Voltage | VIL | -0.5 | V | 66 | |||
| Output Low Voltage | VOL | 0.2 | V | IOL = 100uA | 66 | ||
| Clock Frequency (fSCLK) | fSCLK | 33 | MHz | FAST_READ, RDSFDP, PP, SE, BE32K, BE, CE, DP, RES, WREN, WRDI, RDID, RDSR, WRSR | 68 | ||
| Clock Frequency for READ instructions | fRSCLK | 33 | MHz | for READ instructions | 68 | ||
| Clock Frequency for 2READ/DREAD instructions | fTSCLK | 16 | MHz | for 2READ/DREAD instructions | 68 | ||
| Clock Frequency for 4READ/QREAD instructions | fQ | 16 | MHz | for 4READ/QREAD instructions | 68 | ||
| Clock Frequency for 4PP (Quad page program) | f4PP | 33 | MHz | for 4PP (Quad page program) | 68 | ||
| Clock High Time (Normal Read) | tCH | 13 | ns | Normal Read (fRSCLK) | 68 | ||
| Clock Low Time (Normal Read) | tCL | 13 | ns | Normal Read (fRSCLK) | 68 | ||
| CS# Active Setup Time (relative to SCLK) | tSLCH | 5 | ns | 68 | |||
| CS# Not Active Hold Time (relative to SCLK) | tCHSL | 5 | ns | 68 | |||
| Data In Setup Time | tDVCH | 2 | ns | 68 | |||
| Data In Hold Time | tCHDX | 3 | ns | 68 | |||
| CS# Active Hold Time (relative to SCLK) | tCHSH | 5 | ns | 68 | |||
| CS# Not Active Setup Time (relative to SCLK) | tSHCH | 5 | ns | 68 | |||
| CS# Deselect Time | tSHSL | 15 | ns | From Read to next Read | 68 | ||
| CS# Deselect Time | tSHSL | 30 | ns | From Write/Erase/Program to Read Status Register | 68 | ||
| Output Disable Time | tSHQZ | 8 | ns | 68 | |||
| Clock Low to Output Valid | tCLQV | 12 | ns | Loading: 30pF | 68 | ||
| Clock Low to Output Valid | tCLQV | 10 | ns | Loading: 15pF | 68 | ||
| Output Hold Time | tCLQX | 0 | ns | 68 | |||
| Write Protect Setup Time | tWHSL | 10 | ns | 68 | |||
| Write Protect Hold Time | tSHWL | 10 | ns | 68 | |||
| CS# High to Deep Power-down Mode | tDP | 10 | us | 68 | |||
| Delay Time for Release from Deep Power-Down Mode once entering Deep Power-Down Mode | tDPDD | 30 | us | 68 | |||
| CS# Toggling Time before Release from Deep Power-Down Mode | tCRDP | 20 | ns | 68 | |||
| Write Status Register Cycle Time | tW | 10 | 30 | ms | 68 | ||
| Erase Suspend Latency | tESL | 60 | us | 69 | |||
| Program Suspend Latency | tPSL | 60 | us | 69 | |||
| Latency between Program Resume and next Suspend | tPRS | 0.3 | us | 69 | |||
| Latency between Erase Resume and next Suspend | tERS | 0.3 | us | 69 | |||
| Byte-Program | tBP | 40 | 100 | us | 69 | ||
| Page Program Cycle Time | tPP | 3.2 | 10 | ms | 69 | ||
| Sector Erase Cycle Time | tSE | 58 | 240 | ms | 69 | ||
| Sector Erase Cycle Time | tSE | 36 | 210 | ms | Applied Vhv at WP# pin | 69 | |
| Block Erase (32KB) Cycle Time | tBE32K | 0.4 | 1.75 | s | 69 | ||
| Block Erase (32KB) Cycle Time | tBE32K | 0.22 | 1.05 | s | Applied Vhv at WP# pin | 69 | |
| Block Erase (64KB) Cycle Time | tBE | 0.8 | 3.5 | s | 69 | ||
| Block Erase (64KB) Cycle Time | tBE | 0.43 | 2.1 | s | Applied Vhv at WP# pin | 69 | |
| Chip Erase Cycle Time | tCE | 7.5 | 15 | s | 69 | ||
| Chip Erase Cycle Time | tCE | 2.7 | 8 | s | Applied Vhv at WP# pin | 69 | |
| VCC Rise Time | tVR | 500000 | us/V | 72 |
CAD (KiCad official)
- Symbol:
MX25R4035FZUIL0TR - Footprint:
Package_SON:SON-8-1EP_3x2mm_P0.5mm_EP1.4x1.6mm - 3D model: USON-8(2x3), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
mx25r4035fzuil0tr-etched.step/mx25r4035fzuil0tr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mx25r4035fzuil0tr.step/mx25r4035fzuil0tr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: MXIC(Macronix) datasheet (85 pp, sha256
263cc75f780ebe1b, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# MX25R4035FZUIL0TR
**MXIC(Macronix)** · NOR FLASH · USON-8(2x3)
MX25R4035FZUIL0TR from MXIC(Macronix), in a USON-8(2x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CS# | input | Chip Select input for the serial interface, as listed in the pin description table (CS# is the only function given for this pin). |
| 2 | SO/SIO1 | bidirectional | Serial Data Output for 1 x I/O mode, and Serial Data Input & Output (SIO1) for 4 x I/O read mode. |
| 3 | WP#/SIO2 | bidirectional | Write Protection, active low, or Serial Data Input & Output (SIO2) for 4 x I/O read mode; the internal pull-up stays active while the pin is not physically connected in the system, and is disabled if the system connects to it. |
| 4 | GND | power_in | Ground. |
| 5 | SI/SIO0 | bidirectional | Serial Data Input for 1 x I/O mode, and Serial Data Input & Output (SIO0) for 4 x I/O read mode. |
| 6 | SCLK | input | Clock Input for the serial interface. |
| 7 | RESET#/SIO3 | bidirectional | Hardware Reset pin, active low, or Serial Data Input & Output (SIO3) for 4 x I/O read mode; for this part number (MX25R4035FZUIL0, RESET# option) the pin is RESET#, and the internal pull-up stays active while the pin is not physically connected. |
| 8 | VCC | power_in | Power Supply; the operating range for this part is 1.65V-3.6V per the ordering information. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | MXIC(Macronix) |
| Package | USON-8(2x3) |
| Category | Memory |
| Pins | 9 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Ambient Operating Temperature | | -40 | | 85 | °C | Industrial grade | 64 |
| Storage Temperature | | -65 | | 150 | °C | | 64 |
| Applied Input Voltage | | -0.5 | | | V | | 64 |
| Applied Output Voltage | | -0.5 | | | V | | 64 |
| VCC to Ground Potential | | -0.5 | | 4 | V | MX25R (1.65V-3.6V) | 64 |
| Device operation range (VCC) | | 1.65 | | 3.6 | V | Device operation range (Table 16 note 1) | 66 |
| Input Load Current | ILI | -2 | | 2 | uA | VCC = VCC Max, VIN = VCC or GND | 66 |
| Output Leakage Current | ILO | -2 | | 2 | uA | VCC = VCC Max, VOUT = VCC or GND | 66 |
| VCC Standby Current | ISB1 | | 5 | 24 | uA | VIN = VCC or GND, CS# = VCC | 66 |
| Deep Power-down Current | ISB2 | | 0.007 | 0.35 | uA | VIN = VCC or GND, CS# = VCC | 66 |
| VCC Read current | ICC1 | | 2.8 | 4.5 | mA | f=16MHz (4x I/O) SCLK=0.1VCC/0.9VCC, SO=Open | 66 |
| VCC Read current | ICC1 | | 2.2 | 4 | mA | f=33MHz SCLK=0.1VCC/0.9VCC, SO=Open | 66 |
| VCC Program Current (PP) | ICC2 | | 3.5 | 6 | mA | Program in Progress, CS# = VCC | 66 |
| VCC Write Status Register (WRSR) Current | ICC3 | | 3.1 | 6 | mA | Program status register in progress, CS#=VCC | 66 |
| VCC Sector/Block (64K) Erase Current (SE/BE) | ICC4 | | 3.1 | 6 | mA | Erase in Progress, CS#=VCC | 66 |
| VCC Chip Erase Current (CE) | ICC5 | | 3.1 | 6 | mA | Erase in Progress, CS#=VCC | 66 |
| High Voltage Applied at WP# pin | Vhv | 7 | | 8 | V | Test Condition, VCC=2.0V | 66 |
| Input Low Voltage | VIL | -0.5 | | | V | | 66 |
| Output Low Voltage | VOL | | | 0.2 | V | IOL = 100uA | 66 |
| Clock Frequency (fSCLK) | fSCLK | | | 33 | MHz | FAST_READ, RDSFDP, PP, SE, BE32K, BE, CE, DP, RES, WREN, WRDI, RDID, RDSR, WRSR | 68 |
| Clock Frequency for READ instructions | fRSCLK | | | 33 | MHz | for READ instructions | 68 |
| Clock Frequency for 2READ/DREAD instructions | fTSCLK | | | 16 | MHz | for 2READ/DREAD instructions | 68 |
| Clock Frequency for 4READ/QREAD instructions | fQ | | | 16 | MHz | for 4READ/QREAD instructions | 68 |
| Clock Frequency for 4PP (Quad page program) | f4PP | | | 33 | MHz | for 4PP (Quad page program) | 68 |
| Clock High Time (Normal Read) | tCH | 13 | | | ns | Normal Read (fRSCLK) | 68 |
| Clock Low Time (Normal Read) | tCL | 13 | | | ns | Normal Read (fRSCLK) | 68 |
| CS# Active Setup Time (relative to SCLK) | tSLCH | 5 | | | ns | | 68 |
| CS# Not Active Hold Time (relative to SCLK) | tCHSL | 5 | | | ns | | 68 |
| Data In Setup Time | tDVCH | 2 | | | ns | | 68 |
| Data In Hold Time | tCHDX | 3 | | | ns | | 68 |
| CS# Active Hold Time (relative to SCLK) | tCHSH | 5 | | | ns | | 68 |
| CS# Not Active Setup Time (relative to SCLK) | tSHCH | 5 | | | ns | | 68 |
| CS# Deselect Time | tSHSL | 15 | | | ns | From Read to next Read | 68 |
| CS# Deselect Time | tSHSL | 30 | | | ns | From Write/Erase/Program to Read Status Register | 68 |
| Output Disable Time | tSHQZ | | | 8 | ns | | 68 |
| Clock Low to Output Valid | tCLQV | | | 12 | ns | Loading: 30pF | 68 |
| Clock Low to Output Valid | tCLQV | | | 10 | ns | Loading: 15pF | 68 |
| Output Hold Time | tCLQX | 0 | | | ns | | 68 |
| Write Protect Setup Time | tWHSL | 10 | | | ns | | 68 |
| Write Protect Hold Time | tSHWL | 10 | | | ns | | 68 |
| CS# High to Deep Power-down Mode | tDP | | | 10 | us | | 68 |
| Delay Time for Release from Deep Power-Down Mode once entering Deep Power-Down Mode | tDPDD | | | 30 | us | | 68 |
| CS# Toggling Time before Release from Deep Power-Down Mode | tCRDP | 20 | | | ns | | 68 |
| Write Status Register Cycle Time | tW | | 10 | 30 | ms | | 68 |
| Erase Suspend Latency | tESL | | | 60 | us | | 69 |
| Program Suspend Latency | tPSL | | | 60 | us | | 69 |
| Latency between Program Resume and next Suspend | tPRS | 0.3 | | | us | | 69 |
| Latency between Erase Resume and next Suspend | tERS | 0.3 | | | us | | 69 |
| Byte-Program | tBP | | 40 | 100 | us | | 69 |
| Page Program Cycle Time | tPP | | 3.2 | 10 | ms | | 69 |
| Sector Erase Cycle Time | tSE | | 58 | 240 | ms | | 69 |
| Sector Erase Cycle Time | tSE | | 36 | 210 | ms | Applied Vhv at WP# pin | 69 |
| Block Erase (32KB) Cycle Time | tBE32K | | 0.4 | 1.75 | s | | 69 |
| Block Erase (32KB) Cycle Time | tBE32K | | 0.22 | 1.05 | s | Applied Vhv at WP# pin | 69 |
| Block Erase (64KB) Cycle Time | tBE | | 0.8 | 3.5 | s | | 69 |
| Block Erase (64KB) Cycle Time | tBE | | 0.43 | 2.1 | s | Applied Vhv at WP# pin | 69 |
| Chip Erase Cycle Time | tCE | | 7.5 | 15 | s | | 69 |
| Chip Erase Cycle Time | tCE | | 2.7 | 8 | s | Applied Vhv at WP# pin | 69 |
| VCC Rise Time | tVR | | | 500000 | us/V | | 72 |
## CAD (KiCad official)
- Symbol: `MX25R4035FZUIL0TR`
- Footprint: `Package_SON:SON-8-1EP_3x2mm_P0.5mm_EP1.4x1.6mm`
- 3D model: USON-8(2x3), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files: `mx25r4035fzuil0tr-etched.step` / `mx25r4035fzuil0tr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mx25r4035fzuil0tr.step` / `mx25r4035fzuil0tr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [MXIC(Macronix) datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8555014201449414656) (85 pp, sha256 `263cc75f780ebe1b`, retrieved 2026-10-19, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/mx25r4035fzuil0tr-datasheet.pdf)