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MX25R1635FZUIH0

MACRONIX · Global Sourcing Parts · USON-8(2x3)

MX25R1635FZUIH0 from MACRONIX, in a USON-8(2x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CS# input Chip Select input that selects the device; the datasheet gives no further limits for this pin.
2 SO/SIO1 bidirectional Serial Data Output for 1 x I/O mode, and serial data input and output for 4 x I/O read mode.
3 WP#/SIO2 bidirectional Write Protection, active low, or serial data input and output for 4 x I/O read mode; the internal pull-up stays active only while this pin is not physically connected in the system.
4 GND power_in Ground reference for the device.
5 SI/SIO0 bidirectional Serial Data Input for 1 x I/O mode, and serial data input and output for 4 x I/O read mode.
6 SCLK input Clock Input for serial command, address and data timing.
7 RESET#/SIO3 bidirectional Hardware Reset pin, active low, for this MPN (RESET# option per the ordering table), or serial data input and output for 4 x I/O read mode; the internal pull-up stays active only while this pin is not physically connected in the system.
8 VCC power_in Power supply, 1.65V-3.6V for this part per the ordering information.
9 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer MACRONIX
Package USON-8(2x3)
Category Global Sourcing Parts
Pins 9

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Ambient Operating Temperature (Industrial grade) -40 85 °C 64
Storage Temperature -65 150 °C 64
Applied Input Voltage -0.5 V 64
Applied Output Voltage -0.5 V 64
VCC to Ground Potential MX25R (1.65V-3.6V) -0.5 4 V 64
Input Capacitance CIN 6 pF TA = 25°C, f = 1.0 MHz, VIN = 0V 64
Output Capacitance COUT 8 pF TA = 25°C, f = 1.0 MHz, VOUT = 0V 64
VCC Rise Time tVR 500000 us/V 72
Input Load Current ILI -2 2 uA VCC = VCC Max, VIN = VCC or GND 67
Output Leakage Current ILO -2 2 uA VCC = VCC Max, VOUT = VCC or GND 67
Leakage Current while WP# at Vhv Iwph 30 uA VCC < 2.1V 67
VCC Standby Current ISB1 9 50 uA VIN = VCC or GND, CS# = VCC 67
Deep Power-down Current ISB2 0.007 0.35 uA VIN = VCC or GND, CS# = VCC 67
VCC Read Current ICC1 3.8 6.5 mA f=80MHz, SCLK=0.1VCC/0.9VCC, SO=Open 67
VCC Read Current (2x I/O) ICC1 4.2 6.5 mA f=80MHz (2x I/O), SCLK=0.1VCC/0.9VCC, SO=Open 67
VCC Read Current (4x I/O) ICC1 4.2 6.5 mA f=33MHz (4x I/O), SCLK=0.1VCC/0.9VCC, SO=Open 67
VCC Read Current (4x I/O, 80MHz) ICC1 6.5 9 mA f=80MHz (4x I/O), SCLK=0.1VCC/0.9VCC, SO=Open 67
VCC Program Current (PP) ICC2 5.8 10 mA Program in Progress, CS# = VCC 67
VCC Write Status Register Current (WRSR) ICC3 3.5 10 mA Program status register in progress, CS#=VCC 67
VCC Sector/Block (64K) Erase Current (SE/BE) ICC4 3.5 10 mA Erase in Progress, CS#=VCC 67
VCC Chip Erase Current (CE) ICC5 4 10 mA Erase in Progress, CS#=VCC 67
High Voltage Applied at WP# pin Vhv 7 8 V Test Condition, VCC=2.0V 67
Input Low Voltage VIL -0.5 0.2 V 67
Input High Voltage VIH 0.8 V 67
Output Low Voltage VOL 0.2 V IOL = 100uA 67
Output High Voltage VOH -0.2 V IOH = -100uA 67
Erase Suspend Latency tESL 40 us 71
Program Suspend Latency tPSL 40 us 71
Latency between Program Resume and next Suspend tPRS 0.3 us 71
Latency between Erase Resume and next Suspend tERS 0.3 us 71
Byte-Program tBP 32 100 us 71
Byte-Program (Applied Vhv at WP# pin) tBP 32 100 us Applied Vhv at WP# pin 71
Page Program Cycle Time tPP 0.85 4 ms 71
Page Program Cycle Time (Applied Vhv at WP# pin) tPP 0.6 3.6 ms Applied Vhv at WP# pin 71
Sector Erase Cycle Time tSE 40 240 ms 71
Sector Erase Cycle Time (Applied Vhv at WP# pin) tSE 36 210 ms Applied Vhv at WP# pin 71
Block Erase (32KB) Cycle Time tBE32K 0.24 1.5 s 71
Block Erase (32KB) Cycle Time (Applied Vhv at WP# pin) tBE32K 0.22 1.05 s Applied Vhv at WP# pin 71
Block Erase (64KB) Cycle Time tBE 0.48 3 s 71
Block Erase (64KB) Cycle Time (Applied Vhv at WP# pin) tBE 0.43 2.1 s Applied Vhv at WP# pin 71
Chip Erase Cycle Time tCE 13 38 s 71
Chip Erase Cycle Time (Applied Vhv at WP# pin) tCE 12 34 s Applied Vhv at WP# pin 71
Write Status Register Cycle Time (High Performance Mode) tW 9.5 20 ms 75
Erase/Program Cycle 100000 cycles 75

CAD (KiCad official)

  • Symbol: MX25R1635FZUIH0
  • Footprint: Package_SON:SON-8-1EP_3x2mm_P0.5mm_EP1.4x1.6mm
  • 3D model: USON-8(2x3), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: mx25r1635fzuih0-etched.step / mx25r1635fzuih0-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mx25r1635fzuih0.step / mx25r1635fzuih0.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: MACRONIX datasheet (86 pp, sha256 c460d612ac50864b, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF