# MWCT1012VLF

**NXP Semicon** · Power Management Specialized - PMIC · LQFP-48(7x7)

MWCT1012VLF from NXP Semicon, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | TCK | input | JTAG test clock input that synchronizes the test logic and shifts serial data to the JTAG/EOnCE port, with an internal pull-up and Schmitt-trigger input for noise immunity. |
| 2 | RESET | input | Active-low hardware reset input that places the device in the reset state when asserted low, with a Schmitt-trigger input and internal reset de-asserted synchronously after a fixed number of clocks. |
| 3 | GPIOC0 | bidirectional | Port C GPIO (default after reset) that can alternately serve as EXTAL, the crystal oscillator input for an external crystal or ceramic resonator, or as external clock input CLKIN0. |
| 4 | GPIOC1 | bidirectional | Port C GPIO (default after reset) that can alternately serve as XTAL, the crystal oscillator output for an external crystal or ceramic resonator. |
| 5 | GPIOC2 | bidirectional | Port C GPIO (default after reset) whose alternates on WCT1012 include SCI0 transmit data TXD0, crossbar input XB_IN2, buffered clock output CLKO0 and quad timer B channel 0 TB0. |
| 6 | GPIOC3 | bidirectional | Port C GPIO (default after reset) whose alternates include quad timer A channel 0 TA0, analog comparator A output CMPA_O, SCI0 receive data RXD0 and external clock input CLKIN1. |
| 7 | GPIOC4 | bidirectional | Port C GPIO (default after reset) whose alternates on WCT1012 include quad timer A channel 1 TA1, analog comparator B output CMPB_O, crossbar input XB_IN8 and external watchdog monitor output EWM_OUT. |
| 8 | GPIOA4 | bidirectional | Port A GPIO (default after reset); the datasheet assigns its analog functions (ANA4, CMPD_IN0, ANC8) only to WCT1011 and WCT1013, so no analog function is stated for WCT1012. |
| 9 | GPIOA0 | bidirectional | Port A GPIO (default after reset) that can alternately serve as ADCA analog input channel 0, analog comparator A input CMPA_IN3, or analog comparator C output CMPC_O. |
| 10 | GPIOA1 | bidirectional | Port A GPIO (default after reset) that can alternately serve as ADCA analog input channel 1 or analog comparator A input CMPA_IN0. |
| 11 | GPIOA2 | bidirectional | Port A GPIO (default after reset) that can alternately serve as ADCA analog input channel 2, ADCA high reference VREFHA (selected by ADC control register) or analog comparator A input CMPA_IN1. |
| 12 | GPIOA3 | bidirectional | Port A GPIO (default after reset) that can alternately serve as ADCA analog input channel 3, ADCA low reference VREFLA (selected by ADC control register) or analog comparator A input CMPA_IN2. |
| 13 | GPIOC5 | bidirectional | Port C GPIO (default after reset) that can alternately serve as the 12-bit DAC output DAC_O or crossbar input XB_IN7. |
| 14 | GPIOB4 | bidirectional | Port B GPIO (default after reset); the datasheet assigns its analog functions (ANB4, CMPC_IN1, ANC12) only to WCT1011 and WCT1013, so no analog function is stated for WCT1012. |
| 15 | VDDA | power_in | Analog power supply pin that supplies 3.3 V to the analog modules and must be connected to a clean analog supply. |
| 16 | VSSA | power_in | Analog ground pin that supplies the analog ground to the analog modules and must be connected to a clean power supply. |
| 17 | GPIOB0 | bidirectional | Port B GPIO (default after reset) that can alternately serve as ADCB analog input channel 0 or analog comparator B input CMPB_IN3. |
| 18 | GPIOB1 | bidirectional | Port B GPIO (default after reset) that can alternately serve as ADCB analog input channel 1 or analog comparator B input CMPB_IN0; the DACB_O function is stated for WCT1011 only. |
| 19 | VCAP1 | power_out | Core voltage regulator output that requires a 2.2 µF or greater bypass capacitor between this pin and VSS for proper device operation. |
| 20 | GPIOB2 | bidirectional | Port B GPIO (default after reset) that can alternately serve as ADCB analog input channel 2, ADCB high reference VREFHB (selected by ADC control register) or analog comparator C input CMPC_IN3. |
| 21 | GPIOB3 | bidirectional | Port B GPIO (default after reset) that can alternately serve as ADCB analog input channel 3, ADCB low reference VREFLB (selected by ADC control register) or analog comparator C input CMPC_IN0. |
| 22 | VSS1 | power_in | I/O ground pin that provides ground to the on-chip digital module. |
| 23 | GPIOC6 | bidirectional | Port C GPIO (default after reset) that can alternately serve as quad timer A channel 2 TA2, crossbar input XB_IN3 or the analog comparator reference input CMP_REF (SS0 is stated for WCT1011 only). |
| 24 | GPIOC7 | bidirectional | Port C GPIO (default after reset) that can alternately serve as SPI0 slave select SS0 or SCI0 transmit data TXD0. |
| 25 | GPIOC8 | bidirectional | Port C GPIO (default after reset) that can alternately serve as SPI0 master-in/slave-out MISO0 (high-impedance when slave not selected), SCI0 receive data RXD0 or crossbar input XB_IN9. |
| 26 | GPIOC9 | bidirectional | Port C GPIO (default after reset) that can alternately serve as SPI0 serial clock SCLK0 or crossbar input XB_IN4. |
| 27 | GPIOC10 | bidirectional | Port C GPIO (default after reset) that can alternately serve as SPI0 master-out/slave-in MOSI0, crossbar input XB_IN5 or SPI0 MISO0. |
| 28 | GPIOF0 | bidirectional | Port F GPIO (default after reset) that can alternately serve as crossbar input XB_IN6, quad timer B channel 2 TB2 (stated for WCT1012 and WCT1013) or SPI1 serial clock SCLK1. |
| 29 | GPIOC11 | bidirectional | Port C GPIO (default after reset) that can alternately serve as CAN transmit CANTX, IIC1 serial clock SCL1 (stated for WCT1012 and WCT1013) or SCI1 transmit data TXD1. |
| 30 | GPIOC12 | bidirectional | Port C GPIO (default after reset) that can alternately serve as CAN receive CANRX, IIC1 serial data SDA1 (stated for WCT1012 and WCT1013) or SCI1 receive data RXD1. |
| 31 | VSS2 | power_in | I/O ground pin that provides ground to the on-chip digital module. |
| 32 | VDD2 | power_in | I/O power pin that supplies 3.3 V to the on-chip digital module. |
| 33 | GPIOE0 | bidirectional | Port E GPIO (default after reset) that can alternately serve as NanoEdge eFlexPWM sub-module 0 output B or input capture B. |
| 34 | GPIOE1 | bidirectional | Port E GPIO (default after reset) that can alternately serve as NanoEdge eFlexPWM sub-module 0 output A or input capture A. |
| 35 | GPIOE2 | bidirectional | Port E GPIO (default after reset) that can alternately serve as NanoEdge eFlexPWM sub-module 1 output B or input capture B. |
| 36 | GPIOE3 | bidirectional | Port E GPIO (default after reset) that can alternately serve as NanoEdge eFlexPWM sub-module 1 output A or input capture A. |
| 37 | GPIOC13 | bidirectional | Port C GPIO (default after reset) that can alternately serve as quad timer A channel 3 TA3, crossbar input XB_IN6 or external watchdog monitor output EWM_OUT. |
| 38 | GPIOF1 | bidirectional | Port F GPIO (default after reset) that can alternately serve as buffered clock output CLKO1, crossbar input XB_IN7 or analog comparator D output CMPD_O. |
| 39 | GPIOE4 | bidirectional | Port E GPIO (default after reset) that can alternately serve as NanoEdge eFlexPWM sub-module 2 output B or input capture B, or crossbar input XB_IN2. |
| 40 | GPIOE5 | bidirectional | Port E GPIO (default after reset) that can alternately serve as NanoEdge eFlexPWM sub-module 2 output A or input capture A, or crossbar input XB_IN3. |
| 41 | GPIOC14 | bidirectional | Port C GPIO (default after reset) that can alternately serve as IIC0 serial data SDA0, crossbar output XB_OUT4 or PWM fault input 4 (stated for WCT1011 only). |
| 42 | GPIOC15 | bidirectional | Port C GPIO (default after reset) that can alternately serve as IIC0 serial clock SCL0, crossbar output XB_OUT5 or PWM fault input 5 (stated for WCT1011 only). |
| 43 | VCAP2 | power_out | Core voltage regulator output that requires a 2.2 µF or greater bypass capacitor between this pin and VSS for proper device operation. |
| 44 | VDD3 | power_in | I/O power pin that supplies 3.3 V to the on-chip digital module. |
| 45 | VSS3 | power_in | I/O ground pin that provides ground to the on-chip digital module. |
| 46 | TDO | tri_state | JTAG/EOnCE test data output that is tri-stateable, provides serial output data, and changes on the falling edge of TCK (default function after reset; GPIOD1 is the alternate). |
| 47 | TMS | input | JTAG test mode select input sampled on the rising edge of TCK with an on-chip pull-up; keep debug capability by tying to VDD through a 2.2 kΩ resistor, otherwise tie directly to VDD. |
| 48 | TDI | input | JTAG test data input that is sampled on the rising edge of TCK and has an on-chip pull-up resistor (default function after reset; GPIOD0 is the alternate). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | NXP Semicon |
| Package | LQFP-48(7x7) |
| Category | Power Management ICs |
| Pins | 48 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage Range | VDD | -0.3 |  | 4 | V |  | 4 |
| Analog Supply Voltage Range | VDDA | -0.3 |  | 4 | V |  | 4 |
| ADC High Voltage Reference | VREFHx | -0.3 |  | 4 | V |  | 4 |
| Voltage difference VDD to VDDA | ΔVDD | -0.3 |  | 0.3 | V |  | 4 |
| Voltage difference VSS to VSSA | ΔVss | -0.3 |  | 0.3 | V |  | 4 |
| Digital Input Voltage Range | VIN | -0.3 |  | 5.5 | V | Pin Group 1 | 4 |
| RESET Input Voltage Range | VIN_RESET | -0.3 |  | 4 | V | Pin Group 2 | 4 |
| Oscillator Input Voltage Range | VOSC | -0.4 |  | 4 | V | Pin Group 4 | 4 |
| Analog Input Voltage Range | VINA | -0.3 |  | 4 | V | Pin Group 3 | 4 |
| Input clamp current, per pin | VIC |  |  | -5 | mA | VIN < VSS, 0.3 V | 4 |
| Output clamp current, per pin | VOC | -20 |  | 20 | mA | I/O configured as push-pull mode | 4 |
| Contiguous pin DC injection current, regional limit (sum of 16 contiguous pins) | IIcont | -25 |  | 25 | mA |  | 4 |
| Output Voltage Range (normal push-pull mode) | VOUT | -0.3 |  | 4 | V | Pin Group 1,2 | 4 |
| Output Voltage Range (open drain mode) | VOUTOD | -0.3 |  | 5.5 | V | Pin Group 1 | 4 |
| Ambient Temperature | TA | -40 |  | 105 | °C |  | 4 |
| Storage Temperature Range | TSTG | -55 |  | 150 | °C |  | 4 |
| Solder temperature, lead-free | TSDR |  |  | 260 | °C |  | 5 |
| ESD for Human Body Model (HBM) |  | -2000 |  | 2000 | V |  | 5 |
| Supply Voltage | VDD, VDDA | 2.7 | 3.3 | 3.6 | V |  | 6 |
| ADC (Cyclic) Reference Voltage High | VREFHA, VREFHB | 3 |  |  | V |  | 6 |
| Voltage difference VDD to VDDA | ΔVDD | -0.1 | 0 | 0.1 | V |  | 6 |
| Voltage difference VSS to VSSA | ΔVss | -0.1 | 0 | 0.1 | V |  | 6 |
| Input Voltage High (digital inputs) | VIH |  |  | 5.5 | V | Pin Group 1 | 6 |
| Oscillator Input Voltage High | VIHOSC | 2 |  |  | V | XTAL driven by an external clock source | 6 |
| Oscillator Input Voltage Low | VILOSC | -0.3 |  | 0.8 | V |  | 6 |
| Output Source Current High (at VOH min.), low drive strength | IOH |  |  | -2 | mA | Programmed for low drive strength; Pin Group 1 | 6 |
| Output Source Current High (at VOH min.), high drive strength | IOH |  |  | -9 | mA | Programmed for high drive strength; Pin Group 1 | 6 |
| Output Source Current Low (at VOL max.), low drive strength | IOL |  |  | 2 | mA | Programmed for low drive strength; Pin Group 1,2 | 7 |
| Output Source Current Low (at VOL max.), high drive strength | IOL |  |  | 9 | mA | Programmed for high drive strength; Pin Group 1,2 | 7 |
| Output Voltage Low | VOL |  |  | 0.5 | V | IOL = IOLmax | 7 |
| Digital Input Current High (pull-up enabled or disabled) | IIH | -2.5 | 0 | 2.5 | µA | VIN = 2.4 V to 5.5 V; Pin Group 1 | 7 |
| Comparator Input Current High | IIHC | -2 | 0 | 2 | µA | VIN = VDDA | 7 |
| Comparator Input Current Low | IILC | -2 | 0 | 2 | µA | VIN = 0V | 7 |
| Internal Pull-Up Resistance | RPull-Up | 20 |  | 50 | kΩ |  | 7 |
| Internal Pull-Down Resistance | RPull-Down | 20 |  | 50 | kΩ |  | 7 |
| Output Current High Impedance State | IOZ | -1 | 0 | 1 | µA |  | 7 |
| GPIO pin interrupt pulse width | TINT_Pulse | 1.5 |  |  | Bus clock |  | 7 |
| Port rise and fall time (high drive strength), slew disabled | TPort_H_DIS | 5.5 |  | 15.1 | ns | 2.7 ≤ VDD ≤ 3.6 V | 7 |
| Port rise and fall time (high drive strength), slew enabled | TPort_H_EN | 1.5 |  | 6.8 | ns | 2.7 ≤ VDD ≤ 3.6 V | 8 |
| Port rise and fall time (low drive strength), slew disabled | TPort_L_DIS | 8.2 |  | 17.8 | ns | 2.7 ≤ VDD ≤ 3.6 V | 8 |
| Port rise and fall time (low drive strength), slew enabled | TPort_L_EN | 3.2 |  | 9.2 | ns | 2.7 ≤ VDD ≤ 3.6 V | 8 |
| Device (system and core) clock frequency | fSYSCLK | 0 |  | 100 | MHz |  | 8 |
| Bus clock | fBUS |  |  | 100 | MHz | WCT1012 and WCT1013 maximum bus clock (note 10) | 8 |
| POR delay from VDD reaching 2.7 V to first instruction executes | TPOR | 199 |  | 225 | µs | over the operating temperature range | 8 |
| STOP mode to RUN mode | TS2R | 6.79 |  | 7.27 | µs |  | 8 |
| Minimum RESET Assertion Duration | tRA | 16 |  |  | ns |  | 11 |
| Delay from Interrupt Assertion to Fetch of first instruction (exiting STOP mode) | tIF | 361.3 |  | 570.9 | ns |  | 11 |
| TCK clock pulse width | tPW | 50 |  |  | ns |  | 11 |
| TCK low to TDO data valid | tDV |  |  | 30 | ns |  | 11 |
| Frequency of operation (external clock driver) | fOSC |  |  | 50 | MHz |  | 12 |
| Clock pulse width | tPW | 8 |  |  | ns |  | 12 |
| PLL output frequency | fOP_PLL |  |  | 400 | MHz |  | 12 |
| PLL lock time | tLock_PLL | 35.5 |  | 73.2 | µs |  | 12 |
| Allowed Duty Cycle of input reference | tDC_PLL | 40 | 50 | 60 | % |  | 12 |
| Frequency of operation (external crystal or resonator) | fXOSC | 4 | 8 | 16 | MHz |  | 12 |
| 8 MHz Output Frequency, RUN mode | fROSC_8M | 7.84 | 8 | 8.16 | MHz | RUN mode, 0 °C to 105 °C | 12 |
| 8 MHz Output Frequency, RUN mode | fROSC_8M | 7.76 | 8 | 8.24 | MHz | RUN mode, -40 °C to 105 °C | 12 |
| 200 kHz Output Frequency, RUN mode | fROSC_200k | 194 | 200 | 206 | kHz | RUN mode, -40 °C to 105 °C | 12 |
| 32 kHz Output Frequency, RUN mode | fROSC_32k | 30.1 | 32 | 33.9 | kHz | RUN mode, -40 °C to 105 °C | 12 |
| Die junction temperature | TJ | -40 |  | 125 | °C |  | 22 |

## CAD (KiCad official)

- Symbol: `MWCT1012VLF`
- Footprint: `Package_QFP:LQFP-48_7x7mm_P0.5mm`
- 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
- 3D model files: `mwct1012vlf-etched.step` / `mwct1012vlf-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mwct1012vlf.step` / `mwct1012vlf.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [NXP Semicon datasheet](https://www.nxp.com/docs/en/data-sheet/MWCT1012VLF.pdf) (44 pp, sha256 `b65721f2f360c474`, retrieved 2026-10-30, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/mwct1012vlf-datasheet.pdf)