MUN5236DW1T1G

{
  "slug": "mun5236dw1t1g",
  "version": "0.1.0",
  "type": "component",
  "description": "onsemi Digital Transistors, SOT-363. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
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    "transistors-thyristors",
    "mun5236dw1t1g",
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    "mun5236dw1t1g.step",
    "mun5236dw1t1g.lbr",
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    "docs/mun5236dw1t1g-datasheet.pdf",
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    "viewers/footprint.html",
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  "component": {
    "mpn": "MUN5236DW1T1G",
    "manufacturer": "onsemi",
    "package": "SOT-363",
    "pin_count": 6,
    "category": "Transistors/Thyristors",
    "subcategory": "Digital Transistors",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589985942485299200",
    "parts": {
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      "lbr": "mun5236dw1t1g.lbr"
    },
    "distributor_links": {
      "lcsc": "C891832",
      "mouser": "863-MUN5236DW1T1G"
    },
    "distributor_check": {
      "checked_at": "2026-10-09T21:41:14Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "deferred",
        "error": "shared DigiKey quota guard: 547 calls left today"
      },
      "mouser": {
        "pn": "863-MUN5236DW1T1G",
        "status": "found"
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    "pins": [
      {
        "number": "1",
        "name": "EMITTER 2",
        "type": "passive",
        "description": "Emitter of transistor Q2 (the Q2 bias-resistor NPN); the shared device limits apply, including VCEO 50 Vdc and continuous IC 100 mAdc."
      },
      {
        "number": "2",
        "name": "BASE 2",
        "type": "input",
        "description": "Base of transistor Q2, which connects to the integrated bias network (R1 = 100 kΩ, R2 = 100 kΩ); input forward voltage is rated at 40 Vdc and input reverse voltage at 10 Vdc."
      },
      {
        "number": "3",
        "name": "COLLECTOR 1",
        "type": "passive",
        "description": "Collector of transistor Q1; the shared device limits apply, including VCBO 50 Vdc and continuous IC 100 mAdc."
      },
      {
        "number": "4",
        "name": "EMITTER 1",
        "type": "passive",
        "description": "Emitter of transistor Q1 (the Q1 bias-resistor NPN); the shared device limits apply, including VCEO 50 Vdc and continuous IC 100 mAdc."
      },
      {
        "number": "5",
        "name": "BASE 1",
        "type": "input",
        "description": "Base of transistor Q1, which connects to the integrated bias network (R1 = 100 kΩ, R2 = 100 kΩ); input forward voltage is rated at 40 Vdc and input reverse voltage at 10 Vdc."
      },
      {
        "number": "6",
        "name": "COLLECTOR 2",
        "type": "passive",
        "description": "Collector of transistor Q2; the shared device limits apply, including VCBO 50 Vdc and continuous IC 100 mAdc."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The datasheet does not name a pin style for the MUN5236DW1 itself. Pin assignments are taken from th; The pin connection figure shows Q1 and Q2 with pin labels (3)(2)(1) and (4)(5)(6) but does not map e; Pin types are inferred from the transistor terminal roles: emitters and collectors as passive, bases"
        ],
        "pages_sent": 9,
        "cost_usd": 0.068,
        "at": "2026-10-09T21:38:43"
      },
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        "pages": 9,
        "sha256": "21ef24b2fc8f2df2",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 6,
        "described": 6,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
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}