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MT8870DNR1

Microchip Tech · Telecommunication Interface ICs · SSOP-20-208mil

MT8870DNR1 from Microchip Tech, in a SSOP-20-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	IN+	input	Non-inverting input of the front-end differential op-amp.
2	IN-	input	Inverting input of the front-end differential op-amp.
3	GS	output	Gain select pin giving access to the front-end differential amplifier output so a feedback resistor can be connected for gain adjustment.
4	VRef	power_in	Reference voltage output, nominally VDD/2, used to bias the inputs at mid-rail; 2.3 V to 2.7 V at VDD = 5.0 V with no load.
5	INH	input	Logic high inhibits detection of tones representing characters A, B, C and D; the pin is internally pulled down.
6	PWDN	input	Active-high power-down input that powers down the device and stops the oscillator; the pin is internally pulled down.
7	NC	unconnected	No connection.
8	OSC1	input	Clock input; a 3.579545 MHz crystal is connected between OSC1 and OSC2 to complete the internal oscillator.
9	OSC2	output	Clock output; a 3.579545 MHz crystal between OSC1 and OSC2 completes the oscillator, with a maximum load of 30 pF on OSC2.
10	VSS	power_in	Ground, 0 V typical.
11	TOE	input	Three-state output enable; logic high enables outputs Q1 to Q4 and the pin is pulled up internally, while logic low puts Q1 to Q4 in high impedance.
12	Q1	tri_state	Three-state decoded tone data output, bit 1, providing the code for the last valid tone pair when enabled by TOE.
13	Q2	tri_state	Three-state decoded tone data output, bit 2, providing the code for the last valid tone pair when enabled by TOE.
14	Q3	tri_state	Three-state decoded tone data output, bit 3, providing the code for the last valid tone pair when enabled by TOE.
15	Q4	tri_state	Three-state decoded tone data output, bit 4, providing the code for the last valid tone pair when enabled by TOE.
16	NC	unconnected	No connection.
17	StD	output	Delayed steering output that goes high when a tone pair has been registered and the output latch updated, and returns low when St/GT falls below VTSt.
18	ESt	output	Early steering output that goes high once a valid tone pair is detected and returns low on any momentary loss of signal condition.
19	St/GT	bidirectional	Steering input and guard-time output; a voltage above VTSt registers the tone pair, and a voltage below VTSt frees the device for a new tone pair.
20	VDD	power_in	Positive power supply, +5 V typical (4.75 V to 5.25 V recommended operating range).

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	SSOP-20-208mil
Category	Communication Interface Chip/UART/485/232
Pins	20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
DC Power Supply Voltage (absolute maximum)	VDD			7	V		10
Current at any pin (other than supply)	II			10	mA		10
Storage temperature	TSTG	-65		150	°C		10
Package power dissipation	PD			500	mW		10
DC Power Supply Voltage	VDD	4.75	5	5.25	V		10
Operating Temperature	TO	-40		85	°C		10
Crystal/Clock Freq. Tolerance	∆fc	-0.1		0.1	%		10
Standby supply current	IDDQ		10	25	µA	PWDN=VDD	10
Operating supply current	IDD		3	9	mA		10
Low level input voltage	VIL			1.5	V	VDD=5.0 V	10
High level input voltage	VIH	3.5			V	VDD=5.0 V	10
Input leakage current	IIH/IIL			0.1	µA	VIN=VSS or VDD	10
Pull up (source) current	ISO		7.5	20	µA	TOE (pin 10)=0, VDD=5.0 V	10
Pull down (sink) current	ISI		15	45	µA	INH=5.0 V, PWDN=5.0 V, VDD=5.0 V	10
Steering threshold voltage	VTSt	2.2	2.4	2.5	V	VDD = 5.0 V	10
Output low (sink) current	IOL	1	2.5		mA	VOUT=0.4 V	11
Output high (source) current	IOH	0.4	0.8		mA	VOUT=4.6 V	11
VRef output voltage	VRef	2.3	2.5	2.7	V	No load, VDD = 5.0V	11
VRef output resistance	ROR			1	kΩ		11
Input leakage current (gain setting amplifier)	IIN			100	nA	VSS ≤ VIN ≤ VDD	11
Input offset voltage	VOS			25	mV		11
Power supply rejection	PSRR	50			dB	1 kHz	11
Common mode rejection	CMRR	40			dB	0.75 V ≤ VIN ≤ 4.25 V biased at VRef =2.5 V	11
DC open loop voltage gain	AVOL	32			dB		11
Output voltage swing	VO	4			Vpp	Load ≥ 100 kΩ to VSS @ GS	11
Maximum capacitive load (GS)	CL			100	pF		11
Resistive load (GS)	RL	50			kΩ		11
Valid input signal levels (each tone of composite signal)		-29		1	dBm	Notes 1,2,3,5,6,9	12
Valid input signal levels (each tone of composite signal)		27.5		869	mVRMS	Notes 1,2,3,5,6,9	12
Negative twist accept		8			dB	Notes 2,3,6,9,12	12
Positive twist accept		8			dB	Notes 2,3,6,9,12	12
Frequency deviation accept		-1.5		1.5	%	Notes 2,3,5,9	12
Frequency deviation accept (± 2 Hz term)		-2		2	Hz	Notes 2,3,5,9	12
Frequency deviation reject		-3.5		3.5	%	Notes 2,3,5,9	12
Third tone tolerance				-16	dB	Notes 2,3,4,5,9,10	12
Noise tolerance				-12	dB	Notes 2,3,4,5,7,9,10	12
Dial tone tolerance				22	dB	Notes 2,3,4,5,8,9,11	12
Tone present detect time	tDP	5	11	14	ms	Note 1	14
Tone absent detect time	tDA	0.5	4	8.5	ms	Note 1	14
Tone duration accept	tREC	40			ms	Note 2	14
Tone duration reject	tREC			20	ms	Note 2	14
Interdigit pause accept	tID	40			ms	Note 2	14
Interdigit pause reject	tDO			20	ms	Note 2	14
Propagation delay (St to Q)	tPQ		8	11	µs	TOE=VDD	14
Propagation delay (St to StD)	tPStD		12	16	µs	TOE=VDD	14
Output data set up (Q to StD)	tQStD	3.4			µs	TOE=VDD	14
Propagation delay (TOE to Q ENABLE)	tPTE			50	ns	load of 10 kΩ, 50 pF	14
Propagation delay (TOE to Q DISABLE)	tPTD			300	ns	load of 10 kΩ, 50 pF	14
Power-up time	tPU			30	ms	Note 3	14
Power-down time	tPD			20	ms		14
Clock input rise time	tLHCL			110	ns	Ext. clock	14
Clock input fall time	tHLCL			110	ns	Ext. clock	14
Clock input duty cycle	DCCL	40	50	60	%	Ext. clock	14
Capacitive load (OSC2)	CLO			30	pF		14
Crystal/Clock Frequency	fc		3.57954		MHz		10
Input impedance (IN+, IN-)	RIN		10		MΩ	@ 1 kHz	10
Power consumption	PO		15		mW	fc=3.579545 MHz	10
Unity gain bandwidth (gain setting amplifier)	fC		0.3		MHz		11
Common mode range	VCM		2.5		Vpp	No Load	11

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
contacts		tin	MT8870DSR1-1 18 Pin SOIC* Tape & Reel *Pb Free Matte Tin	1

CAD (KiCad official)

Symbol: MT8870DNR1
Footprint: Package_SO:SSOP-20_5.3x7.2mm_P0.65mm
3D model: SSOP-20-208mil (KiCad packages3D, STEP)
3D model files: mt8870dnr1-etched.step / mt8870dnr1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mt8870dnr1.step / mt8870dnr1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (19 pp, sha256 02ae9b549be6ca37, retrieved 2026-10-29, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF