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MSPM0L1304SRHBR

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Texas Instruments Others, VQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MSPM0L1304SRHBR

Texas Instruments · Others · VQFN-32-EP(5x5)

MSPM0L1304SRHBR from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PA0 bidirectional 5-V tolerant open-drain GPIO with wake from SHUTDOWN, muxed with UART1_TX, I2C0_SDA, TIMG1_C0, SPI0_CS1 and default BSL I2C data (BSLSDA); needs a pullup for output high.
2 PA1 bidirectional 5-V tolerant open-drain GPIO with wake from SHUTDOWN, muxed with UART1_RX, I2C0_SCL, TIMG1_C1 and default BSL I2C clock (BSLSCL); needs a pullup for output high.
3 NRST input Active-low reset input that must be pulled high to VDD for the device to start.
4 VDD power_in Power supply, 1.62 V to 3.6 V recommended, with 10 µF plus 0.1 µF decoupling to VSS.
5 VSS power_in Ground supply.
6 PA2 bidirectional Standard GPIO that also serves as ROSC for an external 100-kΩ resistor to VSS improving SYSOSC accuracy, muxed with TIMG1_C1 and SPI0_CS0.
7 PA3 bidirectional Standard GPIO muxed with TIMG2_C0, SPI0_CS1, UART1_CTS and COMP0_OUT.
8 PA4 bidirectional Standard GPIO muxed with TIMG2_C1, SPI0_POCI and UART1_RTS.
9 PA5 bidirectional High-speed GPIO muxed with TIMG0_C0, SPI0_PICO and FCC_IN.
10 PA6 bidirectional Standard GPIO muxed with TIMG0_C1 and SPI0_SCK.
11 PA7 bidirectional Standard GPIO muxed with COMP0_OUT, CLK_OUT and TIMG1_C0.
12 PA8 bidirectional Standard GPIO muxed with UART0_TX, SPI0_CS0, UART1_RTS and TIMG2_C0.
13 PA9 bidirectional Standard GPIO muxed with UART0_RX, SPI0_PICO, UART1_CTS, TIMG2_C1 and CLK_OUT.
14 PA10 bidirectional High-speed GPIO muxed with UART1_TX, SPI0_POCI, I2C0_SDA, TIMG4_C0 and CLK_OUT.
15 PA11 bidirectional Standard GPIO muxed with UART1_RX, SPI0_SCK, I2C0_SCL, TIMG4_C1 and COMP0_OUT.
16 PA12 bidirectional Standard GPIO muxed with UART0_CTS, TIMG0_C0 and FCC_IN.
17 PA13 bidirectional Standard GPIO muxed with UART0_RTS, TIMG0_C1 and UART1_RX.
18 PA14 bidirectional Standard GPIO muxed with UART1_CTS, CLK_OUT, UART1_TX and TIMG1_C0.
19 PA15 bidirectional Standard GPIO with ADC0 analog input A9, muxed with UART1_RTS, I2C1_SCL, SPI0_CS2 and TIMG4_C1.
20 PA16 bidirectional Standard GPIO with ADC0 input A8 and OPA1_OUT, muxed with COMP0_OUT, I2C1_SDA, SPI0_POCI, TIMG0_C0 and FCC_IN.
21 PA17 bidirectional Standard GPIO with wake from SHUTDOWN and OPA1_IN1- input, muxed with UART0_TX, I2C1_SCL, SPI0_SCK, TIMG4_C0 and SPI0_CS1.
22 PA18 bidirectional GPIO with wake from SHUTDOWN, ADC0 input A7, OPA1_IN0+ and GPAMP_IN-, BSL_invoke pin, muxed with UART0_RX, SPI0_PICO, I2C1_SDA and TIMG4_C1.
23 PA19 bidirectional High-speed GPIO that carries the SWDIO serial wire debug data, muxed with I2C1_SDA and SPI0_POCI.
24 PA20 bidirectional Standard GPIO with ADC0 input A6 and COMP0_IN1+ that carries the SWCLK debug clock, muxed with I2C1_SCL and TIMG4_C0.
25 PA21 bidirectional Standard GPIO with ADC0 input A5 and VREF- external reference ground input, muxed with TIMG2_C0, UART0_CTS and UART0_TX.
26 PA22 bidirectional Standard GPIO with ADC0 input A4, GPAMP_OUT and OPA0_OUT, default BSL UART receive (BSLRX), muxed with UART0_RX, TIMG2_C1, UART0_RTS, CLK_OUT and UART1_RX.
27 PA23 bidirectional Standard GPIO with VREF+ external reference input and COMP0_IN1-, default BSL UART transmit (BSLTX), muxed with UART0_TX, SPI0_CS3, TIMG0_C0, UART0_CTS and UART1_TX.
28 PA24 bidirectional Standard GPIO with ADC0 input A3 and OPA0_IN1-/OPA0_IN0-, muxed with SPI0_CS2, TIMG0_C1 and UART0_RTS.
29 PA25 bidirectional Standard GPIO with ADC0 input A2 and OPA0_IN0+, muxed with TIMG4_C1, UART0_TX and SPI0_PICO.
30 PA26 bidirectional Standard GPIO with ADC0 input A1, GPAMP_IN+ and COMP0_IN0+, muxed with TIMG1_C0, UART0_RX and SPI0_POCI.
31 PA27 bidirectional Standard GPIO with ADC0 input A0 and COMP0_IN0-, muxed with TIMG1_C1 and SPI0_CS3.
32 VCORE power_out Regulated core supply output that must connect only to a 0.47 µF (470 nF) capacitor to VSS, with no external voltage or load applied.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-32-EP(5x5)
Category Others
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage (abs max) VDD -0.3 4.1 V At VDD pin, with respect to VSS 16
Input voltage, 5-V tolerant open-drain pins (abs max) VI -0.3 5.5 V Applied to any 5-V tolerant open-drain pins 16
Current into VDD pin IVDD 80 mA -40℃ ≤ Tj ≤ 130℃ 16
Current into VDD pin IVDD 100 mA -40℃ ≤ Tj ≤ 85℃ 16
Current out of VSS pin IVSS 80 mA -40℃ ≤ Tj ≤ 130℃ 16
Current out of VSS pin IVSS 100 mA -40℃ ≤ Tj ≤ 85℃ 16
Current for SDIO pin IIO 6 mA Current sunk or sourced by SDIO pin 16
Current for HSIO pin IIO 6 mA Current sunk or sourced by HSIO pin 16
Current for ODIO pin IIO 20 mA Current sunk by ODIO pin 16
Supported diode current ID -2 2 mA Diode current at any device pin 16
Junction temperature (abs max) Tj -40 130 °C 16
Storage temperature Tstg -40 150 °C 16
ESD HBM V(ESD) -2000 2000 V Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins 16
ESD CDM V(ESD) -500 500 V Charged device model (CDM), per JEDEC specification JESD22-C101, all pins 16
Supply voltage VDD 1.62 3.6 V 16
Capacitor between VDD and VSS CVDD 10 uF Low-ESR, tolerance ±20% or better 16
Capacitor between VCORE and VSS CVCORE 470 nF Low-ESR, tolerance ±20% or better 16
Ambient temperature, S version TA -40 125 °C S version 16
Max junction temperature, S version TJ 130 °C S version 16
MCLK/CPUCLK/ULPCLK frequency, 1 flash wait state fMCLK 32 MHz 1 flash wait state 16
MCLK/CPUCLK/ULPCLK frequency, 0 flash wait states fMCLK 24 MHz 0 flash wait states 16
Junction-to-ambient thermal resistance RθJA 36.3 °C/W VQFN-32 (RHB) 17
Junction-to-case (top) thermal resistance RθJC(top) 28.5 °C/W VQFN-32 (RHB) 17
Junction-to-board thermal resistance RθJB 17.2 °C/W VQFN-32 (RHB) 17
Junction-to-top characterization parameter ΨJT 0.8 °C/W VQFN-32 (RHB) 17
Junction-to-board characterization parameter ΨJB 17.2 °C/W VQFN-32 (RHB) 17
Junction-to-case (bottom) thermal resistance RθJC(bot) 6.9 °C/W VQFN-32 (RHB) 17
SLEEP mode supply current, 32MHz IDDSLEEP 1070 1416 uA MCLK=SYSOSC, CPU is halted, 32MHz, 125°C, VDD=3.3V 18
SLEEP mode supply current, 4MHz IDDSLEEP 458 809 uA MCLK=SYSOSC, CPU is halted, 4MHz, 125°C, VDD=3.3V 18
STOP0 supply current IDDSTOP0 334 361 uA SYSOSC=32MHz, USE4MHZSTOP=0, DISABLESTOP=0, ULPCLK 4MHz, 125°C 18
STOP1 supply current IDDSTOP1 166 192 uA SYSOSC=4MHz, USE4MHZSTOP=1, DISABLESTOP=0, ULPCLK 4MHz, 125°C 18
STOP2 supply current IDDSTOP2 56 76 uA SYSOSC off, DISABLESTOP=1, ULPCLK=LFCLK 32kHz, 125°C 18
STANDBY0 supply current IDDSTBY0 11 25 uA STOPCLKSTBY=0, TIMG0 enabled, 32kHz, 125°C 18
STANDBY1 supply current IDDSTBY1 11 25 uA STOPCLKSTBY=1, TIMG0 enabled, 32kHz, 125°C 18
RUN mode supply current, 32MHz IDDRUN 2.4 mA MCLK=SYSOSC, CoreMark, execute from flash, 32MHz, 125°C, VDD=3.3V 18
Power-on reset voltage level, rising VPOR+ 0.95 1.3 1.51 V Rising (1) 19
Power-on reset voltage level, falling VPOR- 0.9 1.25 1.48 V Falling (1) 19
POR hysteresis VHYS, POR 30 45 60 mV (1) 19
BOR level 0 cold start rising VBOR0+, COLD 1.48 1.54 1.61 V Cold start, rising (1) 19
BOR level 0 rising VBOR0+ 1.55 1.59 1.62 V Rising (1) (2) 19
BOR level 0 falling VBOR0- 1.54 1.58 1.61 V Falling (1) (2) 19
BOR level 1 rising VBOR1+ 2.13 2.18 2.23 V Rising (1) (2) 19
BOR level 1 falling VBOR1- 2.1 2.15 2.19 V Falling (1) (2) 19
BOR level 2 rising VBOR2+ 2.72 2.77 2.82 V Rising (1) (2) 19
BOR level 2 falling VBOR2- 2.69 2.74 2.79 V Falling (1) (2) 19
BOR level 3 rising VBOR3+ 2.88 2.97 3.04 V Rising (1) (2) 19
BOR level 3 falling VBOR3- 2.85 2.94 3.01 V Falling (1) (2) 19
Program and erase supply voltage VDDPGM/ERASE 1.62 3.6 V 20
Flash word program time tPROG (WORD, 64) 50 275 µs 20
SYSOSC accuracy, FCL disabled, 32MHz fSYSOSC -2.6 1.8 % SETUSEFCL=0, SYSOSCCFG.FREQ=00, -40 ℃ ≤ Ta ≤ 125 ℃ 22
SYSOSC accuracy, FCL enabled, ideal ROSC -0.8 1.3 % SETUSEFCL=1, -40 ℃ ≤ Ta ≤ 125 ℃ 22
LFOSC accuracy -5 5 % -40 ℃ ≤ Ta ≤ 125 ℃ 22
High level input voltage, ODIO VIH 2 5.5 V ODIO, VDD≥2.7V 23
Low level input voltage, ODIO VIL -0.3 0.8 V ODIO, VDD≥2.7V 23
High-Z leakage current Ilkg -50 50 nA SDIO 23
Low level output voltage SDIO VOL 0.45 V SDIO, -40 °C ≤Tj≤130 °C 24
Low level output voltage ODIO VOL 0.45 V ODIO, VDD≥2.7V, IOL,max=8mA, -40 °C ≤Tj≤130 °C 24
ADC sampling frequency FS 1.68 Msps RES = 0x0 (12-bit mode), External Reference 25
ADC integral linearity error EI -2 2 LSB External reference 26
VREF output voltage 1.4V VREF 1.379 1.4 1.421 V BUFCONFIG = 1 27
VREF output voltage 2.5V VREF 2.462 2.5 2.538 V BUFCONFIG = 0 27

CAD (KiCad official)

  • Symbol: MSPM0L1304SRHBR
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: mspm0l1304srhbr-etched.step / mspm0l1304srhbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mspm0l1304srhbr.step / mspm0l1304srhbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (89 pp, sha256 d79bb920f524c429, retrieved 2026-10-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF