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MSPM0L1304SRGER

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Texas Instruments Microcontrollers (MCU/MPU/SOC), VQFN-24(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MSPM0L1304SRGER

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · VQFN-24(4x4)

MSPM0L1304SRGER from Texas Instruments, in a VQFN-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PA1 bidirectional 5-V tolerant open-drain GPIO with wake up from SHUTDOWN, muxed with UART1_RX, I2C0_SCL, TIMG1_C1 and the default BSL I2C clock (BSLSCL); needs a pullup to output high.
2 NRST input Active-low reset input that must be pulled high to VDD for the device to start.
3 VDD power_in Power supply, 1.62 V to 3.6 V recommended, with a 10 µF capacitor to VSS.
4 VSS power_in Ground supply.
5 PA2/ROSC bidirectional Standard-drive GPIO also used as ROSC, the external resistor (100 kΩ to VSS) pin that improves SYSOSC accuracy, with TIMG1_C1 and SPI0_CS0 functions.
6 PA3 bidirectional Standard-drive GPIO muxed with TIMG2_C0, SPI0_CS1, UART1_CTS and COMP0_OUT.
7 PA4 bidirectional Standard-drive GPIO muxed with TIMG2_C1, SPI0_POCI and UART1_RTS.
8 PA9 bidirectional Standard-drive GPIO muxed with UART0_RX, SPI0_PICO, UART1_CTS, TIMG2_C1 and CLK_OUT.
9 PA10 bidirectional High-speed GPIO muxed with UART1_TX, SPI0_POCI, I2C0_SDA, TIMG4_C0 and CLK_OUT.
10 PA11 bidirectional Standard-drive GPIO muxed with UART1_RX, SPI0_SCK, I2C0_SCL, TIMG4_C1 and COMP0_OUT.
11 PA15/A9 bidirectional Standard-drive GPIO with ADC0 analog input 9, muxed with UART1_RTS, I2C1_SCL, SPI0_CS2 and TIMG4_C1.
12 PA16/A8 bidirectional Standard-drive GPIO with ADC0 analog input 8 and OPA1 output, muxed with COMP0_OUT, I2C1_SDA, SPI0_POCI, TIMG0_C0 and FCC_IN.
13 PA17 bidirectional GPIO with wake up from SHUTDOWN and OPA1 inverting input (IN1-, also IN0- on this package), muxed with UART0_TX, I2C1_SCL, SPI0_SCK, TIMG4_C0 and SPI0_CS1.
14 PA18/A7 bidirectional GPIO with wake up from SHUTDOWN, ADC0 analog input 7, OPA1 non-inverting input 0 and GPAMP inverting input, muxed with UART0_RX, SPI0_PICO, I2C1_SDA, TIMG4_C1 and BSL_invoke.
15 PA19/SWDIO bidirectional High-speed GPIO used as serial wire debug data input/output (SWDIO), muxed with I2C1_SDA and SPI0_POCI.
16 PA20/A6/SWCLK bidirectional Standard-drive GPIO used as serial wire debug clock input (SWCLK), with ADC0 analog input 6 and comparator 0 non-inverting input 1, muxed with I2C1_SCL and TIMG4_C0.
17 PA21 bidirectional Standard-drive GPIO with ADC0 analog input 5 and VREF- external reference ground input, muxed with TIMG2_C0, UART0_CTS and UART0_TX.
18 PA22/A4 bidirectional Standard-drive GPIO with ADC0 analog input 4, GPAMP output and OPA0 output, muxed with UART0_RX (default BSL UART receive, BSLRX), TIMG2_C1, UART0_RTS, CLK_OUT and UART1_RX.
19 PA23 bidirectional Standard-drive GPIO with VREF+ external reference input and comparator 0 inverting input 1, muxed with UART0_TX (default BSL UART transmit, BSLTX), SPI0_CS3, TIMG0_C0, UART0_CTS and UART1_TX.
20 PA24 bidirectional Standard-drive GPIO with ADC0 analog input 3 and OPA0 inverting inputs, muxed with SPI0_CS2, TIMG0_C1 and UART0_RTS.
21 PA25 bidirectional Standard-drive GPIO with ADC0 analog input 2 and OPA0 non-inverting input 0, muxed with TIMG4_C1, UART0_TX and SPI0_PICO.
22 PA26 bidirectional Standard-drive GPIO with ADC0 analog input 1, GPAMP non-inverting input and comparator 0 non-inverting input 0, muxed with TIMG1_C0, UART0_RX and SPI0_POCI.
23 VCORE power_out Regulated core supply output that must only connect to a 470 nF capacitor to VSS, with no external voltage or load applied.
24 PA0 bidirectional 5-V tolerant open-drain GPIO with wake up from SHUTDOWN, muxed with UART1_TX, I2C0_SDA, TIMG1_C0, SPI0_CS1 and the default BSL I2C data (BSLSDA); needs a pullup to output high.
25 QFN Pad passive QFN exposed thermal pad; TI recommends connecting it to VSS.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-24(4x4)
Category Embedded Processors & Controllers
Pins 25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD -0.3 4.1 V At VDD pin, with respect to VSS 16
Input voltage, 5-V tolerant open-drain pins VI -0.3 5.5 V Applied to any 5-V tolerant open-drain pins 16
Input voltage, common tolerance pins VI -0.3 4.1 V Applied to any common tolerance pins; VDD + 0.3 (4.1 MAX) 16
Current into VDD pin (source) IVDD 80 mA -40°C ≤ Tj ≤ 130°C 16
Current into VDD pin (source) IVDD 100 mA -40°C ≤ Tj ≤ 85°C 16
Current out of VSS pin (sink) IVSS 80 mA -40°C ≤ Tj ≤ 130°C 16
Current out of VSS pin (sink) IVSS 100 mA -40°C ≤ Tj ≤ 85°C 16
Current for SDIO pin IIO 6 mA Current sunk or sourced by SDIO pin 16
Current for HSIO pin IIO 6 mA Current sunk or sourced by HSIO pin 16
Current for ODIO pin IIO 20 mA Current sunk by ODIO pin 16
Supported diode current ID -2 2 mA Diode current at any device pin 16
Junction temperature Tj -40 130 °C 16
Storage temperature Tstg -40 150 °C 16
ESD HBM V(ESD) -2000 2000 V Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins 16
ESD CDM V(ESD) -500 500 V Charged device model (CDM), per JEDEC specification JESD22-C101, all pins 16
Supply voltage VDD 1.62 3.6 V Functionality guaranteed down to VBOR0-(min) 16
Voltage on VCORE pin VCORE 1.35 V 16
Capacitor between VDD and VSS CVDD 10 uF Low-ESR, tolerance ±20% or better 16
Capacitor between VCORE and VSS CVCORE 470 nF Low-ESR, tolerance ±20% or better 16
Ambient temperature, S version TA -40 125 °C S version 16
Max junction temperature, S version TJ 130 °C S version 16
MCLK frequency with 1 flash wait state fMCLK 32 MHz MCLK, CPUCLK, ULPCLK with 1 flash wait state 16
MCLK frequency with 0 flash wait states fMCLK 24 MHz MCLK, CPUCLK, ULPCLK with 0 flash wait states 16
Junction-to-ambient thermal resistance RθJA 44.7 °C/W VQFN-24 (RGE) 17
Junction-to-case (top) thermal resistance RθJC(top) 38.1 °C/W VQFN-24 (RGE) 17
Junction-to-board thermal resistance RθJB 21.9 °C/W VQFN-24 (RGE) 17
Junction-to-top characterization parameter ΨJT 1.1 °C/W VQFN-24 (RGE) 17
Junction-to-board characterization parameter ΨJB 21.9 °C/W VQFN-24 (RGE) 17
Junction-to-case (bottom) thermal resistance RθJC(bot) 7.1 °C/W VQFN-24 (RGE) 17
RUN mode supply current, 32MHz IDDRUN 2.4 mA 125°C, VDD=3.3V, MCLK=SYSOSC, CoreMark, execute from flash, 32MHz 18
STOP mode supply current (STOP1) IDDSTOP1 151 171 uA 25°C, SYSOSC=4MHz, USE4MHZSTOP=1, DISABLESTOP=0, ULPCLK 4MHz 18
STOP mode supply current (STOP2) IDDSTOP2 44 54 uA 25°C, SYSOSC off, DISABLESTOP=1, ULPCLK=LFCLK 32kHz 18
STANDBY mode supply current IDDSTBY1 1 1.4 uA 25°C, STOPCLKSTBY=1, TIMG0 enabled, 32kHz 18
STANDBY mode supply current IDDSTBY1 11 25 uA 125°C, STOPCLKSTBY=1, TIMG0 enabled, 32kHz 18
SHUTDOWN mode supply current IDDSHDN 2020 nA 125°C, VDD 3.3V 18
Power-on reset voltage level, rising VPOR+ 0.95 1.3 1.51 V Rising 19
Power-on reset voltage level, falling VPOR- 0.9 1.25 1.48 V Falling 19
POR hysteresis VHYS, POR 30 45 60 mV 19
BOR level 0, cold start rising VBOR0+, COLD 1.48 1.54 1.61 V Cold start, rising 19
BOR level 0 rising VBOR0+ 1.55 1.59 1.62 V Rising 19
BOR level 0 falling VBOR0- 1.54 1.58 1.61 V Falling 19
BOR level 1 rising VBOR1+ 2.13 2.18 2.23 V Rising 19
BOR level 1 falling VBOR1- 2.1 2.15 2.19 V Falling 19
BOR level 2 rising VBOR2+ 2.72 2.77 2.82 V Rising 19
BOR level 2 falling VBOR2- 2.69 2.74 2.79 V Falling 19
BOR level 3 rising VBOR3+ 2.88 2.97 3.04 V Rising 19
BOR level 3 falling VBOR3- 2.85 2.94 3.01 V Falling 19
Program and erase supply voltage VDDPGM/ERASE 1.62 3.6 V 20
Flash word program time tPROG (WORD, 64) 50 275 µs 20
LFOSC accuracy -5 5 % -40 ℃ ≤ Ta ≤ 125 ℃ 22
SYSOSC accuracy, FCL disabled, 32MHz fSYSOSC -2.6 1.8 % SETUSEFCL=0, SYSOSCCFG.FREQ=00, -40 ℃ ≤ Ta ≤ 125 ℃ 22
SYSOSC accuracy, FCL enabled with ROSC, 125°C fSYSOSC -1.1 1.7 % SETUSEFCL=1, -40 ℃ ≤ Ta ≤ 125 ℃, ±0.1% ±25ppm ROSC 22
High level input voltage, all I/O except ODIO & Reset VIH 0.7 V VDD≥1.62V; min printed as 0.7*VDD, max VDD+0.3 23
Low level input voltage, all I/O except ODIO & Reset VIL -0.3 V VDD≥1.62V; max printed as 0.3*VDD 23
High-Z leakage current SDIO Ilkg -50 50 nA SDIO not muxed with analog inputs 23
Pull up resistance RPU 40 kΩ All I/O except ODIO 23
Input capacitance CI 5 pF 23
ADC INL EI -2 2 LSB External reference 26
VREF output voltage VREF 1.379 1.4 1.421 V BUFCONFIG = 1 27
VREF output voltage VREF 2.462 2.5 2.538 V BUFCONFIG = 0 27

CAD (KiCad official)

  • Symbol: MSPM0L1304SRGER
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • 3D model: VQFN-24(4x4) (KiCad packages3D, STEP)
  • 3D model files: mspm0l1304srger-etched.step / mspm0l1304srger-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mspm0l1304srger.step / mspm0l1304srger.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (89 pp, sha256 d79bb920f524c429, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF