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MSPM0L1227SRHBR

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Texas Instruments , VQFN-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MSPM0L1227SRHBR

Texas Instruments · IC · VQFN-32(5x5)

MSPM0L1227SRHBR from Texas Instruments, in a VQFN-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PA0 bidirectional 5V-tolerant open-drain GPIO (ODIO) with UART0_TX, I2C0_SDA, TIMA0_C0, FCC_IN, BSLSDA and WAKE functions; needs a pullup for output high.
2 PA1 bidirectional 5V-tolerant open-drain GPIO (ODIO) with UART0_RX, I2C0_SCL, TIMA0_C1, SPI0_CS3, BSLSCL and WAKE functions; needs a pullup for output high.
3 NRST input Active-low reset input that must be pulled high (47kΩ pullup with 10nF capacitor recommended) or the device will not start.
4 VBAT,VDD power_in Supply pin for 1.62V to 3.6V, with VBAT internally shorted to VDD on the 32-pin package; recommended 10µF and 0.1µF low-ESR decoupling to VSS.
5 VSS power_in Ground reference for the device.
6 PA2 bidirectional Standard-drive GPIO with SPI0_CS0, SPI1_CS0, TIMA0 and UART4_CTS functions, and ROSC analog function for the external 100kΩ SYSOSC resistor.
7 PA3 bidirectional LFSSIO GPIO with SPI0_CS1, I2C1_SDA, UART2_CTS, UART1_TX functions and LFXIN analog function for the 32kHz crystal.
8 PA4 bidirectional LFSSIO GPIO with SPI0_POCI, I2C1_SCL, UART1_RX, LFCLK_IN functions and LFXOUT analog function for the 32kHz crystal.
9 PA5 bidirectional Standard-drive GPIO with SPI0_PICO, I2C1_SDA, UART0_CTS, UART1_TX functions and HFXIN analog function for the HF crystal.
10 PA6 bidirectional Standard-drive GPIO with SPI0_SCK, I2C1_SCL, UART0_RTS, UART1_RX, HFCLK_IN functions and HFXOUT analog function for the HF crystal.
11 PA7 bidirectional LFSSIO GPIO with COMP0_OUT, CLK_OUT, SPI0_CS2, SPI0_POCI and TIMx functions, plus TIO0 tamper input.
12 PA8 bidirectional Standard-drive GPIO with UART1_TX, SPI0_CS0, I2C0_SDA, HFCLK_IN, UART0_RTS functions and LCD0 analog function.
13 PA9 bidirectional Standard-drive GPIO with UART1_RX, SPI0_PICO, I2C0_SCL, CLK_OUT, RTC_OUT functions and LCD1 analog function.
14 PA10 bidirectional High-drive GPIO with UART0_TX, SPI0_POCI, I2C0_SDA, CLK_OUT functions, BSLTX, WAKE input and LCD2 analog function.
15 PA11 bidirectional High-drive GPIO with UART0_RX, SPI0_SCK, I2C0_SCL, COMP0_OUT functions, BSLRX, WAKE input and LCD3 analog function.
16 PA12 bidirectional Standard-drive GPIO with UART3_CTS, SPI0_SCK, COMP0_OUT, FCC_IN functions and analog A_18.
17 PA13 bidirectional Standard-drive GPIO with UART3_RTS, SPI0_POCI, UART3_RX, RTC_OUT functions and analog A_17 and COMP0_IN2-.
18 PA14 bidirectional Standard-drive GPIO with UART0_CTS, SPI0_PICO, UART3_TX, CLK_OUT functions and analog A_16 and COMP0_IN2+.
19 PA15 bidirectional Standard-drive GPIO with UART0_RTS, I2C1_SCL, I2C2_SCL functions and analog A_15 and COMP0_IN3+.
20 PA16 bidirectional Standard-drive GPIO with COMP0_OUT, SPI1_POCI, I2C1_SDA, I2C2_SDA, FCC_IN functions and analog A_14.
21 PA17 bidirectional Standard-drive GPIO with wake, UART1_TX, SPI1_SCK, I2C1_SCL functions, WAKE and analog A_13 and COMP0_IN1-.
22 PA18 bidirectional Standard-drive GPIO with wake, UART1_RX, SPI1_PICO, I2C1_SDA functions, BSL_invoke, WAKE and analog A_12 and COMP0_IN1+.
23 PA19 bidirectional Standard-drive GPIO that carries the SWDIO serial wire debug data signal, with SPI1_POCI and I2C1_SDA functions.
24 PA20 bidirectional Standard-drive GPIO that carries the SWCLK serial wire debug clock input, with SPI1_SCK and I2C1_SCL functions.
25 PA21 bidirectional Standard-drive GPIO with UART2_TX, SPI0_CS3, UART1_CTS functions and analog A_8 and VREF- external reference input.
26 PA22 bidirectional Standard-drive GPIO with UART2_RX, SPI0_CS2, UART1_RTS, CLK_OUT, I2C0_SCL functions and analog A_7.
27 PA23 bidirectional Standard-drive GPIO with UART2_TX, SPI0_CS3, I2C2_SCL functions and analog VREF+ external reference input.
28 PA24 bidirectional Standard-drive GPIO with UART2_RX, SPI0_CS2, I2C2_SDA functions and analog A_3.
29 PA25 bidirectional Standard-drive GPIO with UART3_RX, SPI1_CS3, COMP0_OUT functions and analog A_2.
30 PA26 bidirectional Standard-drive GPIO with UART3_TX, SPI1_CS0, UART2_RTS functions and analog A_1 and COMP0_IN0+.
31 PA27 bidirectional Standard-drive GPIO with UART3_RX, SPI1_CS1, CLK_OUT, RTC_OUT, COMP0_OUT functions and analog A_0 and COMP0_IN0-.
32 VCORE power_out Internal core regulator output that must only connect to a 470nF (0.47µF) capacitor to VSS, with no external voltage or load applied.
33 Thermal Pad passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-32(5x5)
Category
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD -0.3 4.1 V At VDD pin 42
Battery backup supply VBAT -0.3 4.1 V At VBAT pin, with respect to VSS 42
Input voltage, 5-V tolerant open-drain pins VI -0.3 5.5 V Applied to any 5-V tolerant open-drain pins 42
Input voltage, common pins VI -0.3 V Applied to any common tolerance pins; max printed as VDD + 0.3 (4.1 MAX) 42
Current of VDD pin IVDD 80 mA Current into VDD pin (source), VDD >= 2.7V 42
Current of VBAT pin IVBAT 20 mA Current into VBAT pin (source), VBAT >= 2.7V 42
Current of VSS pin IVSS 80 mA Current out of VSS pin (sink), VDD, VBAT>=2.7V 42
Current of SD IO pin IIO 6 mA Current sunk or sourced by SD IO pin, VDD>=2.7V 42
Current of HS IO pin IIO 6 mA Current sunk or sourced by HS IO pin, VDD >=2.7V 42
Current of HD IO pin IIO 20 mA Current sunk or sourced by HD IO pin 42
Current of OD IO pin IIO 20 mA Current sunk by OD IO pin 42
Supported diode current, LCD pin ID -2 0.4 mA Diode current on pin supporting LCD function 42
Supported diode current, non-LCD pin ID -2 0.05 mA Diode current on pin not supporting LCD function (excluding Open Drain IO) 42
Junction temperature TJ -40 130 °C 42
Storage temperature Tstg -40 150 °C 42
ESD HBM V(ESD) -2000 2000 V Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins 42
ESD CDM V(ESD) -500 500 V Charged device model (CDM), per JEDEC specification JESD22-C101, all pins 42
Supply voltage VDD 1.62 3.6 V 42
VBAT supply voltage VBAT 1.62 3.6 V At VBAT pin, with respect to VSS 42
Voltage on VCORE pin VCORE 1.35 V Voltage on VCORE pin 42
VDD capacitor CVDD 10 uF Capacitor connected between VDD and VSS 42
VBAT capacitor CVBAT 1 µF Capacitor connected between VBAT and VSS 42
VCORE capacitor CVCORE 470 nF Capacitor connected between VCORE and VSS 42
Ambient temperature TA -40 125 °C 42
Max junction temperature TJ 130 °C 42
MCLK frequency, 1 flash wait state fMCLK 32 MHz MCLK, CPUCLK, ULPCLK frequency with 1 flash wait state 43
MCLK frequency, 0 flash wait states fMCLK 24 MHz MCLK, CPUCLK, ULPCLK frequency with 0 flash wait states 43
Junction-to-ambient thermal resistance RθJA 32.1 °C/W VQFN-32 (RHB) 43
Junction-to-case (top) thermal resistance RθJC(top) 23.6 °C/W VQFN-32 (RHB) 43
Junction-to-board thermal resistance RθJB 13 °C/W VQFN-32 (RHB) 43
Junction-to-top characterization parameter ΨJT 0.3 °C/W VQFN-32 (RHB) 43
Junction-to-board characterization parameter ΨJB 13 °C/W VQFN-32 (RHB) 43
Junction-to-case (bottom) thermal resistance RθJC(bot) 3.3 °C/W VQFN-32 (RHB) 43
Power-on reset level, rising VPOR+ 0.95 1.3 1.56 V Rising 47
Power-on reset level, falling VPOR- 0.9 1.25 1.53 V Falling 47
POR hysteresis VHYS, POR 25 45 70 mV 47
BOR0 level, cold start rising VBOR0+, COLD 1.48 1.54 1.61 V Cold start, rising 47
BOR0 level, rising VBOR0+ 1.56 1.59 1.62 V Rising 47
BOR0 level, falling VBOR0- 1.55 1.58 1.61 V Falling 47
BOR1 level, rising VBOR1+ 2.13 2.17 2.21 V Rising 47
BOR2 level, rising VBOR2+ 2.73 2.77 2.82 V Rising 47
BOR3 level, rising VBOR3+ 2.88 2.96 3.04 V Rising 47
Internal switch resistance between VBAT and VDD Rswitch 0.9 1.4 2.7 kΩ 48
Flash program and erase supply voltage VDDPGM/ERASE 1.62 3.6 V 48
Flash word program time tPROG (WORD, 64) 50 275 µs 48
Sector erase time tERASE (SEC) 20 200 ms <10k erase/program cycles 48
SYSOSC accuracy, FCL on, 25 °C fSYSOSC -0.41 0.58 % SETUSEFCL=1, Ta = 25 ℃ 50
SYSOSC accuracy, FCL on, internal ROSC fSYSOSC -2 1.4 % SETUSEFCL=1 -40 ℃ ≤ Ta ≤ 125 ℃ 50
LFOSC accuracy -5 5 % -40 ℃ ≤ Ta ≤ 125 ℃ 50
High level input voltage ODIO VIH 2 5.5 V ODIO, VDD≥2.7V 52
Low level input voltage ODIO VIL -0.3 0.8 V ODIO, VDD≥2.7V 52
High-Z leakage current non-LCD pins Ilkg 50 nA SDIO 52
Low level output voltage SDIO VOL 0.4 V SDIO, VDD≥2.7V, /IIO/,max=6mA; VDD≥1.71V, /IIO/,max=2mA; Tj≤85 °C 53
ADC analog input range Vin(ADC) 0 V Applies to all ADC analog input pins; max printed VDD 54
ADC operating supply current I(ADC) 460 600 μA FS = 1.68MSPS, Internal reference OFF, VR+ = VDD 54
ADC INL Ej -2 2 LSB External reference 55
ADC DNL Ek -1 1 LSB External reference 55
ADC offset error EO -3.5 3.5 mV External reference 55
ADC gain error EG -4 4 LSB External reference 55
VREF output voltage 2.5V VREF 2.46 2.5 2.54 V BUFCONFIG = 0 58
VREF output voltage 1.4V VREF 1.38 1.4 1.42 V BUFCONFIG = 1 58
VREF temperature coefficient TCVREF 75 ppm/°C BUFCONFIG = {0, 1} 57
Comparator input offset voltage Voffset -20 20 mV 58
Temperature sensor temperature coefficient TSc -1.9 -1.8 -1.7 mV/℃ -40℃ ≤ Tj ≤ 130℃ 55

CAD (KiCad official)

  • Symbol: MSPM0L1227SRHBR
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: VQFN-32(5x5) (KiCad packages3D, STEP)
  • 3D model files: mspm0l1227srhbr-etched.step / mspm0l1227srhbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mspm0l1227srhbr.step / mspm0l1227srhbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (134 pp, sha256 ec3945476714eea7, retrieved 2026-10-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF