component
MSPM0L1106TRHBR
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), VQFN-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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MSPM0L1106TRHBR
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · VQFN-32(5x5)
MSPM0L1106TRHBR from Texas Instruments, in a VQFN-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PA0 | bidirectional | General-purpose digital I/O with wake up from SHUTDOWN on a 5-V tolerant open-drain (ODIO) pin that needs an external pullup to drive high, with UART1_TX, I2C0_SDA, TIMG1_C0 and SPI0_CS1 alternates and default BSL I2C_SDA. |
| 2 | PA1 | bidirectional | General-purpose digital I/O with wake up from SHUTDOWN on a 5-V tolerant open-drain (ODIO) pin that needs an external pullup to drive high, with UART1_RX, I2C0_SCL and TIMG1_C1 alternates and default BSL I2C_SCL. |
| 3 | NRST | input | Active-low reset input that must be pulled high to VDD, otherwise the device cannot start (a 47-kΩ pullup is recommended). |
| 4 | VDD | power_in | Power supply input with a recommended range of 1.62 V to 3.6 V and an absolute maximum of 4.1 V, decoupled with a 10-µF capacitor to VSS. |
| 5 | VSS | power_in | Ground supply; the QFN exposed thermal pad is recommended to be connected to VSS. |
| 6 | PA2 | bidirectional | General-purpose digital I/O that doubles as the ROSC pin, which needs an external 100-kΩ 0.1% resistor to VSS only when the SYSOSC frequency correction loop is used. |
| 7 | PA3 | bidirectional | General-purpose digital I/O (standard drive) with TIMG2_C0, SPI0_CS1 and UART1_CTS alternate functions. |
| 8 | PA4 | bidirectional | General-purpose digital I/O (standard drive) with TIMG2_C1, SPI0_POCI and UART1_RTS alternate functions. |
| 9 | PA5 | bidirectional | High-speed general-purpose digital I/O with TIMG0_C0, SPI0_PICO and FCC_IN alternate functions. |
| 10 | PA6 | bidirectional | General-purpose digital I/O (standard drive) with TIMG0_C1 and SPI0_SCK alternate functions. |
| 11 | PA7 | bidirectional | General-purpose digital I/O (standard drive) with CLK_OUT and TIMG1_C0 alternate functions. |
| 12 | PA8 | bidirectional | General-purpose digital I/O (standard drive) with UART0_TX, SPI0_CS0, UART1_RTS and TIMG2_C0 alternate functions. |
| 13 | PA9 | bidirectional | General-purpose digital I/O (standard drive) with UART0_RX, SPI0_PICO, UART1_CTS and TIMG2_C1 alternate functions. |
| 14 | PA10 | bidirectional | High-speed general-purpose digital I/O with UART1_TX, SPI0_POCI, I2C0_SDA and TIMG4_C0 alternate functions. |
| 15 | PA11 | bidirectional | General-purpose digital I/O (standard drive) with UART1_RX, SPI0_SCK, I2C0_SCL and TIMG4_C1 alternate functions. |
| 16 | PA12 | bidirectional | General-purpose digital I/O (standard drive) with UART0_CTS, TIMG0_C0 and FCC_IN alternate functions. |
| 17 | PA13 | bidirectional | General-purpose digital I/O (standard drive) with UART0_RTS, TIMG0_C1 and UART1_RX alternate functions. |
| 18 | PA14 | bidirectional | General-purpose digital I/O (standard drive) with UART1_CTS, CLK_OUT, UART1_TX and TIMG1_C0 alternate functions. |
| 19 | PA15 | bidirectional | General-purpose digital I/O (standard drive) that is also ADC0 analog input A9, with UART1_RTS, SPI0_CS2 and TIMG4_C1 alternate functions. |
| 20 | PA16 | bidirectional | General-purpose digital I/O (standard drive) that is also ADC0 analog input A8, with SPI0_POCI, TIMG0_C0 and FCC_IN alternate functions. |
| 21 | PA17 | bidirectional | General-purpose digital I/O with wake up from SHUTDOWN, with UART0_TX, SPI0_SCK, TIMG4_C0 and SPI0_CS1 alternate functions. |
| 22 | PA18 | bidirectional | General-purpose digital I/O with wake up from SHUTDOWN that is also ADC0 analog input A7 and GPAMP inverting input GPAMP_IN-, and is the active-high BSL_invoke pin used to start the bootloader during boot. |
| 23 | PA19 | bidirectional | High-speed general-purpose digital I/O that is also the bidirectional serial wire debug data pin SWDIO, with SPI0_POCI as an alternate function. |
| 24 | PA20 | bidirectional | General-purpose digital I/O that is also ADC0 analog input A6 and the serial wire debug input clock SWCLK, with TIMG4_C0 as an alternate function. |
| 25 | PA21 | bidirectional | General-purpose digital I/O that is also ADC0 analog input A5 and the external voltage reference ground input VREF-, with TIMG2_C0, UART0_CTS and UART0_TX alternate functions. |
| 26 | PA22 | bidirectional | General-purpose digital I/O that is also ADC0 analog input A4 and GPAMP_OUT, with default BSL UART_RX and UART0_RX, TIMG2_C1, UART0_RTS, CLK_OUT and UART1_RX alternate functions. |
| 27 | PA23 | bidirectional | General-purpose digital I/O that is also the external voltage reference positive input VREF+, with default BSL UART_TX and UART0_TX, SPI0_CS3, TIMG0_C0, UART0_CTS and UART1_TX alternate functions. |
| 28 | PA24 | bidirectional | General-purpose digital I/O that is also ADC0 analog input A3, with SPI0_CS2, TIMG0_C1 and UART0_RTS alternate functions. |
| 29 | PA25 | bidirectional | General-purpose digital I/O that is also ADC0 analog input A2, with TIMG4_C1, UART0_TX and SPI0_PICO alternate functions. |
| 30 | PA26 | bidirectional | General-purpose digital I/O that is also ADC0 analog input A1 and the GPAMP non-inverting input GPAMP_IN+, with TIMG1_C0, UART0_RX and SPI0_POCI alternate functions. |
| 31 | PA27 | bidirectional | General-purpose digital I/O that is also ADC0 analog input A0, with TIMG1_C1 and SPI0_CS3 alternate functions. |
| 32 | VCORE | power_out | Regulated core power output at 1.35 V that must only be connected to a 0.47-µF capacitor to VSS and must not be supplied or loaded externally. |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-32(5x5) |
| Category | Embedded Processors & Controllers |
| Pins | 33 |
CAD (KiCad official)
- Symbol:
MSPM0L1106TRHBR - Footprint:
Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm - 3D model: VQFN-32(5x5) (KiCad packages3D, STEP)
- 3D model files:
mspm0l1106trhbr-etched.step/mspm0l1106trhbr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mspm0l1106trhbr.step/mspm0l1106trhbr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (74 pp, sha256
99a46f09107d8a08, retrieved 2026-10-10, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# MSPM0L1106TRHBR
**Texas Instruments** · Microcontrollers (MCU/MPU/SOC) · VQFN-32(5x5)
MSPM0L1106TRHBR from Texas Instruments, in a VQFN-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PA0 | bidirectional | General-purpose digital I/O with wake up from SHUTDOWN on a 5-V tolerant open-drain (ODIO) pin that needs an external pullup to drive high, with UART1_TX, I2C0_SDA, TIMG1_C0 and SPI0_CS1 alternates and default BSL I2C_SDA. |
| 2 | PA1 | bidirectional | General-purpose digital I/O with wake up from SHUTDOWN on a 5-V tolerant open-drain (ODIO) pin that needs an external pullup to drive high, with UART1_RX, I2C0_SCL and TIMG1_C1 alternates and default BSL I2C_SCL. |
| 3 | NRST | input | Active-low reset input that must be pulled high to VDD, otherwise the device cannot start (a 47-kΩ pullup is recommended). |
| 4 | VDD | power_in | Power supply input with a recommended range of 1.62 V to 3.6 V and an absolute maximum of 4.1 V, decoupled with a 10-µF capacitor to VSS. |
| 5 | VSS | power_in | Ground supply; the QFN exposed thermal pad is recommended to be connected to VSS. |
| 6 | PA2 | bidirectional | General-purpose digital I/O that doubles as the ROSC pin, which needs an external 100-kΩ 0.1% resistor to VSS only when the SYSOSC frequency correction loop is used. |
| 7 | PA3 | bidirectional | General-purpose digital I/O (standard drive) with TIMG2_C0, SPI0_CS1 and UART1_CTS alternate functions. |
| 8 | PA4 | bidirectional | General-purpose digital I/O (standard drive) with TIMG2_C1, SPI0_POCI and UART1_RTS alternate functions. |
| 9 | PA5 | bidirectional | High-speed general-purpose digital I/O with TIMG0_C0, SPI0_PICO and FCC_IN alternate functions. |
| 10 | PA6 | bidirectional | General-purpose digital I/O (standard drive) with TIMG0_C1 and SPI0_SCK alternate functions. |
| 11 | PA7 | bidirectional | General-purpose digital I/O (standard drive) with CLK_OUT and TIMG1_C0 alternate functions. |
| 12 | PA8 | bidirectional | General-purpose digital I/O (standard drive) with UART0_TX, SPI0_CS0, UART1_RTS and TIMG2_C0 alternate functions. |
| 13 | PA9 | bidirectional | General-purpose digital I/O (standard drive) with UART0_RX, SPI0_PICO, UART1_CTS and TIMG2_C1 alternate functions. |
| 14 | PA10 | bidirectional | High-speed general-purpose digital I/O with UART1_TX, SPI0_POCI, I2C0_SDA and TIMG4_C0 alternate functions. |
| 15 | PA11 | bidirectional | General-purpose digital I/O (standard drive) with UART1_RX, SPI0_SCK, I2C0_SCL and TIMG4_C1 alternate functions. |
| 16 | PA12 | bidirectional | General-purpose digital I/O (standard drive) with UART0_CTS, TIMG0_C0 and FCC_IN alternate functions. |
| 17 | PA13 | bidirectional | General-purpose digital I/O (standard drive) with UART0_RTS, TIMG0_C1 and UART1_RX alternate functions. |
| 18 | PA14 | bidirectional | General-purpose digital I/O (standard drive) with UART1_CTS, CLK_OUT, UART1_TX and TIMG1_C0 alternate functions. |
| 19 | PA15 | bidirectional | General-purpose digital I/O (standard drive) that is also ADC0 analog input A9, with UART1_RTS, SPI0_CS2 and TIMG4_C1 alternate functions. |
| 20 | PA16 | bidirectional | General-purpose digital I/O (standard drive) that is also ADC0 analog input A8, with SPI0_POCI, TIMG0_C0 and FCC_IN alternate functions. |
| 21 | PA17 | bidirectional | General-purpose digital I/O with wake up from SHUTDOWN, with UART0_TX, SPI0_SCK, TIMG4_C0 and SPI0_CS1 alternate functions. |
| 22 | PA18 | bidirectional | General-purpose digital I/O with wake up from SHUTDOWN that is also ADC0 analog input A7 and GPAMP inverting input GPAMP_IN-, and is the active-high BSL_invoke pin used to start the bootloader during boot. |
| 23 | PA19 | bidirectional | High-speed general-purpose digital I/O that is also the bidirectional serial wire debug data pin SWDIO, with SPI0_POCI as an alternate function. |
| 24 | PA20 | bidirectional | General-purpose digital I/O that is also ADC0 analog input A6 and the serial wire debug input clock SWCLK, with TIMG4_C0 as an alternate function. |
| 25 | PA21 | bidirectional | General-purpose digital I/O that is also ADC0 analog input A5 and the external voltage reference ground input VREF-, with TIMG2_C0, UART0_CTS and UART0_TX alternate functions. |
| 26 | PA22 | bidirectional | General-purpose digital I/O that is also ADC0 analog input A4 and GPAMP_OUT, with default BSL UART_RX and UART0_RX, TIMG2_C1, UART0_RTS, CLK_OUT and UART1_RX alternate functions. |
| 27 | PA23 | bidirectional | General-purpose digital I/O that is also the external voltage reference positive input VREF+, with default BSL UART_TX and UART0_TX, SPI0_CS3, TIMG0_C0, UART0_CTS and UART1_TX alternate functions. |
| 28 | PA24 | bidirectional | General-purpose digital I/O that is also ADC0 analog input A3, with SPI0_CS2, TIMG0_C1 and UART0_RTS alternate functions. |
| 29 | PA25 | bidirectional | General-purpose digital I/O that is also ADC0 analog input A2, with TIMG4_C1, UART0_TX and SPI0_PICO alternate functions. |
| 30 | PA26 | bidirectional | General-purpose digital I/O that is also ADC0 analog input A1 and the GPAMP non-inverting input GPAMP_IN+, with TIMG1_C0, UART0_RX and SPI0_POCI alternate functions. |
| 31 | PA27 | bidirectional | General-purpose digital I/O that is also ADC0 analog input A0, with TIMG1_C1 and SPI0_CS3 alternate functions. |
| 32 | VCORE | power_out | Regulated core power output at 1.35 V that must only be connected to a 0.47-µF capacitor to VSS and must not be supplied or loaded externally. |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-32(5x5) |
| Category | Embedded Processors & Controllers |
| Pins | 33 |
## CAD (KiCad official)
- Symbol: `MSPM0L1106TRHBR`
- Footprint: `Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm`
- 3D model: VQFN-32(5x5) (KiCad packages3D, STEP)
- 3D model files: `mspm0l1106trhbr-etched.step` / `mspm0l1106trhbr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mspm0l1106trhbr.step` / `mspm0l1106trhbr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603071634538713088) (74 pp, sha256 `99a46f09107d8a08`, retrieved 2026-10-10, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/mspm0l1106trhbr-datasheet.pdf)