MSPM0G3507SRGZR

Texas Instruments · IC · VQFN-48-EP(7x7)

MSPM0G3507SRGZR from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	PA0	bidirectional	5V-tolerant open-drain GPIO (wake from SHUTDOWN) muxed with UART0_TX, I2C0_SDA, TIMA0_C0, TIMG8_C1 and FCC_IN, and the default BSL I2C data pin.
2	PA1	bidirectional	5V-tolerant open-drain GPIO (wake from SHUTDOWN) muxed with UART0_RX, I2C0_SCL, TIMA0_C1 and TIMG8 signals, and the default BSL I2C clock pin.
3	PA28	bidirectional	High-drive GPIO (wake from SHUTDOWN) muxed with UART0_TX, I2C0_SDA, TIMA0_C3, TIMA_FAL0, TIMG7_C0 and TIMA1_C0.
4	NRST	input	Active-low reset input that must be pulled high to VDD for the device to start.
5	PA31	bidirectional	High-drive GPIO (wake from SHUTDOWN) muxed with UART0_RX, I2C0_SCL, TIMA0_C3N, TIMG12_C1, CLK_OUT, TIMG7_C1 and TIMA1_C1.
6	VDD	power_in	Power supply, 1.62 V to 3.6 V, with 10 µF recommended between VDD and VSS.
7	VSS	power_in	Ground supply.
8	PA2	bidirectional	Standard GPIO that is also the ROSC pin for the external 100 kΩ SYSOSC correction resistor to VSS; muxed with TIMG8_C1, SPI0_CS0, TIMG7_C1 and SPI1_CS0.
9	PA3	bidirectional	Standard GPIO that is also LFXIN, the low-frequency crystal oscillator input; muxed with TIMG8_C0, SPI0_CS1, UART2_CTS, TIMA0_C2, COMP1_OUT, TIMG7_C0, TIMA0_C1 and I2C1_SDA.
10	PA4	bidirectional	Standard GPIO that is also LFXOUT, the low-frequency crystal output, and LFCLK_IN; muxed with SPI0_POCI, UART2_RTS, TIMA0_C3 and I2C1_SCL.
11	PA5	bidirectional	Standard GPIO that is also HFXIN, the high-frequency crystal oscillator input; muxed with TIMG8_C0, SPI0_PICO, TIMA_FAL1, TIMG0_C0, TIMG6_C0 and FCC_IN.
12	PA6	bidirectional	Standard GPIO that is also HFXOUT, the high-frequency crystal output, and HFCLK_IN; muxed with TIMG8_C1, SPI0_SCK, TIMA_FAL0, TIMG0_C1, TIMG6_C1 and TIMA0_C2N.
13	PA7	bidirectional	Standard GPIO muxed with COMP0_OUT, CLK_OUT, TIMG8_C0, TIMA0_C2, TIMG8_IDX, TIMG7_C1 and TIMA0_C1.
14	PB2	bidirectional	Standard GPIO muxed with UART3_TX, UART2_CTS, I2C1_SCL, TIMA0_C3, UART1_CTS, TIMG6_C0 and TIMA1_C0.
15	PB3	bidirectional	Standard GPIO muxed with UART3_RX, UART2_RTS, I2C1_SDA, TIMA0_C3N, UART1_RTS, TIMG6_C1 and TIMA1_C1.
16	PA8	bidirectional	Standard GPIO muxed with UART1_TX, SPI0_CS0, UART0_RTS, TIMA0_C0 and TIMA1_C0N.
17	PA9	bidirectional	High-speed GPIO muxed with UART1_RX, SPI0_PICO, UART0_CTS, TIMA0_C1, RTC_OUT, CLK_OUT and TIMA timer outputs.
18	PA10	bidirectional	High-drive GPIO (wake from SHUTDOWN) muxed with UART0_TX, SPI0_POCI, I2C0_SDA, I2C1_SDA and CLK_OUT, and the default BSL UART transmit pin.
19	PA11	bidirectional	High-drive GPIO (wake from SHUTDOWN) muxed with UART0_RX, SPI0_SCK, I2C0_SCL, COMP0_OUT and I2C1_SCL, and the default BSL UART receive pin.
20	PB6	bidirectional	Standard GPIO muxed with UART1_TX, SPI1_CS0, SPI0_CS1, TIMG8_C0, UART2_CTS, TIMG6_C0 and TIMA1_C0N.
21	PB7	bidirectional	Standard GPIO muxed with UART1_RX, SPI1_POCI, SPI0_CS2, TIMG8_C1, UART2_RTS, TIMG6_C1 and TIMA1_C1N.
22	PB8	bidirectional	Standard GPIO muxed with UART1_CTS, SPI1_PICO, TIMA0_C0 and COMP1_OUT.
23	PB9	bidirectional	Standard GPIO muxed with UART1_RTS, SPI1_SCK, TIMA0_C1 and TIMA0_C0N.
24	PB14	bidirectional	Standard GPIO muxed with SPI1_CS3, SPI1_POCI, SPI0_CS3, TIMG12_C1, TIMG8_IDX and TIMA0_C0.
25	PB15	bidirectional	Standard GPIO muxed with UART2_TX, SPI1_PICO, UART3_CTS, TIMG8_C0 and TIMG7_C0.
26	PB16	bidirectional	Standard GPIO muxed with UART2_RX, SPI1_SCK, UART3_RTS, TIMG8_C1 and TIMG7_C1.
27	PA12	bidirectional	High-speed GPIO muxed with UART3_CTS, SPI0_SCK, TIMG0_C0, CAN_TX, TIMA0_C3 and FCC_IN.
28	PA13	bidirectional	High-speed GPIO with COMP0_IN2- analog input, muxed with UART3_RTS, SPI0_POCI, UART3_RX, TIMG0_C1, CAN_RX and TIMA0_C3N.
29	PA14	bidirectional	High-speed GPIO with COMP0_IN2+ and ADC input A0_12, muxed with UART0_CTS, SPI0_PICO, UART3_TX, TIMG12_C0 and CLK_OUT.
30	PA15	bidirectional	Standard GPIO with ADC input A1_0, DAC_OUT, OPA0_IN2+, OPA1_IN2+, COMP0_IN3+ and COMP1_IN3+, muxed with UART0_RTS, SPI1_CS2, I2C1_SCL and timer signals.
31	PA16	bidirectional	Standard GPIO with ADC input A1_1 and OPA1_OUT, muxed with COMP2_OUT, SPI1_POCI, I2C1_SDA, TIMA1_C1 and FCC_IN.
32	PA17	bidirectional	Standard GPIO with wake from SHUTDOWN, ADC input A1_2, OPA1_IN1- and COMP0_IN1-, muxed with UART1_TX, SPI1_SCK, I2C1_SCL and timer signals.
33	PA18	bidirectional	Standard GPIO with wake from SHUTDOWN, ADC input A1_3, OPA1_IN1+, COMP0_IN1+ and GPAMP_IN-, muxed with UART1_RX, SPI1_PICO and I2C1_SDA, and the default BSL_invoke pin.
34	PA19	bidirectional	High-speed GPIO used as SWDIO, the serial wire debug data input/output.
35	PA20	bidirectional	Standard GPIO used as SWCLK, the serial wire debug clock input.
36	PB17	bidirectional	Standard GPIO with ADC input A1_4 and COMP1_IN2-, muxed with UART2_TX, SPI0_PICO, SPI1_CS1, TIMA1_C0 and TIMA0_C2.
37	PB18	bidirectional	Standard GPIO with ADC input A1_5 and COMP1_IN2+, muxed with UART2_RX, SPI0_SCK, SPI1_CS2, TIMA1_C1 and TIMA0_C2N.
38	PB19	bidirectional	Standard GPIO with ADC input A1_6, COMP2_IN1+ and OPA1_IN0+, muxed with COMP2_OUT, SPI0_POCI, TIMG8_C1, UART0_CTS and TIMG7_C1.
39	PA21	bidirectional	Standard GPIO with ADC input A1_7, COMP2_IN1- and VREF- (voltage reference ground); no injection current allowed since it has an internal test connection.
40	PA22	bidirectional	Standard GPIO with ADC input A0_7, GPAMP_OUT and OPA0_OUT, muxed with UART2_RX, TIMG8_C1, UART1_RTS, TIMA0_C1 and CLK_OUT.
41	PB20	bidirectional	Standard GPIO with ADC input A0_6 and OPA1_IN0-, muxed with SPI0_CS2, SPI1_CS0, TIMA0_C2, TIMG12_C0 and TIMA_FAL1.
42	PB24	bidirectional	Standard GPIO with ADC input A0_5 and COMP1_IN1+, muxed with SPI0_CS3, SPI0_CS1, TIMA0_C3, TIMG12_C1 and TIMA0_C1N.
43	PA23	bidirectional	Standard GPIO with COMP1_IN1- and VREF+ (external reference input or internal reference output), muxed with UART2_TX, SPI0_CS3, TIMA0_C3 and TIMG0_C0.
44	PA24	bidirectional	Standard GPIO with ADC input A0_3 and OPA0_IN1-, muxed with UART2_RX, SPI0_CS2, TIMA0_C3N, TIMG0_C1 and UART3_RTS.
45	PA25	bidirectional	Standard GPIO with ADC input A0_2 and OPA0_IN1+, muxed with UART3_RX, SPI1_CS3, TIMG12_C1, TIMA0_C3 and TIMA0_C1N.
46	PA26	bidirectional	Standard GPIO with ADC input A0_1, COMP0_IN0+, OPA0_IN0+ and GPAMP_IN+, muxed with UART3_TX, SPI1_CS0, TIMG8_C0, TIMA_FAL0 and CAN_TX.
47	PA27	bidirectional	Standard GPIO with ADC input A0_0, COMP0_IN0- and OPA0_IN0-, muxed with RTC_OUT, SPI1_CS1, TIMG8_C1, TIMA_FAL2 and CAN_RX.
48	VCORE	power_in	Regulated core supply output that must only connect to a 470 nF (0.47 µF) capacitor to VSS, with no external supply or load.
49	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-48-EP(7x7)
Category
Pins	49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage	VDD	1.62		3.6	V		25
Ambient temperature, S version	TA	-40		125	°C		25
Max junction temperature, S version	TJ			130	°C		25
Capacitor between VDD and VSS	CVDD	10			uF		25
Capacitor between VCORE and VSS	CVCORE	470			nF		25
Supply voltage at VDD pin	VDD	-0.3		4.1	V	At VDD pin	25
Input voltage, 5-V tolerant open-drain pins	VI	-0.3		5.5	V	Applied to any 5-V tolerant open-drain pins	25
Input voltage, common pins	VI	-0.3		4.1	V	Applied to any common tolerance pins; VDD + 0.3 (4.1 MAX)	25
Diode current at any pin	ID	-2		2	mA	Diode current at any device pin	25
Storage temperature	Tstg	-40		150	°C		25
Junction temperature	TJ	-40		130	°C		25
ESD HBM	V(ESD)	-2000		2000	V	HBM, all pins	25
ESD CDM	V(ESD)	-500		500	V	CDM, all pins	25
Junction-to-ambient thermal resistance VQFN-48 (RGZ)	RθJA		30.1		°C/W	VQFN-48 (RGZ)	26
Junction-to-case (top) thermal resistance	RθJC(top)		20.7		°C/W	VQFN-48 (RGZ)	26
Junction-to-board thermal resistance	RθJB		12.5		°C/W	VQFN-48 (RGZ)	26
Junction-to-case (bottom) thermal resistance	RθJC(bot)		4.2		°C/W	VQFN-48 (RGZ)	26
Power-on reset voltage, rising	VPOR+	0.95	1.3	1.59	V	Rising	29
Power-on reset voltage, falling	VPOR-	0.9	1.25	1.54	V	Falling	29
SHUTDOWN supply current	IDDSHDN		40	80	nA	VDD=3.3V, -40°C	29
RUN mode supply current	IDDRUN		8		mA	VDD=3.3V, 80MHz, MCLK=SYSPLL, CoreMark, flash, -40°C	28
Brown-out reset level 0 rising	VBOR0+	1.56	1.59	1.62	V	Rising	30
Brown-out reset level 0 falling	VBOR0-	1.55	1.58	1.61	V	Falling	30
Program and erase supply voltage	VDDPGM/ERASE	1.62		3.6	V		30
LFOSC accuracy	LFOSC accuracy	-3		3	%	-40 ℃ ≤ Ta ≤ 85 ℃	33
LFOSC accuracy	LFOSC accuracy	-5		5	%	-40 ℃ ≤ Ta ≤ 125 ℃	33
SYSOSC accuracy FCL disabled 32MHz	fSYSOSC	-2.6		1.8	%	SETUSEFCL=0, SYSOSCCFG.FREQ=00, -40 ℃ ≤ Ta ≤ 125 ℃	33
VREF output voltage	VREF	2.46	2.5	2.54	V	BUFCONFIG = 0	41
VREF output voltage	VREF	1.38	1.4	1.42	V	BUFCONFIG = 1	41
ADC offset error	EO	-5		5	mV	Internal or External reference	40
ADC integral linearity error	EI	-2		2	LSB	External reference	40
ADC gain error	EG	-4		4	LSB	External reference	40
Comparator input offset voltage	Voffset	-20		20	mV		42
Temperature coefficient of VREF	TCVREF			80	ppm/°C	BUFCONFIG = {1}	41

CAD (KiCad official)

Symbol: MSPM0G3507SRGZR
Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
3D model files: mspm0g3507srgzr-etched.step / mspm0g3507srgzr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mspm0g3507srgzr.step / mspm0g3507srgzr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (120 pp, sha256 0cba2418fd28709c, retrieved 2026-10-22, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# MSPM0G3507SRGZR

**Texas Instruments** · IC · VQFN-48-EP(7x7)

MSPM0G3507SRGZR from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PA0 | bidirectional | 5V-tolerant open-drain GPIO (wake from SHUTDOWN) muxed with UART0_TX, I2C0_SDA, TIMA0_C0, TIMG8_C1 and FCC_IN, and the default BSL I2C data pin. |
| 2 | PA1 | bidirectional | 5V-tolerant open-drain GPIO (wake from SHUTDOWN) muxed with UART0_RX, I2C0_SCL, TIMA0_C1 and TIMG8 signals, and the default BSL I2C clock pin. |
| 3 | PA28 | bidirectional | High-drive GPIO (wake from SHUTDOWN) muxed with UART0_TX, I2C0_SDA, TIMA0_C3, TIMA_FAL0, TIMG7_C0 and TIMA1_C0. |
| 4 | NRST | input | Active-low reset input that must be pulled high to VDD for the device to start. |
| 5 | PA31 | bidirectional | High-drive GPIO (wake from SHUTDOWN) muxed with UART0_RX, I2C0_SCL, TIMA0_C3N, TIMG12_C1, CLK_OUT, TIMG7_C1 and TIMA1_C1. |
| 6 | VDD | power_in | Power supply, 1.62 V to 3.6 V, with 10 µF recommended between VDD and VSS. |
| 7 | VSS | power_in | Ground supply. |
| 8 | PA2 | bidirectional | Standard GPIO that is also the ROSC pin for the external 100 kΩ SYSOSC correction resistor to VSS; muxed with TIMG8_C1, SPI0_CS0, TIMG7_C1 and SPI1_CS0. |
| 9 | PA3 | bidirectional | Standard GPIO that is also LFXIN, the low-frequency crystal oscillator input; muxed with TIMG8_C0, SPI0_CS1, UART2_CTS, TIMA0_C2, COMP1_OUT, TIMG7_C0, TIMA0_C1 and I2C1_SDA. |
| 10 | PA4 | bidirectional | Standard GPIO that is also LFXOUT, the low-frequency crystal output, and LFCLK_IN; muxed with SPI0_POCI, UART2_RTS, TIMA0_C3 and I2C1_SCL. |
| 11 | PA5 | bidirectional | Standard GPIO that is also HFXIN, the high-frequency crystal oscillator input; muxed with TIMG8_C0, SPI0_PICO, TIMA_FAL1, TIMG0_C0, TIMG6_C0 and FCC_IN. |
| 12 | PA6 | bidirectional | Standard GPIO that is also HFXOUT, the high-frequency crystal output, and HFCLK_IN; muxed with TIMG8_C1, SPI0_SCK, TIMA_FAL0, TIMG0_C1, TIMG6_C1 and TIMA0_C2N. |
| 13 | PA7 | bidirectional | Standard GPIO muxed with COMP0_OUT, CLK_OUT, TIMG8_C0, TIMA0_C2, TIMG8_IDX, TIMG7_C1 and TIMA0_C1. |
| 14 | PB2 | bidirectional | Standard GPIO muxed with UART3_TX, UART2_CTS, I2C1_SCL, TIMA0_C3, UART1_CTS, TIMG6_C0 and TIMA1_C0. |
| 15 | PB3 | bidirectional | Standard GPIO muxed with UART3_RX, UART2_RTS, I2C1_SDA, TIMA0_C3N, UART1_RTS, TIMG6_C1 and TIMA1_C1. |
| 16 | PA8 | bidirectional | Standard GPIO muxed with UART1_TX, SPI0_CS0, UART0_RTS, TIMA0_C0 and TIMA1_C0N. |
| 17 | PA9 | bidirectional | High-speed GPIO muxed with UART1_RX, SPI0_PICO, UART0_CTS, TIMA0_C1, RTC_OUT, CLK_OUT and TIMA timer outputs. |
| 18 | PA10 | bidirectional | High-drive GPIO (wake from SHUTDOWN) muxed with UART0_TX, SPI0_POCI, I2C0_SDA, I2C1_SDA and CLK_OUT, and the default BSL UART transmit pin. |
| 19 | PA11 | bidirectional | High-drive GPIO (wake from SHUTDOWN) muxed with UART0_RX, SPI0_SCK, I2C0_SCL, COMP0_OUT and I2C1_SCL, and the default BSL UART receive pin. |
| 20 | PB6 | bidirectional | Standard GPIO muxed with UART1_TX, SPI1_CS0, SPI0_CS1, TIMG8_C0, UART2_CTS, TIMG6_C0 and TIMA1_C0N. |
| 21 | PB7 | bidirectional | Standard GPIO muxed with UART1_RX, SPI1_POCI, SPI0_CS2, TIMG8_C1, UART2_RTS, TIMG6_C1 and TIMA1_C1N. |
| 22 | PB8 | bidirectional | Standard GPIO muxed with UART1_CTS, SPI1_PICO, TIMA0_C0 and COMP1_OUT. |
| 23 | PB9 | bidirectional | Standard GPIO muxed with UART1_RTS, SPI1_SCK, TIMA0_C1 and TIMA0_C0N. |
| 24 | PB14 | bidirectional | Standard GPIO muxed with SPI1_CS3, SPI1_POCI, SPI0_CS3, TIMG12_C1, TIMG8_IDX and TIMA0_C0. |
| 25 | PB15 | bidirectional | Standard GPIO muxed with UART2_TX, SPI1_PICO, UART3_CTS, TIMG8_C0 and TIMG7_C0. |
| 26 | PB16 | bidirectional | Standard GPIO muxed with UART2_RX, SPI1_SCK, UART3_RTS, TIMG8_C1 and TIMG7_C1. |
| 27 | PA12 | bidirectional | High-speed GPIO muxed with UART3_CTS, SPI0_SCK, TIMG0_C0, CAN_TX, TIMA0_C3 and FCC_IN. |
| 28 | PA13 | bidirectional | High-speed GPIO with COMP0_IN2- analog input, muxed with UART3_RTS, SPI0_POCI, UART3_RX, TIMG0_C1, CAN_RX and TIMA0_C3N. |
| 29 | PA14 | bidirectional | High-speed GPIO with COMP0_IN2+ and ADC input A0_12, muxed with UART0_CTS, SPI0_PICO, UART3_TX, TIMG12_C0 and CLK_OUT. |
| 30 | PA15 | bidirectional | Standard GPIO with ADC input A1_0, DAC_OUT, OPA0_IN2+, OPA1_IN2+, COMP0_IN3+ and COMP1_IN3+, muxed with UART0_RTS, SPI1_CS2, I2C1_SCL and timer signals. |
| 31 | PA16 | bidirectional | Standard GPIO with ADC input A1_1 and OPA1_OUT, muxed with COMP2_OUT, SPI1_POCI, I2C1_SDA, TIMA1_C1 and FCC_IN. |
| 32 | PA17 | bidirectional | Standard GPIO with wake from SHUTDOWN, ADC input A1_2, OPA1_IN1- and COMP0_IN1-, muxed with UART1_TX, SPI1_SCK, I2C1_SCL and timer signals. |
| 33 | PA18 | bidirectional | Standard GPIO with wake from SHUTDOWN, ADC input A1_3, OPA1_IN1+, COMP0_IN1+ and GPAMP_IN-, muxed with UART1_RX, SPI1_PICO and I2C1_SDA, and the default BSL_invoke pin. |
| 34 | PA19 | bidirectional | High-speed GPIO used as SWDIO, the serial wire debug data input/output. |
| 35 | PA20 | bidirectional | Standard GPIO used as SWCLK, the serial wire debug clock input. |
| 36 | PB17 | bidirectional | Standard GPIO with ADC input A1_4 and COMP1_IN2-, muxed with UART2_TX, SPI0_PICO, SPI1_CS1, TIMA1_C0 and TIMA0_C2. |
| 37 | PB18 | bidirectional | Standard GPIO with ADC input A1_5 and COMP1_IN2+, muxed with UART2_RX, SPI0_SCK, SPI1_CS2, TIMA1_C1 and TIMA0_C2N. |
| 38 | PB19 | bidirectional | Standard GPIO with ADC input A1_6, COMP2_IN1+ and OPA1_IN0+, muxed with COMP2_OUT, SPI0_POCI, TIMG8_C1, UART0_CTS and TIMG7_C1. |
| 39 | PA21 | bidirectional | Standard GPIO with ADC input A1_7, COMP2_IN1- and VREF- (voltage reference ground); no injection current allowed since it has an internal test connection. |
| 40 | PA22 | bidirectional | Standard GPIO with ADC input A0_7, GPAMP_OUT and OPA0_OUT, muxed with UART2_RX, TIMG8_C1, UART1_RTS, TIMA0_C1 and CLK_OUT. |
| 41 | PB20 | bidirectional | Standard GPIO with ADC input A0_6 and OPA1_IN0-, muxed with SPI0_CS2, SPI1_CS0, TIMA0_C2, TIMG12_C0 and TIMA_FAL1. |
| 42 | PB24 | bidirectional | Standard GPIO with ADC input A0_5 and COMP1_IN1+, muxed with SPI0_CS3, SPI0_CS1, TIMA0_C3, TIMG12_C1 and TIMA0_C1N. |
| 43 | PA23 | bidirectional | Standard GPIO with COMP1_IN1- and VREF+ (external reference input or internal reference output), muxed with UART2_TX, SPI0_CS3, TIMA0_C3 and TIMG0_C0. |
| 44 | PA24 | bidirectional | Standard GPIO with ADC input A0_3 and OPA0_IN1-, muxed with UART2_RX, SPI0_CS2, TIMA0_C3N, TIMG0_C1 and UART3_RTS. |
| 45 | PA25 | bidirectional | Standard GPIO with ADC input A0_2 and OPA0_IN1+, muxed with UART3_RX, SPI1_CS3, TIMG12_C1, TIMA0_C3 and TIMA0_C1N. |
| 46 | PA26 | bidirectional | Standard GPIO with ADC input A0_1, COMP0_IN0+, OPA0_IN0+ and GPAMP_IN+, muxed with UART3_TX, SPI1_CS0, TIMG8_C0, TIMA_FAL0 and CAN_TX. |
| 47 | PA27 | bidirectional | Standard GPIO with ADC input A0_0, COMP0_IN0- and OPA0_IN0-, muxed with RTC_OUT, SPI1_CS1, TIMG8_C1, TIMA_FAL2 and CAN_RX. |
| 48 | VCORE | power_in | Regulated core supply output that must only connect to a 470 nF (0.47 µF) capacitor to VSS, with no external supply or load. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-48-EP(7x7) |
| Category |  |
| Pins | 49 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VDD | 1.62 |  | 3.6 | V |  | 25 |
| Ambient temperature, S version | TA | -40 |  | 125 | °C |  | 25 |
| Max junction temperature, S version | TJ |  |  | 130 | °C |  | 25 |
| Capacitor between VDD and VSS | CVDD | 10 |  |  | uF |  | 25 |
| Capacitor between VCORE and VSS | CVCORE | 470 |  |  | nF |  | 25 |
| Supply voltage at VDD pin | VDD | -0.3 |  | 4.1 | V | At VDD pin | 25 |
| Input voltage, 5-V tolerant open-drain pins | VI | -0.3 |  | 5.5 | V | Applied to any 5-V tolerant open-drain pins | 25 |
| Input voltage, common pins | VI | -0.3 |  | 4.1 | V | Applied to any common tolerance pins; VDD + 0.3 (4.1 MAX) | 25 |
| Diode current at any pin | ID | -2 |  | 2 | mA | Diode current at any device pin | 25 |
| Storage temperature | Tstg | -40 |  | 150 | °C |  | 25 |
| Junction temperature | TJ | -40 |  | 130 | °C |  | 25 |
| ESD HBM | V(ESD) | -2000 |  | 2000 | V | HBM, all pins | 25 |
| ESD CDM | V(ESD) | -500 |  | 500 | V | CDM, all pins | 25 |
| Junction-to-ambient thermal resistance VQFN-48 (RGZ) | RθJA |  | 30.1 |  | °C/W | VQFN-48 (RGZ) | 26 |
| Junction-to-case (top) thermal resistance | RθJC(top) |  | 20.7 |  | °C/W | VQFN-48 (RGZ) | 26 |
| Junction-to-board thermal resistance | RθJB |  | 12.5 |  | °C/W | VQFN-48 (RGZ) | 26 |
| Junction-to-case (bottom) thermal resistance | RθJC(bot) |  | 4.2 |  | °C/W | VQFN-48 (RGZ) | 26 |
| Power-on reset voltage, rising | VPOR+ | 0.95 | 1.3 | 1.59 | V | Rising | 29 |
| Power-on reset voltage, falling | VPOR- | 0.9 | 1.25 | 1.54 | V | Falling | 29 |
| SHUTDOWN supply current | IDDSHDN |  | 40 | 80 | nA | VDD=3.3V, -40°C | 29 |
| RUN mode supply current | IDDRUN |  | 8 |  | mA | VDD=3.3V, 80MHz, MCLK=SYSPLL, CoreMark, flash, -40°C | 28 |
| Brown-out reset level 0 rising | VBOR0+ | 1.56 | 1.59 | 1.62 | V | Rising | 30 |
| Brown-out reset level 0 falling | VBOR0- | 1.55 | 1.58 | 1.61 | V | Falling | 30 |
| Program and erase supply voltage | VDDPGM/ERASE | 1.62 |  | 3.6 | V |  | 30 |
| LFOSC accuracy | LFOSC accuracy | -3 |  | 3 | % | -40 ℃ ≤ Ta ≤ 85 ℃ | 33 |
| LFOSC accuracy | LFOSC accuracy | -5 |  | 5 | % | -40 ℃ ≤ Ta ≤ 125 ℃ | 33 |
| SYSOSC accuracy FCL disabled 32MHz | fSYSOSC | -2.6 |  | 1.8 | % | SETUSEFCL=0, SYSOSCCFG.FREQ=00, -40 ℃ ≤ Ta ≤ 125 ℃ | 33 |
| VREF output voltage | VREF | 2.46 | 2.5 | 2.54 | V | BUFCONFIG = 0 | 41 |
| VREF output voltage | VREF | 1.38 | 1.4 | 1.42 | V | BUFCONFIG = 1 | 41 |
| ADC offset error | EO | -5 |  | 5 | mV | Internal or External reference | 40 |
| ADC integral linearity error | EI | -2 |  | 2 | LSB | External reference | 40 |
| ADC gain error | EG | -4 |  | 4 | LSB | External reference | 40 |
| Comparator input offset voltage | Voffset | -20 |  | 20 | mV |  | 42 |
| Temperature coefficient of VREF | TCVREF |  |  | 80 | ppm/°C | BUFCONFIG = {1} | 41 |

## CAD (KiCad official)

- Symbol: `MSPM0G3507SRGZR`
- Footprint: `Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm`
- 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
- 3D model files: `mspm0g3507srgzr-etched.step` / `mspm0g3507srgzr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `mspm0g3507srgzr.step` / `mspm0g3507srgzr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/gpn/mspm0g3506) (120 pp, sha256 `0cba2418fd28709c`, retrieved 2026-10-22, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/mspm0g3507srgzr-datasheet.pdf)