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MSPM0G1507SRGZR

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Texas Instruments Microcontrollers (MCU/MPU/SOC), VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MSPM0G1507SRGZR

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · VQFN-48-EP(7x7)

MSPM0G1507SRGZR from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PA0 / FCC_IN bidirectional 5V-tolerant open-drain I/O (ODIO) that needs an external pull-up for output-high and can wake the device from SHUTDOWN; alternates include UART0_TX, I2C0_SDA and FCC_IN.
2 PA1 bidirectional 5V-tolerant open-drain I/O (ODIO) that needs an external pull-up for output-high and can wake the device from SHUTDOWN; alternates include UART0_RX, I2C0_SCL and TIMA0_C1.
3 PA28 bidirectional High-drive I/O that can wake the device from SHUTDOWN; alternates include UART0_TX, I2C0_SDA and TIMA0_C3.
4 NRST input Active-low reset input that must be pulled up to VDD, otherwise the device cannot start.
5 PA31 / CLK_OUT bidirectional High-drive I/O that can wake the device from SHUTDOWN; alternates include UART0_RX, I2C0_SCL and CLK_OUT.
6 VDD power_in Supply input with a recommended range of 1.62 V to 3.6 V (absolute maximum -0.3 V to 4.1 V), decoupled to VSS with 10 µF and 0.1 µF low-ESR capacitors placed within a few millimeters of the pin.
7 VSS power_in Ground reference for the device; the exposed thermal pad is recommended to be connected to VSS.
8 PA2 / ROSC bidirectional Standard I/O that serves as the ROSC input for a 100 kΩ ±0.1% ±25 ppm resistor to VSS when SYSOSC frequency correction loop is used; otherwise it is a digital I/O.
9 PA3 / LFXIN bidirectional Standard I/O that serves as the LFXIN input of the external 32 kHz low-frequency crystal oscillator (LFXT).
10 PA4 / LFCLK_IN / LFXOUT bidirectional Standard I/O that serves as the LFXOUT output of the 32 kHz crystal oscillator or as the LFCLK_IN digital clock input (29491 Hz to 36045 Hz, logic-level square wave).
11 PA5 / HFXIN / FCC_IN bidirectional Standard I/O that serves as the HFXIN input of the high-frequency crystal oscillator HFXT (4 MHz to 48 MHz range); also usable as FCC_IN.
12 PA6 / HFCLK_IN / HFXOUT bidirectional Standard I/O that serves as the HFXOUT output of HFXT or as the HFCLK_IN digital clock input (4 MHz to 48 MHz).
13 PA7 / CLK_OUT bidirectional Standard I/O with alternates COMP0_OUT and CLK_OUT for clock output.
14 PB2 bidirectional Standard general-purpose I/O with alternates including UART3_TX, I2C1_SCL and TIMA0_C3.
15 PB3 bidirectional Standard general-purpose I/O with alternates including UART3_RX, I2C1_SDA and TIMA0_C3N.
16 PA8 bidirectional Standard general-purpose I/O with alternates including UART1_TX, SPI0_CS0 and TIMA0_C0.
17 PA9 / RTC_OUT / CLK_OUT bidirectional High-speed I/O (HSIO) with alternates including UART1_RX, SPI0_PICO, RTC_OUT and CLK_OUT.
18 PA10 / CLK_OUT bidirectional High-drive I/O with alternates including UART0_TX, SPI0_POCI, I2C0_SDA and CLK_OUT.
19 PA11 bidirectional High-drive I/O with alternates including UART0_RX, SPI0_SCK, I2C0_SCL and COMP0_OUT.
20 PB6 bidirectional Standard general-purpose I/O with alternates including UART1_TX, SPI1_CS0 and TIMG8_C0.
21 PB7 bidirectional Standard general-purpose I/O with alternates including UART1_RX, SPI1_POCI and TIMG8_C1.
22 PB8 bidirectional Standard general-purpose I/O with alternates including UART1_CTS, SPI1_PICO and COMP1_OUT.
23 PB9 bidirectional Standard general-purpose I/O with alternates including UART1_RTS, SPI1_SCK and TIMA0_C1.
24 PB14 bidirectional Standard general-purpose I/O with alternates including SPI1_CS3, SPI1_POCI and TIMA0_C0.
25 PB15 bidirectional Standard general-purpose I/O with alternates including UART2_TX, SPI1_PICO and UART3_CTS.
26 PB16 bidirectional Standard general-purpose I/O with alternates including UART2_RX, SPI1_SCK and UART3_RTS.
27 PA12 / FCC_IN bidirectional High-speed I/O with alternates including UART3_CTS, SPI0_SCK, TIMG0_C0 and FCC_IN.
28 PA13 bidirectional High-speed I/O with COMP0_IN2- as analog input and alternates including UART3_RTS, SPI0_POCI and UART3_RX.
29 PA14 bidirectional High-speed I/O that is also ADC0 analog input A0_12 and COMP0_IN2+; alternates include UART0_CTS, SPI0_PICO and CLK_OUT.
30 PA15 bidirectional Standard I/O that is ADC1 analog input A1_0 and the DAC_OUT pin; avoid external circuitry on this pin when DAC_OUT is enabled.
31 PA16 / A1_1 / FCC_IN bidirectional Standard I/O that is ADC1 analog input A1_1 and OPA1_OUT; alternates include COMP2_OUT, SPI1_POCI and I2C1_SDA.
32 PA17 / A1_2 bidirectional Standard I/O with wake-from-SHUTDOWN capability that is ADC1 analog input A1_2, OPA1_IN1- and COMP0_IN1-; alternates include UART1_TX, SPI1_SCK and I2C1_SCL.
33 PA18 / A1_3 bidirectional Standard I/O with wake-from-SHUTDOWN capability that is ADC1 analog input A1_3, OPA1_IN1+, COMP0_IN1+ and GPAMP_IN-; alternates include UART1_RX, SPI1_PICO and I2C1_SDA.
34 PA19 / SWDIO bidirectional High-speed I/O used as the bidirectional serial-wire debug data line SWDIO.
35 PA20 / SWCLK input Standard I/O used as the serial-wire debug clock input SWCLK from the debug probe.
36 PB17 / A1_4 bidirectional Standard I/O that is ADC1 analog input A1_4 and COMP1_IN2-; alternates include UART2_TX, SPI0_PICO and TIMA1_C0.
37 PB18 / A1_5 bidirectional Standard I/O that is ADC1 analog input A1_5 and COMP1_IN2+; alternates include UART2_RX, SPI0_SCK and TIMA1_C1.
38 PB19 / A1_6 bidirectional Standard I/O that is ADC1 analog input A1_6, COMP2_IN1+ and OPA1_IN0+; alternates include COMP2_OUT, SPI0_POCI and UART0_CTS.
39 PA21 bidirectional Standard I/O that is ADC1 analog input A1_7 and COMP2_IN1-; this pad is also the VREF- pin, which is an external reference input or internal reference output with ground reference.
40 PA22 bidirectional Standard I/O that is ADC0 analog input A0_7 and GPAMP_OUT/OPA0_OUT; alternates include UART2_RX, TIMG8_C1 and CLK_OUT.
41 PB20 / A0_6 bidirectional Standard I/O that is ADC0 analog input A0_6 and OPA1_IN0-; alternates include SPI0_CS2, SPI1_CS0 and TIMA0_C2.
42 PB24 / A0_5 bidirectional Standard I/O that is ADC0 analog input A0_5 and COMP1_IN1+; alternates include SPI0_CS3, SPI0_CS1 and TIMA0_C3.
43 PA23 / VREF+ bidirectional Standard I/O that is COMP1_IN1- and the VREF+ pin, an external reference input or internal reference output; a decoupling capacitor of 0.7 µF to 1.15 µF is required between VREF+ and VREF-/GND when used.
44 PA24 / A0_3 bidirectional Standard I/O that is ADC0 analog input A0_3 and OPA0_IN1-; alternates include UART2_RX, SPI0_CS2 and TIMA0_C3N.
45 PA25 / A0_2 / OPA0_IN1+ bidirectional Standard I/O that is ADC0 analog input A0_2 and OPA0_IN1+; alternates include UART3_RX, SPI1_CS3 and TIMG12_C1.
46 PA26 / A0_1 bidirectional Standard I/O that is ADC0 analog input A0_1, COMP0_IN0+, OPA0_IN0+ and GPAMP_IN+; alternates include UART3_TX, SPI1_CS0 and TIMG8_C0.
47 PA27 / RTC_OUT / A0_0 bidirectional Standard I/O that is ADC0 analog input A0_0, COMP0_IN0- and OPA0_IN0-; alternates include RTC_OUT, SPI1_CS1 and TIMG8_C1.
48 VCORE power_out Regulated core-supply output that must only be connected to a 470 nF capacitor to VSS placed close to the pin; no voltage or external load may be applied to it.
49 PAD passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-48-EP(7x7)
Category Embedded Processors & Controllers
Pins 49

CAD (KiCad official)

  • Symbol: MSPM0G1507SRGZR
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: mspm0g1507srgzr-etched.step / mspm0g1507srgzr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mspm0g1507srgzr.step / mspm0g1507srgzr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (101 pp, sha256 5fe0f52106449460, retrieved 2026-10-10, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF