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MSPM0G1506SRGZR

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Texas Instruments Microcontrollers (MCU/MPU/SOC), VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MSPM0G1506SRGZR

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · VQFN-48-EP(7x7)

MSPM0G1506SRGZR from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PA0 bidirectional 5V-tolerant open-drain GPIO that can wake the device from SHUTDOWN, with UART0_TX, I2C0_SDA, TIMA0_C0, TIMA_FAL1, TIMG8_C1 and FCC_IN functions, and BSLSDA as the default I2C BSL data.
2 PA1 bidirectional 5V-tolerant open-drain GPIO that can wake the device from SHUTDOWN, with UART0_RX, I2C0_SCL, TIMA0_C1, TIMA_FAL2, TIMG8_IDX and TIMG8_C0 functions, and BSLSCL as the default I2C BSL clock.
3 PA28 bidirectional High-drive GPIO that can wake the device from SHUTDOWN, with UART0_TX, I2C0_SDA, TIMA0_C3, TIMA_FAL0, TIMG7_C0 and TIMA1_C0 functions.
4 NRST input Active-low reset input that must be pulled up to VDD or the device will not start.
5 PA31 bidirectional High-drive GPIO that can wake the device from SHUTDOWN, with UART0_RX, I2C0_SCL, TIMA0_C3N, TIMG12_C1, CLK_OUT, TIMG7_C1 and TIMA1_C1 functions.
6 VDD power_in Power supply, 1.62 V to 3.6 V, decoupled to VSS with a 10 uF capacitor (0.1 uF also recommended) placed close to the pin.
7 VSS power_in Ground supply.
8 PA2 bidirectional Standard-drive GPIO that doubles as ROSC, the external 100 kOhm resistor input to VSS for the SYSOSC frequency correction loop, with TIMG8_C1, SPI0_CS0, TIMG7_C1 and SPI1_CS0 functions.
9 PA3 bidirectional Standard-drive GPIO that doubles as LFXIN, the low-frequency crystal oscillator input, with TIMG8_C0, SPI0_CS1, UART2_CTS, TIMA0_C2, COMP1_OUT, TIMG7_C0, TIMA0_C1 and I2C1_SDA functions.
10 PA4 bidirectional Standard-drive GPIO that doubles as LFXOUT, the low-frequency crystal oscillator output, and LFCLK_IN, with TIMG8_C1, SPI0_POCI, UART2_RTS, TIMA0_C3, TIMG7_C1, TIMA0_C1N and I2C1_SCL functions.
11 PA5 bidirectional Standard-drive GPIO that doubles as HFXIN, the high-frequency crystal oscillator input, with TIMG8_C0, SPI0_PICO, TIMA_FAL1, TIMG0_C0, TIMG6_C0 and FCC_IN functions.
12 PA6 bidirectional Standard-drive GPIO that doubles as HFXOUT, the high-frequency crystal oscillator output, and HFCLK_IN, with TIMG8_C1, SPI0_SCK, TIMA_FAL0, TIMG0_C1, TIMG6_C1 and TIMA0_C2N functions.
13 PA7 bidirectional Standard-drive GPIO with COMP0_OUT, CLK_OUT, TIMG8_C0, TIMA0_C2, TIMG8_IDX, TIMG7_C1 and TIMA0_C1 functions.
14 PB2 bidirectional Standard-drive GPIO with UART3_TX, UART2_CTS, I2C1_SCL, TIMA0_C3, UART1_CTS, TIMG6_C0 and TIMA1_C0 functions.
15 PB3 bidirectional Standard-drive GPIO with UART3_RX, UART2_RTS, I2C1_SDA, TIMA0_C3N, UART1_RTS, TIMG6_C1 and TIMA1_C1 functions.
16 PA8 bidirectional Standard-drive GPIO with UART1_TX, SPI0_CS0, UART0_RTS, TIMA0_C0 and TIMA1_C0N functions.
17 PA9 bidirectional High-speed GPIO with UART1_RX, SPI0_PICO, UART0_CTS, TIMA0_C1, RTC_OUT, TIMA0_C0N, TIMA1_C1N and CLK_OUT functions.
18 PA10 bidirectional High-drive GPIO that can wake the device from SHUTDOWN, with UART0_TX, SPI0_POCI, I2C0_SDA, TIMA1_C0, TIMG12_C0, TIMA0_C2, I2C1_SDA and CLK_OUT functions, and BSLTX as the default UART BSL transmit.
19 PA11 bidirectional High-drive GPIO that can wake the device from SHUTDOWN, with UART0_RX, SPI0_SCK, I2C0_SCL, TIMA1_C1, COMP0_OUT, TIMA0_C2N and I2C1_SCL functions, and BSLRX as the default UART BSL receive.
20 PB6 bidirectional Standard-drive GPIO with UART1_TX, SPI1_CS0, SPI0_CS1, TIMG8_C0, UART2_CTS, TIMG6_C0 and TIMA1_C0N functions.
21 PB7 bidirectional Standard-drive GPIO with UART1_RX, SPI1_POCI, SPI0_CS2, TIMG8_C1, UART2_RTS, TIMG6_C1 and TIMA1_C1N functions.
22 PB8 bidirectional Standard-drive GPIO with UART1_CTS, SPI1_PICO, TIMA0_C0 and COMP1_OUT functions.
23 PB9 bidirectional Standard-drive GPIO with UART1_RTS, SPI1_SCK, TIMA0_C1 and TIMA0_C0N functions.
24 PB14 bidirectional Standard-drive GPIO with SPI1_CS3, SPI1_POCI, SPI0_CS3, TIMG12_C1, TIMG8_IDX and TIMA0_C0 functions.
25 PB15 bidirectional Standard-drive GPIO with UART2_TX, SPI1_PICO, UART3_CTS, TIMG8_C0 and TIMG7_C0 functions.
26 PB16 bidirectional Standard-drive GPIO with UART2_RX, SPI1_SCK, UART3_RTS, TIMG8_C1 and TIMG7_C1 functions.
27 PA12 bidirectional High-speed GPIO with UART3_CTS, SPI0_SCK, TIMG0_C0, TIMA0_C3 and FCC_IN functions.
28 PA13 bidirectional High-speed GPIO with analog input COMP0_IN2- and UART3_RTS, SPI0_POCI, UART3_RX, TIMG0_C1 and TIMA0_C3N functions.
29 PA14 bidirectional High-speed GPIO with analog inputs COMP0_IN2+ and ADC0 channel A0_12, plus UART0_CTS, SPI0_PICO, UART3_TX, TIMG12_C0 and CLK_OUT functions.
30 PA15 bidirectional Standard-drive GPIO with analog functions A1_0, DAC_OUT, OPA0_IN2+, OPA1_IN2+, COMP0_IN3+ and COMP1_IN3+; avoid external circuitry on this pin when DAC_OUT is used.
31 PA16 bidirectional Standard-drive GPIO with analog functions A1_1 and OPA1_OUT, plus COMP2_OUT, SPI1_POCI, I2C1_SDA, TIMA1_C1 and FCC_IN functions.
32 PA17 bidirectional Standard-drive GPIO with SHUTDOWN wake capability and analog functions A1_2, OPA1_IN1- and COMP0_IN1-, plus UART1_TX, SPI1_SCK and I2C1_SCL functions.
33 PA18 bidirectional Standard-drive GPIO with SHUTDOWN wake capability and analog functions A1_3, OPA1_IN1+, COMP0_IN1+ and GPAMP_IN-, plus UART1_RX, SPI1_PICO, I2C1_SDA and BSL_invoke functions.
34 PA19 bidirectional High-speed GPIO that carries SWDIO, the serial wire debug data input/output.
35 PA20 bidirectional Standard-drive GPIO that carries SWCLK, the serial wire debug clock input.
36 PB17 bidirectional Standard-drive GPIO with analog functions A1_4 and COMP1_IN2-, plus UART2_TX, SPI0_PICO, SPI1_CS1, TIMA1_C0 and TIMA0_C2 functions.
37 PB18 bidirectional Standard-drive GPIO with analog functions A1_5 and COMP1_IN2+, plus UART2_RX, SPI0_SCK, SPI1_CS2, TIMA1_C1 and TIMA0_C2N functions.
38 PB19 bidirectional Standard-drive GPIO with analog functions A1_6, COMP2_IN1+ and OPA1_IN0+, plus COMP2_OUT, SPI0_POCI, TIMG8_C1, UART0_CTS and TIMG7_C1 functions.
39 PA21 bidirectional Standard-drive GPIO with analog functions A1_7, COMP2_IN1- and VREF- (voltage reference ground, with a decoupling capacitor between VREF+ and VREF-), plus UART2_TX, TIMG8_C0, UART1_CTS, TIMA0_C0 and TIMG6_C0 functions.
40 PA22 bidirectional Standard-drive GPIO with analog functions A0_7, GPAMP_OUT and OPA0_OUT, plus UART2_RX, TIMG8_C1, UART1_RTS, TIMA0_C1, CLK_OUT, TIMA0_C0N and TIMG6_C1 functions.
41 PB20 bidirectional Standard-drive GPIO with analog functions A0_6 and OPA1_IN0-, plus SPI0_CS2, SPI1_CS0, TIMA0_C2, TIMG12_C0, TIMA_FAL1, TIMA0_C1 and TIMA1_C1N functions.
42 PB24 bidirectional Standard-drive GPIO with analog functions A0_5 and COMP1_IN1+, plus SPI0_CS3, SPI0_CS1, TIMA0_C3, TIMG12_C1, TIMA0_C1N and TIMA1_C0N functions.
43 PA23 bidirectional Standard-drive GPIO with analog functions COMP1_IN1- and VREF+ (voltage reference supply, external reference input or internal reference output, with a 1 uF decoupling capacitor recommended), plus UART2_TX, SPI0_CS3, TIMA0_C3, TIMG0_C0, UART3_CTS, TIMG7_C0 and TIMG8_C0 functions.
44 PA24 bidirectional Standard-drive GPIO with analog functions A0_3 and OPA0_IN1-, plus UART2_RX, SPI0_CS2, TIMA0_C3N, TIMG0_C1, UART3_RTS, TIMG7_C1 and TIMA1_C1 functions.
45 PA25 bidirectional Standard-drive GPIO with analog functions A0_2 and OPA0_IN1+, plus UART3_RX, SPI1_CS3, TIMG12_C1, TIMA0_C3 and TIMA0_C1N functions.
46 PA26 bidirectional Standard-drive GPIO with analog functions A0_1, COMP0_IN0+, OPA0_IN0+ and GPAMP_IN+, plus UART3_TX, SPI1_CS0, TIMG8_C0, TIMA_FAL0 and TIMG7_C0 functions.
47 PA27 bidirectional Standard-drive GPIO with analog functions A0_0, COMP0_IN0- and OPA0_IN0-, plus RTC_OUT, SPI1_CS1, TIMG8_C1, TIMA_FAL2 and TIMG7_C1 functions.
48 VCORE power_out Regulated core supply output that must connect only to a 470 nF capacitor to VSS, with no external voltage or load applied.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-48-EP(7x7)
Category Embedded Processors & Controllers
Pins 49

CAD (KiCad official)

  • Symbol: MSPM0G1506SRGZR
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: mspm0g1506srgzr-etched.step / mspm0g1506srgzr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mspm0g1506srgzr.step / mspm0g1506srgzr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (101 pp, sha256 5fe0f52106449460, retrieved 2026-10-01, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF