component
MSPM0G1506SRGER
Public Made by Adomby adom
TEXAS INSTRUMENTS Global Sourcing Parts, VQFN-24(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMSPM0G1506SRGER
TEXAS INSTRUMENTS · Global Sourcing Parts · VQFN-24(4x4)
MSPM0G1506SRGER from TEXAS INSTRUMENTS, in a VQFN-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PA1 | bidirectional | 5V-tolerant open-drain GPIO with wake-up from SHUTDOWN, muxed with UART0_RX, I2C0_SCL (default BSL I2C_SCL), TIMA0_C1, TIMA_FAL2, TIMG8_IDX and TIMG8_C0; needs a pullup to output high. |
| 2 | NRST | input | Active-low reset input that must be pulled high to VDD for the device to release from reset and boot. |
| 3 | VDD | power_in | Power supply, 1.62V to 3.6V, with a 10uF and 0.1uF ceramic capacitor to VSS placed close to the pin. |
| 4 | VSS | power_in | Ground supply. |
| 5 | PA2 | bidirectional | Standard GPIO that serves as ROSC for an external 100kΩ resistor to VSS when the SYSOSC frequency correction loop is used, muxed with TIMG8_C1, SPI0_CS0, TIMG7_C1 and SPI1_CS0. |
| 6 | PA3 | bidirectional | Standard GPIO muxed with TIMG8_C0, SPI0_CS1, UART2_CTS, TIMA0_C2, COMP1_OUT, TIMG7_C0, TIMA0_C1 and I2C1_SDA. |
| 7 | PA4 | bidirectional | Standard GPIO with LFXOUT crystal output, muxed with TIMG8_C1, SPI0_POCI, UART2_RTS, TIMA0_C3, LFCLK_IN, TIMG7_C1, TIMA0_C1N and I2C1_SCL. |
| 8 | PA9 | bidirectional | High-speed GPIO muxed with UART1_RX, SPI0_PICO, UART0_CTS, TIMA0_C1, RTC_OUT, TIMA0_C0N, TIMA1_C1N and CLK_OUT. |
| 9 | PA10 | bidirectional | High-drive GPIO with wake-up from SHUTDOWN and 20mA drive, muxed with UART0_TX (default BSL UART_TX), SPI0_POCI, I2C0_SDA, TIMA1_C0, TIMG12_C0, TIMA0_C2, I2C1_SDA and CLK_OUT. |
| 10 | PA11 | bidirectional | High-drive GPIO with wake-up from SHUTDOWN and 20mA drive, muxed with UART0_RX (default BSL UART_RX), SPI0_SCK, I2C0_SCL, TIMA1_C1, COMP0_OUT, TIMA0_C2N and I2C1_SCL. |
| 11 | PA15 | bidirectional | Standard GPIO with analog functions A1_0, DAC_OUT, OPA0_IN2+, OPA1_IN2+, COMP0_IN3+ and COMP1_IN3+, muxed with UART0_RTS, SPI1_CS2, I2C1_SCL and timer signals. |
| 12 | PA16 | bidirectional | Standard GPIO with analog functions A1_1 and OPA1_OUT, muxed with COMP2_OUT, SPI1_POCI, I2C1_SDA, TIMA1_C1, TIMA1_C1N, TIMA0_C2N and FCC_IN. |
| 13 | PA17 | bidirectional | Standard GPIO with wake-up from SHUTDOWN and analog functions A1_2, OPA1_IN1- and COMP0_IN1-, muxed with UART1_TX, SPI1_SCK, I2C1_SCL and timer signals. |
| 14 | PA18 | bidirectional | Standard GPIO with wake-up from SHUTDOWN and analog functions A1_3, OPA1_IN1+, COMP0_IN1+ and GPAMP_IN-, muxed with UART1_RX, SPI1_PICO and I2C1_SDA; default BSL_invoke input. |
| 15 | PA19 | bidirectional | High-speed GPIO that serves as the SWDIO serial wire debug data input/output. |
| 16 | PA20 | bidirectional | Standard GPIO that serves as the SWCLK serial wire debug clock input. |
| 17 | PA21 | bidirectional | Standard GPIO with analog functions A1_7, COMP2_IN1- and VREF- (voltage reference ground), muxed with UART2_TX, TIMG8_C0, UART1_CTS, TIMA0_C0 and TIMG6_C0; no injection current allowed. |
| 18 | PA22 | bidirectional | Standard GPIO with analog functions A0_7, GPAMP_OUT and OPA0_OUT, muxed with UART2_RX, TIMG8_C1, UART1_RTS, TIMA0_C1, CLK_OUT, TIMA0_C0N and TIMG6_C1. |
| 19 | PA23 | bidirectional | Standard GPIO with analog functions COMP1_IN1- and VREF+ (voltage reference supply, external reference input or internal reference output), muxed with UART2_TX, SPI0_CS3 and timer signals. |
| 20 | PA24 | bidirectional | Standard GPIO with analog functions A0_3 and OPA0_IN1-, muxed with UART2_RX, SPI0_CS2, TIMA0_C3N, TIMG0_C1, UART3_RTS, TIMG7_C1 and TIMA1_C1. |
| 21 | PA25 | bidirectional | Standard GPIO with analog functions A0_2 and OPA0_IN1+, muxed with UART3_RX, SPI1_CS3, TIMG12_C1, TIMA0_C3 and TIMA0_C1N. |
| 22 | PA26 | bidirectional | Standard GPIO with analog functions A0_1, COMP0_IN0+, OPA0_IN0+ and GPAMP_IN+, muxed with UART3_TX, SPI1_CS0, TIMG8_C0, TIMA_FAL0 and TIMG7_C0. |
| 23 | VCORE | power_out | Regulated core power supply output that connects only to a 0.47uF capacitor to VSS (1.35V); no external voltage or load may be applied. |
| 24 | PA0 | bidirectional | 5V-tolerant open-drain GPIO with wake-up from SHUTDOWN, muxed with UART0_TX, I2C0_SDA (default BSL I2C_SDA), TIMA0_C0, TIMA_FAL1, TIMG8_C1 and FCC_IN; needs a pullup to output high. |
| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TEXAS INSTRUMENTS |
| Package | VQFN-24(4x4) |
| Category | Global Sourcing Parts |
| Pins | 25 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VDD | -0.3 | 4.1 | V | At VDD pin | 30 | |
| Input voltage, 5-V tolerant open-drain pins | VI | -0.3 | 5.5 | V | Applied to any 5-V tolerant open-drain pins | 30 | |
| Input voltage, common tolerance pins | VI | -0.3 | 4.1 | V | Applied to any common tolerance pins; VDD + 0.3 (4.1 MAX) | 30 | |
| Current into VDD pin | IVDD | 80 | mA | -40℃ ≤ Tj ≤ 130℃ | 30 | ||
| Current out of VSS pin | IVSS | 80 | mA | -40℃ ≤ Tj≤ 130℃ | 30 | ||
| Diode current at any device pin | ID | -2 | 2 | mA | Diode current at any device pin | 30 | |
| Ambient temperature | TA | -40 | 125 | °C | Ambient Temperature | 30 | |
| Junction temperature | TJ | -40 | 130 | °C | Junction temperature | 30 | |
| Storage temperature | Tstg | -40 | 150 | °C | Storage temperature | 30 | |
| Supply voltage | VDD | 1.62 | 3.6 | V | 30 | ||
| Ambient temperature, S version | TA | -40 | 125 | °C | S version | 30 | |
| Max junction temperature, S version | TJ | 130 | °C | S version | 30 | ||
| Capacitor between VDD and VSS | CVDD | 10 | uF | 30 | |||
| Capacitor between VCORE and VSS | CVCORE | 470 | nF | 30 | |||
| MCLK, CPUCLK frequency with 2 flash wait states | fMCLK | 80 | MHz | 2 flash wait states | 31 | ||
| ULPCLK frequency | fULPCLK | 40 | MHz | 31 | |||
| Junction-to-ambient thermal resistance | RθJA | 40.3 | °C/W | VQFN-24 (RGE) | 31 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 30.8 | °C/W | VQFN-24 (RGE) | 31 | ||
| Junction-to-board thermal resistance | RθJB | 17.9 | °C/W | VQFN-24 (RGE) | 31 | ||
| Power-on reset voltage level, rising | VPOR+ | 0.95 | 1.3 | 1.59 | V | Rising | 34 |
| Power-on reset voltage level, falling | VPOR- | 0.9 | 1.25 | 1.54 | V | Falling | 34 |
| Brown-out reset level 0, rising | VBOR0+ | 1.56 | 1.59 | 1.62 | V | Rising (1) | 35 |
| Program and erase supply voltage | VDDPGM/ERASE | 1.62 | 3.6 | V | 35 | ||
| Supply current in SHUTDOWN mode | IDDSHDN | 40 | 80 | nA | VDD 3.3V, -40°C column | 34 | |
| RUN current, 80MHz | IDDRUN | 8.2 | mA | MCLK=SYSPLL, CoreMark, execute from flash, 80MHz, 25°C column | 33 | ||
| STANDBY current, LFCLK=LFXT | IDDSTBY0 | 2 | 7 | uA | LFCLK=LFXT, STOPCLKSTBY=0, RTC enabled, 32kHz, 25°C column | 34 | |
| SYSOSC accuracy, FCL enabled, internal ROSC, 32MHz | fSYSOSC | -2.1 | 1.6 | % | SETUSEFCL=1 -40 ℃ ≤ Ta ≤ 125 ℃ | 37 | |
| LFOSC accuracy | -5 | 5 | % | -40 ℃ ≤ Ta ≤ 125 ℃ | 38 | ||
| Pull up resistance | RPU | 40 | kΩ | All I/O except ODIO | 40 | ||
| ADC integral linearity error | EI | -2 | 2 | LSB | External reference (2) | 45 | |
| ADC offset error | EO | -5 | 5 | mV | Internal or External reference (2) (3) | 45 | |
| ADC gain error | EG | -4 | 4 | LSB | External reference (2) | 45 | |
| VREF output voltage | VREF | 1.38 | 1.4 | 1.42 | V | BUFCONFIG = 1 | 46 |
| VREF output voltage | VREF | 2.46 | 2.5 | 2.54 | V | BUFCONFIG = 0 | 46 |
| Comparator input offset voltage | Voffset | -20 | 20 | mV | 47 | ||
| ESD HBM | V(ESD) | -2000 | 2000 | V | Human body model (HBM), all pins | 30 | |
| ESD CDM | V(ESD) | -500 | 500 | V | Charged device model (CDM), all pins | 30 |
CAD (KiCad official)
- Symbol:
MSPM0G1506SRGER - Footprint:
Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm - 3D model: VQFN-24(4x4) (KiCad packages3D, STEP)
- 3D model files:
mspm0g1506srger-etched.step/mspm0g1506srger-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mspm0g1506srger.step/mspm0g1506srger.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: TEXAS INSTRUMENTS datasheet (135 pp, sha256
0e4369b6aeb4218c, retrieved 2026-10-27, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).