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MSPM0G1107TRHBR

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Texas Instruments Microcontrollers (MCU/MPU/SOC), VQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MSPM0G1107TRHBR

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · VQFN-32-EP(5x5)

MSPM0G1107TRHBR from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PA0 bidirectional 5V-tolerant open-drain I/O that can wake the device from SHUTDOWN, with UART0_TX, I2C0_SDA, FCC_IN and default BSL I2C_SDA functions.
2 PA1 bidirectional 5V-tolerant open-drain I/O that can wake the device from SHUTDOWN, with UART0_RX, I2C0_SCL, TIMA0_C1 and default BSL I2C_SCL functions.
3 NRST input Active-low reset input that must be pulled up to VDD, otherwise the device cannot start.
4 VDD power_in Supply voltage input, 1.62 V to 3.6 V recommended (absolute maximum 4.1 V), with 10 µF and 0.1 µF low-ESR decoupling placed close to the pin.
5 VSS power_in Ground reference for the device; TI recommends connecting the QFN exposed thermal pad to VSS.
6 PA2 bidirectional General-purpose digital I/O that serves as the ROSC pin for the external 100 kΩ, ±0.1% (±25 ppm) reference resistor to VSS used by the SYSOSC frequency correction loop; it can be used as GPIO if the FCL is not enabled.
7 PA3 bidirectional General-purpose digital I/O that also serves as the LFXIN input of the 32 kHz low-frequency crystal oscillator (LFXT).
8 PA4 bidirectional General-purpose digital I/O that also serves as the LFXOUT output of the LFXT oscillator and the LFCLK_IN digital clock input.
9 PA5 bidirectional General-purpose digital I/O that also serves as the HFXIN input of the 4 MHz to 48 MHz high-frequency crystal oscillator (HFXT) and FCC_IN.
10 PA6 bidirectional General-purpose digital I/O that also serves as the HFXOUT output of HFXT and the HFCLK_IN digital high-frequency clock input.
11 PA7 bidirectional General-purpose digital I/O with CLK_OUT and timer alternate functions.
12 PA8 bidirectional General-purpose digital I/O with UART1_TX, SPI0_CS0, UART0_RTS and timer alternate functions.
13 PA9 bidirectional High-speed digital I/O with RTC_OUT, CLK_OUT, UART1_RX and timer alternate functions.
14 PA10 bidirectional High-drive digital I/O rated for 20 mA, with default BSL UART_TX function.
15 PA11 bidirectional High-drive digital I/O rated for 20 mA, wake-capable from SHUTDOWN, with default BSL UART_RX function.
16 PA12 bidirectional High-speed digital I/O with UART3_CTS, SPI0_SCK, TIMG0_C0 and FCC_IN alternate functions.
17 PA13 bidirectional High-speed digital I/O with UART3_RTS, SPI0_POCI, UART3_RX and timer alternate functions.
18 PA14 bidirectional High-speed digital I/O that also serves as ADC0 analog input A0_12 and a CLK_OUT alternate function.
19 PA15 bidirectional Standard digital I/O that also serves as ADC1 analog input A1_0, with UART0_RTS, SPI1_CS2 and I2C1_SCL alternate functions.
20 PA16 bidirectional Standard digital I/O that also serves as ADC1 analog input A1_1, with SPI1_POCI, I2C1_SDA and FCC_IN alternate functions.
21 PA17 bidirectional Wake-capable standard digital I/O from SHUTDOWN that also serves as ADC1 analog input A1_2.
22 PA18 bidirectional Wake-capable standard digital I/O from SHUTDOWN that also serves as ADC1 analog input A1_3 and GPAMP_IN-, with default BSL_invoke function.
23 PA19 bidirectional High-speed digital I/O that carries the SWDIO serial-wire debug data signal.
24 PA20 bidirectional Standard digital I/O that carries the SWCLK serial-wire debug clock input.
25 PA21 bidirectional Standard digital I/O that also serves as ADC1 analog input A1_7 and VREF-; it has an internal test connection, so no current may be injected into this pin.
26 PA22 bidirectional Standard digital I/O that also serves as ADC0 analog input A0_7 and GPAMP_OUT, with CLK_OUT and UART2_RX alternate functions.
27 PA23 bidirectional Standard digital I/O that also serves as VREF+ for an external voltage reference input or internal reference output, requiring a decoupling capacitor between VREF+ and VREF-/GND when used.
28 PA24 bidirectional Standard digital I/O that also serves as ADC0 analog input A0_3, with UART2_RX and SPI0_CS2 alternate functions.
29 PA25 bidirectional Standard digital I/O that also serves as ADC0 analog input A0_2, with UART3_RX and SPI1_CS3 alternate functions.
30 PA26 bidirectional Standard digital I/O that also serves as ADC0 analog input A0_1 and GPAMP_IN+, with UART3_TX and SPI1_CS0 alternate functions.
31 PA27 bidirectional Standard digital I/O that also serves as ADC0 analog input A0_0 and RTC_OUT, with SPI1_CS1 and TIMG8_C1 alternate functions.
32 VCORE power_out Regulated core supply output at 1.35 V that must connect only to a 0.47 µF CVCORE capacitor to VSS, with no external voltage or load applied.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-32-EP(5x5)
Category Embedded Processors & Controllers
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage range (features summary) VDD 1.62 3.6 V 1
Operating temperature range (features summary) -40 105 °C 1
LFXT duty cycle DCLFXT 30 70 % 37
LFCLK_IN frequency fLFIN 29491 32768 36045 Hz SETUSEEXLF=1 37
LFCLK_IN duty cycle DCLFIN 40 60 % SETUSEEXLF=1 37
LFCLK monitor fault frequency fFAULTLF 2800 4200 8400 Hz MONITOR=1 37
HFXT frequency fHFXT 4 8 MHz HFXTRSEL=00 37
HFXT frequency fHFXT 8.01 16 MHz HFXTRSEL=01 37
HFXT frequency fHFXT 16.01 32 MHz HFXTRSEL=10 37
HFXT frequency fHFXT 32.01 48 MHz HFXTRSEL=11 37
HFXT duty cycle DCHFXT 40 65 % HFXTRSEL=00 37
HFXT duty cycle DCHFXT 40 60 % HFXTRSEL=01 37
HFCLK_IN frequency fHFIN 4 48 MHz USEEXTHFCLK=1 38
HFCLK_IN duty cycle DCHFIN 40 60 % USEEXTHFCLK=1 38
SYSPLL startup time tstart, SYSPLL 14 24 us fSYSPLLREF 32MHz, PDIV=3, QDIV=39, fVCO 160MHz, ±0.5% accuracy 37
High-level input voltage, ODIO VIH 5.5 V ODIO, VDD ≥ 1.62V; printed min is 0.7*VDD 38
High-level input voltage, ODIO VIH 2 5.5 V ODIO, VDD ≥ 2.7V 38
Low-level input voltage, ODIO VIL -0.3 0.8 V ODIO, VDD ≥ 2.7V 38
Low-level input voltage, ODIO VIL -0.3 V ODIO, VDD ≥ 1.62V; printed max is 0.3*VDD 38
Low-level input voltage, all I/O except ODIO and reset VIL -0.3 V VDD ≥ 1.62V; printed max is 0.3*VDD 38
Low-level output voltage, SDIO VOL 0.4 V VDD ≥ 2.7V, /IIO/max = 6mA, -40°C ≤ Ta ≤ 25°C 40
Low-level output voltage, SDIO VOL 0.45 V VDD ≥ 2.7V, /IIO/max = 6mA, -40°C ≤ Ta ≤ 125°C 40
Low-level output voltage, HDIO VOL 0.4 V VDD ≥ 2.7V, DRV=1, /IIO/max = 20mA 40
Low-level output voltage, ODIO VOL 0.4 V VDD ≥ 2.7V, IOL,max = 8mA, -40°C ≤ Ta ≤ 25°C 40
Low-level output voltage, ODIO VOL 0.45 V VDD ≥ 2.7V, IOL,max = 8mA, -40°C ≤ Ta ≤ 125°C 40
Output fall time, ODIO tf 120 ns VDD ≥ 1.71V, FM+, CL = 20pF-100pF; printed min is 20*VDD/5.5 41
ADC analog input voltage range Vin(ADC) 0 V Applies to all ADC analog input pins; printed max is VDD 42
Supply monitor divider (VDD/3) accuracy VSupplyMon -1.5 1.5 % ADC input channel: supply monitor 42
ADC clock frequency fADCCLK 4 48 MHz 42
Integral nonlinearity (INL) EI -2 2 LSB External reference 43
Differential nonlinearity (DNL) ED -1 1 LSB Guaranteed no missing codes, external reference 43
Offset error EO -5 5 mV Internal or external reference 43
Gain error EG -4 4 LSB External reference 43
Factory trim temperature TSTRIM 27 30 33 ℃ ADC/VREF RES=0 (12-bit), VRSEL=0h, VDD=3.3V, ADC tsample=12.5µs 44
Temperature sensor temperature coefficient TSc -2.1 -1.8 -1.7 mV/℃ -40℃ ≤ Tj ≤ 130℃ 44
VREF minimum supply voltage VDDmin 1.62 V BUFCONFIG = 1 44
VREF minimum supply voltage VDDmin 2.7 V BUFCONFIG = 0 44
VREF output voltage VREF 1.38 1.4 1.42 V BUFCONFIG = 1 44
VREF output voltage VREF 2.46 2.5 2.54 V BUFCONFIG = 0 44
VREF operating supply current IVREF 189 330 µA BUFCONFIG = {0, 1}, no load 44
Recommended VREF decoupling capacitor on VREF+ pin CVREF 0.7 1 1.15 µF 44
GPAMP common-mode voltage range VCM -0.1 V RRI = 0x0; printed max is VDD-1 45
GPAMP common-mode voltage range VCM 1 V RRI = 0x1; printed max is VDD-0.2 45
GPAMP open-loop voltage gain (DC) AOL 82 90 107 dB RL = 350kΩ, 0.3V < Vo < VDD-0.3V 45
GPAMP phase margin PM 69 70 72 度 CL = 200pF, RL = 350kΩ 45
GPAMP enable time tEN 12 20 µs ENABLE = 0x0 to 0x1, bandgap on, 0.1%, unity gain 46

CAD (KiCad official)

  • Symbol: MSPM0G1107TRHBR
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: mspm0g1107trhbr-etched.step / mspm0g1107trhbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mspm0g1107trhbr.step / mspm0g1107trhbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (100 pp, sha256 f125d9cbe0fd5b85, retrieved 2026-10-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF