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MSPM0G1106TPTR

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Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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MSPM0G1106TPTR

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)

MSPM0G1106TPTR from Texas Instruments, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PA0 bidirectional 5V-tolerant open-drain GPIO PA0 that can wake the device from SHUTDOWN; alternate functions include UART0_TX, I2C0_SDA, TIMA0_C0 and FCC_IN, and an external pull-up is required for output-high on I2C/UART use.
2 PA1 bidirectional 5V-tolerant open-drain GPIO PA1 that can wake the device from SHUTDOWN; alternate functions include UART0_RX, I2C0_SCL, TIMA0_C1 and TIMG8_C0, and an external pull-up is required for output-high on I2C/UART use.
3 PA28 bidirectional High-drive GPIO PA28 that can wake the device from SHUTDOWN; alternate functions include UART0_TX, I2C0_SDA, TIMA0_C3, TIMG7_C0 and TIMA1_C0.
4 NRST input Active-low reset input that must be pulled up to VDD for the device to start.
5 PA31 bidirectional High-drive GPIO PA31 that can wake the device from SHUTDOWN; alternate functions include UART0_RX, I2C0_SCL, TIMA0_C3N, TIMG12_C1, CLK_OUT, TIMG7_C1 and TIMA1_C1.
6 VDD power_in Power supply pin; the recommended operating range is 1.62 V to 3.6 V, with a 10 µF and 0.1 µF low-ESR ceramic decoupling pair placed within a few millimetres of the pin.
7 VSS power_in Ground pin for the device supply, connected to the system ground.
8 PA2 bidirectional Standard GPIO PA2 that doubles as the ROSC pin; the 100 kΩ ±0.1% ±25ppm reference resistor to VSS is needed only when the SYSOSC frequency-correction loop is used, and otherwise PA2 can be a digital I/O.
9 PA3 bidirectional Standard GPIO PA3 that doubles as the LFXT input (LFXIN) for the 32 kHz crystal; alternate functions include SPI0_CS1, UART2_CTS, I2C1_SDA and TIMA0_C2.
10 PA4 bidirectional Standard GPIO PA4 that doubles as the LFXT output (LFXOUT) and as the LFCLK_IN digital 32 kHz clock input (29491 Hz to 36045 Hz); alternate functions include SPI0_POCI, UART2_RTS and I2C1_SCL.
11 PA5 bidirectional Standard GPIO PA5 that doubles as the HFXT input (HFXIN) for a 4 MHz to 48 MHz crystal; alternate functions include SPI0_PICO, TIMA_FAL1, TIMG0_C0 and FCC_IN.
12 PA6 bidirectional Standard GPIO PA6 that doubles as the HFXT output (HFXOUT) and as the HFCLK_IN digital clock input (4 MHz to 48 MHz); alternate functions include SPI0_SCK, TIMA_FAL0 and TIMG0_C1.
13 PA7 bidirectional Standard GPIO PA7; alternate functions include CLK_OUT, TIMG8_C0, TIMA0_C2, TIMG8_IDX, TIMG7_C1 and TIMA0_C1.
14 PB2 bidirectional Standard GPIO PB2; alternate functions include UART3_TX, UART2_CTS, I2C1_SCL, TIMA0_C3, UART1_CTS and TIMG6_C0.
15 PB3 bidirectional Standard GPIO PB3; alternate functions include UART3_RX, UART2_RTS, I2C1_SDA, TIMA0_C3N, UART1_RTS and TIMG6_C1.
16 PA8 bidirectional Standard GPIO PA8; alternate functions include UART1_TX, SPI0_CS0, UART0_RTS, TIMA0_C0 and TIMA1_C0N.
17 PA9 bidirectional High-speed GPIO PA9; alternate functions include UART1_RX, SPI0_PICO, UART0_CTS, TIMA0_C1, RTC_OUT, TIMA0_C0N and CLK_OUT.
18 PA10 bidirectional High-drive GPIO PA10 that can wake the device from SHUTDOWN; alternate functions include UART0_TX, SPI0_POCI, I2C0_SDA, TIMA1_C0, TIMG12_C0 and CLK_OUT.
19 PA11 bidirectional High-drive GPIO PA11 that can wake the device from SHUTDOWN; alternate functions include UART0_RX, SPI0_SCK, I2C0_SCL, TIMA1_C1 and I2C1_SCL.
20 PB6 bidirectional Standard GPIO PB6; alternate functions include UART1_TX, SPI1_CS0, SPI0_CS1, TIMG8_C0, UART2_CTS, TIMG6_C0 and TIMA1_C0N.
21 PB7 bidirectional Standard GPIO PB7; alternate functions include UART1_RX, SPI1_POCI, SPI0_CS2, TIMG8_C1, UART2_RTS, TIMG6_C1 and TIMA1_C1N.
22 PB8 bidirectional Standard GPIO PB8; alternate functions include UART1_CTS, SPI1_PICO and TIMA0_C0.
23 PB9 bidirectional Standard GPIO PB9; alternate functions include UART1_RTS, SPI1_SCK, TIMA0_C1 and TIMA0_C0N.
24 PB14 bidirectional Standard GPIO PB14; alternate functions include SPI1_CS3, SPI1_POCI, SPI0_CS3, TIMG12_C1, TIMG8_IDX and TIMA0_C0.
25 PB15 bidirectional Standard GPIO PB15; alternate functions include UART2_TX, SPI1_PICO, UART3_CTS, TIMG8_C0 and TIMG7_C0.
26 PB16 bidirectional Standard GPIO PB16; alternate functions include UART2_RX, SPI1_SCK, UART3_RTS, TIMG8_C1 and TIMG7_C1.
27 PA12 bidirectional High-speed GPIO PA12; alternate functions include UART3_CTS, SPI0_SCK, TIMG0_C0, TIMA0_C3 and FCC_IN.
28 PA13 bidirectional High-speed GPIO PA13; alternate functions include UART3_RTS, SPI0_POCI, UART3_RX, TIMG0_C1 and TIMA0_C3N.
29 PA14 bidirectional High-speed GPIO PA14 that doubles as ADC0 analog input A0_12; alternate functions include UART0_CTS, SPI0_PICO, UART3_TX, TIMG12_C0 and CLK_OUT.
30 PA15 bidirectional Standard GPIO PA15 that doubles as ADC1 analog input A1_0; alternate functions include UART0_RTS, SPI1_CS2, I2C1_SCL, TIMA1_C0 and TIMG8_IDX.
31 PA16 bidirectional Standard GPIO PA16 that doubles as ADC1 analog input A1_1; alternate functions include SPI1_POCI, I2C1_SDA, TIMA1_C1, TIMA0_C2N and FCC_IN.
32 PA17 bidirectional Standard GPIO PA17 with wake-from-SHUTDOWN capability that doubles as ADC1 analog input A1_2; alternate functions include UART1_TX, SPI1_SCK, I2C1_SCL, TIMA0_C3, TIMG7_C0 and TIMA1_C0.
33 PA18 bidirectional Standard GPIO PA18 with wake-from-SHUTDOWN capability that doubles as ADC1 analog input A1_3 and GPAMP_IN-; alternate functions include UART1_RX, SPI1_PICO, I2C1_SDA, TIMA0_C3N and TIMA1_C1.
34 PA19 bidirectional High-speed GPIO PA19 used as the serial wire debug data pin SWDIO (bidirectional data input/output).
35 PA20 bidirectional Standard GPIO PA20 used as the serial wire debug clock pin SWCLK (input from the debug probe).
36 PB17 bidirectional Standard GPIO PB17 that doubles as ADC1 analog input A1_4; alternate functions include UART2_TX, SPI0_PICO, SPI1_CS1, TIMA1_C0 and TIMA0_C2.
37 PB18 bidirectional Standard GPIO PB18 that doubles as ADC1 analog input A1_5; alternate functions include UART2_RX, SPI0_SCK, SPI1_CS2, TIMA1_C1 and TIMA0_C2N.
38 PB19 bidirectional Standard GPIO PB19 that doubles as ADC1 analog input A1_6; alternate functions include SPI0_POCI, TIMG8_C1, UART0_CTS and TIMG7_C1.
39 PA21 bidirectional Standard GPIO PA21 that doubles as ADC1 analog input A1_7 and VREF- (external reference ground); alternate functions include UART2_TX, TIMG8_C0, UART1_CTS, TIMA0_C0 and TIMG6_C0.
40 PA22 bidirectional Standard GPIO PA22 that doubles as ADC0 analog input A0_7 and GPAMP_OUT; alternate functions include UART2_RX, TIMG8_C1, UART1_RTS, TIMA0_C1, CLK_OUT and TIMA0_C0N.
41 PB20 bidirectional Standard GPIO PB20 that doubles as ADC0 analog input A0_6; alternate functions include SPI0_CS2, SPI1_CS0, TIMA0_C2, TIMG12_C0 and TIMA_FAL1.
42 PB24 bidirectional Standard GPIO PB24 that doubles as ADC0 analog input A0_5; alternate functions include SPI0_CS3, SPI0_CS1, TIMA0_C3, TIMG12_C1 and TIMA0_C1N.
43 PA23 bidirectional Standard GPIO PA23 that doubles as the VREF+ pin, an external voltage reference input or internal reference output that needs a decoupling capacitor between VREF+ and VREF-/GND; alternate functions include UART2_TX, SPI0_CS3, TIMA0_C3 and TIMG0_C0.
44 PA24 bidirectional Standard GPIO PA24 that doubles as ADC0 analog input A0_3; alternate functions include UART2_RX, SPI0_CS2, TIMA0_C3N, TIMG0_C1 and UART3_RTS.
45 PA25 bidirectional Standard GPIO PA25 that doubles as ADC0 analog input A0_2; alternate functions include UART3_RX, SPI1_CS3, TIMG12_C1, TIMA0_C3 and TIMA0_C1N.
46 PA26 bidirectional Standard GPIO PA26 that doubles as ADC0 analog input A0_1 and GPAMP_IN+; alternate functions include UART3_TX, SPI1_CS0, TIMG8_C0, TIMA_FAL0 and TIMG7_C0.
47 PA27 bidirectional Standard GPIO PA27 that doubles as ADC0 analog input A0_0; alternate functions include RTC_OUT, SPI1_CS1, TIMG8_C1, TIMA_FAL2 and TIMG7_C1.
48 VCORE power_out Regulated core supply output that needs only a 470 nF low-ESR capacitor (±20% or better) placed close to the pin between VCORE and VSS; no voltage or external load may be applied to this pin.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-48(7x7)
Category Embedded Processors & Controllers
Pins 48

CAD (KiCad official)

  • Symbol: MSPM0G1106TPTR
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: mspm0g1106tptr-etched.step / mspm0g1106tptr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mspm0g1106tptr.step / mspm0g1106tptr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (91 pp, sha256 2cddc09fb7f556fb, retrieved 2026-10-11, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF