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MSP432E401YTPDTR

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Texas Instruments Microcontrollers (MCU/MPU/SOC), TQFP-128(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MSP432E401YTPDTR

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · TQFP-128(14x14)

MSP432E401YTPDTR from Texas Instruments, in a TQFP-128(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PD0 bidirectional GPIO port D bit 0, 3.3-V LVCMOS, high-impedance after reset; alternate functions AIN15 (analog), I2C7SCL, T0CCP0, C0o, SSI2XDAT1.
2 PD1 bidirectional GPIO port D bit 1, 3.3-V LVCMOS, high-impedance after reset; alternate functions AIN14 (analog), I2C7SDA, T0CCP1, C1o, SSI2XDAT0.
3 PD2 bidirectional GPIO port D bit 2, 3.3-V LVCMOS, high-impedance after reset; alternate functions AIN13 (analog), C2o, I2C8SCL, SSI2Fss, T1CCP0.
4 PD3 bidirectional GPIO port D bit 3, 3.3-V LVCMOS, high-impedance after reset; alternate functions AIN12 (analog), I2C8SDA, SSI2Clk, T1CCP1.
5 PQ0 bidirectional GPIO port Q bit 0, 3.3-V LVCMOS, high-impedance after reset; alternate functions EPI0S20, SSI3Clk.
6 PQ1 bidirectional GPIO port Q bit 1, 3.3-V LVCMOS; alternate functions EPI0S21, SSI3Fss.
7 VDD power_in Positive supply for I/O and some logic; 2.97 V to 3.63 V (3.3 V nominal).
8 VDDA power_in Positive supply for analog circuits (ADC, analog comparators); 2.97 V to 3.63 V, and must be powered on before VDD if sourced from a different supply.
9 VREFA+ input ADC reference voltage that sets the code-4095 full-scale level; must stay within the ADC electrical specification range and connect to VDDA when unused per Table 4-6.
10 GNDA power_in Ground reference for analog circuits (ADC, analog comparators), kept separate from GND to limit noise on analog functions.
11 PQ2 bidirectional GPIO port Q bit 2, 3.3-V LVCMOS; alternate functions EPI0S22, SSI3XDAT0.
12 PE3 bidirectional GPIO port E bit 3, 3.3-V LVCMOS, high-impedance after reset; alternate functions AIN0 (analog), U1DTR.
13 PE2 bidirectional GPIO port E bit 2, 3.3-V LVCMOS, high-impedance after reset; alternate functions AIN1 (analog), U1DCD.
14 PE1 bidirectional GPIO port E bit 1, 3.3-V LVCMOS, high-impedance after reset; alternate functions AIN2 (analog), U1DSR.
15 PE0 bidirectional GPIO port E bit 0, 3.3-V LVCMOS, high-impedance after reset; alternate functions AIN3 (analog), U1RTS.
16 VDD power_in Positive supply for I/O and some logic; 2.97 V to 3.63 V (3.3 V nominal).
17 GND power_in Ground reference for logic and I/O pins.
18 PK0 bidirectional GPIO port K bit 0, 3.3-V LVCMOS; alternate functions AIN16 (analog), EPI0S0, U4Rx.
19 PK1 bidirectional GPIO port K bit 1, 3.3-V LVCMOS; alternate functions AIN17 (analog), EPI0S1, U4Tx.
20 PK2 bidirectional GPIO port K bit 2, 3.3-V LVCMOS; alternate functions AIN18 (analog), EPI0S2, U4RTS.
21 PK3 bidirectional GPIO port K bit 3, 3.3-V LVCMOS; alternate functions AIN19 (analog), EPI0S3, U4CTS.
22 PC7 bidirectional GPIO port C bit 7, 3.3-V LVCMOS; alternate functions C0- (analog comparator 0 negative input), EPI0S4, U5Tx.
23 PC6 bidirectional GPIO port C bit 6, 3.3-V LVCMOS; alternate functions C0+ (analog comparator 0 positive input), EPI0S5, U5Rx.
24 PC5 bidirectional GPIO port C bit 5, 3.3-V LVCMOS; alternate functions C1+ (analog comparator 1 positive input), EPI0S6, U7Tx, RTCCLK.
25 PC4 bidirectional GPIO port C bit 4, 3.3-V LVCMOS; alternate functions C1- (analog comparator 1 negative input), EPI0S7, U7Rx.
26 VDD power_in Positive supply for I/O and some logic; 2.97 V to 3.63 V (3.3 V nominal).
27 PQ3 bidirectional GPIO port Q bit 3, 3.3-V LVCMOS; alternate functions EPI0S23, SSI3XDAT1.
28 VDD power_in Positive supply for I/O and some logic; 2.97 V to 3.63 V (3.3 V nominal).
29 PH0 bidirectional GPIO port H bit 0, 3.3-V LVCMOS; alternate function U0RTS (UART0 request to send).
30 PH1 bidirectional GPIO port H bit 1, 3.3-V LVCMOS; alternate function U0CTS (UART0 clear to send).
31 PH2 bidirectional GPIO port H bit 2, 3.3-V LVCMOS; alternate function U0DCD (UART0 data carrier detect).
32 PH3 bidirectional GPIO port H bit 3, 3.3-V LVCMOS; alternate function U0DSR (UART0 data set ready).
33 PA0 bidirectional GPIO port A bit 0, 3.3-V LVCMOS; alternate functions U0Rx, I2C9SCL, T0CCP0, CAN0Rx.
34 PA1 bidirectional GPIO port A bit 1, 3.3-V LVCMOS; alternate functions U0Tx, I2C9SDA, T0CCP1, CAN0Tx; the ROM bootloader may drive it as an output if no flash code is present and PA0 receives a valid boot signature, so do not tie it directly to GND.
35 PA2 bidirectional GPIO port A bit 2, 3.3-V LVCMOS; alternate functions U4Rx, I2C8SCL, T1CCP0, SSI0Clk.
36 PA3 bidirectional GPIO port A bit 3, 3.3-V LVCMOS; alternate functions U4Tx, I2C8SDA, T1CCP1, SSI0Fss.
37 PA4 bidirectional GPIO port A bit 4, 3.3-V LVCMOS; alternate functions U3Rx, I2C7SCL, T2CCP0, SSI0XDAT0; the ROM bootloader may enable it as an output, so do not tie it directly to GND.
38 PA5 bidirectional GPIO port A bit 5, 3.3-V LVCMOS; alternate functions U3Tx, I2C7SDA, T2CCP1, SSI0XDAT1.
39 VDD power_in Positive supply for I/O and some logic; 2.97 V to 3.63 V (3.3 V nominal).
40 PA6 bidirectional GPIO port A bit 6, 3.3-V LVCMOS; alternate functions U2Rx, I2C6SCL, T3CCP0, USB0EPEN, SSI0XDAT2, EPI0S8.
41 PA7 bidirectional GPIO port A bit 7, 3.3-V LVCMOS; alternate functions U2Tx, I2C6SDA, T3CCP1, USB0PFLT, USB0EPEN, SSI0XDAT3, EPI0S9.
42 PF0 bidirectional GPIO port F bit 0, 3.3-V LVCMOS; alternate functions M0PWM0, TRD2, EN0LED0, SSI3XDAT1.
43 PF1 bidirectional GPIO port F bit 1, 3.3-V LVCMOS; alternate functions M0PWM1, TRD1, EN0LED2, SSI3XDAT0.
44 PF2 bidirectional GPIO port F bit 2, 3.3-V LVCMOS; alternate functions M0PWM2, TRD0, SSI3Fss.
45 PF3 bidirectional GPIO port F bit 3, 3.3-V LVCMOS; alternate functions M0PWM3, TRCLK, SSI3Clk.
46 PF4 bidirectional GPIO port F bit 4, 3.3-V LVCMOS; alternate functions M0FAULT0, TRD3, EN0LED1, SSI3XDAT2.
47 VDD power_in Positive supply for I/O and some logic; 2.97 V to 3.63 V (3.3 V nominal).
48 GND power_in Ground reference for logic and I/O pins.
49 PG0 bidirectional GPIO port G bit 0, 3.3-V LVCMOS; alternate functions I2C1SCL, M0PWM4, EN0PPS, EPI0S11.
50 PG1 bidirectional GPIO port G bit 1, 3.3-V LVCMOS; alternate functions I2C1SDA, M0PWM5, EPI0S10.
51 VDD power_in Positive supply for I/O and some logic; 2.97 V to 3.63 V (3.3 V nominal).
52 VDD power_in Positive supply for I/O and some logic; 2.97 V to 3.63 V (3.3 V nominal).
53 EN0RXIN bidirectional Ethernet PHY negative receive differential input; leave unconnected (NC) when Ethernet is unused.
54 EN0RXIP bidirectional Ethernet PHY positive receive differential input; leave unconnected (NC) when Ethernet is unused.
55 GND power_in Ground reference for logic and I/O pins.
56 EN0TXON bidirectional Ethernet PHY negative transmit differential output; leave unconnected (NC) when Ethernet is unused.
57 EN0TXOP bidirectional Ethernet PHY positive transmit differential output; leave unconnected (NC) when Ethernet is unused.
58 GND power_in Ground reference for logic and I/O pins.
59 RBIAS passive Ethernet PHY bias: connect to ground through a 4.87-kΩ, 1% precision resistor.
60 PK7 bidirectional GPIO port K bit 7, 3.3-V LVCMOS; alternate functions EPI0S24, I2C4SDA, M0FAULT2, RTCCLK, U0RI.
61 PK6 bidirectional GPIO port K bit 6, 3.3-V LVCMOS; alternate functions EPI0S25, I2C4SCL, M0FAULT1, EN0LED1.
62 PK5 bidirectional GPIO port K bit 5, 3.3-V LVCMOS; alternate functions EPI0S31, I2C3SDA, M0PWM7, EN0LED2.
63 PK4 bidirectional GPIO port K bit 4, 3.3-V LVCMOS; alternate functions EPI0S32, I2C3SCL, M0PWM6, EN0LED0.
64 WAKE input External input that brings the processor out of Hibernate mode when asserted; GND is the preferred connection when unused.
65 HIB output Output indicating the processor is in Hibernate mode; leave unconnected (NC) when unused.
66 XOSC0 input Hibernation oscillator crystal input or 32.768-kHz external clock reference; GND is the preferred connection when unused.
67 XOSC1 output Hibernation oscillator crystal output; leave unconnected when using a single-ended clock source.
68 VBAT power_in Battery backup and power source for the Hibernation module, absolute maximum 0 V to 4 V; VDD is the preferred connection when Hibernation is unused.
69 VDD power_in Positive supply for I/O and some logic; 2.97 V to 3.63 V (3.3 V nominal).
70 RST input System reset input; pull up to VDD through a 0 to 100-kΩ resistor per Table 4-6.
71 PM7 bidirectional GPIO port M bit 7, fast pad supporting only 2-, 4-, 6- and 8-mA drive; alternate functions T5CCP1, U0RI, TMPR0.
72 PM6 bidirectional GPIO port M bit 6, fast pad supporting only 2-, 4-, 6- and 8-mA drive; alternate functions T5CCP0, U0DSR, TMPR1.
73 PM5 bidirectional GPIO port M bit 5, fast pad supporting only 2-, 4-, 6- and 8-mA drive; alternate functions T4CCP1, U0DCD, TMPR2.
74 PM4 bidirectional GPIO port M bit 4, fast pad supporting only 2-, 4-, 6- and 8-mA drive; alternate functions T4CCP0, U0CTS, TMPR3.
75 PM3 bidirectional GPIO port M bit 3, 3.3-V LVCMOS; alternate functions EPI0S12, T3CCP1.
76 PM2 bidirectional GPIO port M bit 2, 3.3-V LVCMOS; alternate functions EPI0S13, T3CCP0.
77 PM1 bidirectional GPIO port M bit 1, 3.3-V LVCMOS; alternate functions EPI0S14, T2CCP1.
78 PM0 bidirectional GPIO port M bit 0, 3.3-V LVCMOS; alternate functions EPI0S15, T2CCP0.
79 VDD power_in Positive supply for I/O and some logic; 2.97 V to 3.63 V (3.3 V nominal).
80 GND power_in Ground reference for logic and I/O pins.
81 PL0 bidirectional GPIO port L bit 0, 3.3-V LVCMOS; alternate functions I2C2SDA, USB0D0, EPI0S16, M0FAULT3.
82 PL1 bidirectional GPIO port L bit 1, 3.3-V LVCMOS; alternate functions I2C2SCL, USB0D1, EPI0S17, PhA0.
83 PL2 bidirectional GPIO port L bit 2, 3.3-V LVCMOS; alternate functions C0o, USB0D2, EPI0S18, PhB0.
84 PL3 bidirectional GPIO port L bit 3, 3.3-V LVCMOS; alternate functions C1o, USB0D3, EPI0S19, IDX0.
85 PL4 bidirectional GPIO port L bit 4, 3.3-V LVCMOS; alternate functions T0CCP0, USB0D4, EPI0S26.
86 PL5 bidirectional GPIO port L bit 5, 3.3-V LVCMOS; alternate functions T0CCP1, USB0D5, EPI0S33.
87 VDDC power_out Core logic supply generated by the on-chip LDO at 1.2 V (1.14 V to 1.32 V in run mode); connect only to the other VDDC pins and the external capacitor specified in the LDO characteristics.
88 OSC0 input Main oscillator crystal input or external clock reference; GND is the preferred connection when unused.
89 OSC1 output Main oscillator crystal output; leave unconnected when using a single-ended clock source.
90 VDD power_in Positive supply for I/O and some logic; 2.97 V to 3.63 V (3.3 V nominal).
91 PB2 bidirectional GPIO port B bit 2, 3.3-V LVCMOS; alternate functions I2C0SCL, T5CCP0, USB0STP, EPI0S27.
92 PB3 bidirectional GPIO port B bit 3, 3.3-V LVCMOS; alternate functions I2C0SDA, T5CCP1, USB0CLK, EPI0S28.
93 PL7 bidirectional GPIO port L bit 7 (fast pad, 4-mA drive only), also USB0DM; unused pins should be pulled down to GND through 1 kΩ per Table 4-6; alternate function T1CCP1.
94 PL6 bidirectional GPIO port L bit 6 (fast pad, 4-mA drive only), also USB0DP; unused pins should be pulled down to GND through 1 kΩ per Table 4-6; alternate function T1CCP0.
95 PB0 bidirectional GPIO port B bit 0, 3.3-V LVCMOS; alternate functions USB0ID, U1Rx, I2C5SCL, T4CCP0, CAN1Rx.
96 PB1 bidirectional GPIO port B bit 1, 3.3-V LVCMOS; alternate functions USB0VBUS, U1Tx, I2C5SDA, T4CCP1, CAN1Tx.
97 PC3 bidirectional GPIO port C bit 3, 3.3-V LVCMOS; default function JTAG TDO/SWO.
98 PC2 bidirectional GPIO port C bit 2, 3.3-V LVCMOS; default function JTAG TDI.
99 PC1 bidirectional GPIO port C bit 1, 3.3-V LVCMOS; default function JTAG TMS/SWDIO.
100 PC0 bidirectional GPIO port C bit 0, 3.3-V LVCMOS; default function JTAG TCK/SWCLK.
101 VDD power_in Positive supply for I/O and some logic; 2.97 V to 3.63 V (3.3 V nominal).
102 PQ4 bidirectional GPIO port Q bit 4, 3.3-V LVCMOS; alternate functions DIVSCLK (optionally divided reference clock output), U1Rx.
103 PP2 bidirectional GPIO port P bit 2, 3.3-V LVCMOS; alternate functions EPI0S29, U0DTR, USB0NXT.
104 PP3 bidirectional GPIO port P bit 3, 3.3-V LVCMOS; alternate functions EPI0S30, U0DCD, U1CTS, USB0DIR, RTCCLK.
105 PP4 bidirectional GPIO port P bit 4, 3.3-V LVCMOS; alternate functions U0DSR, U3RTS, USB0D7.
106 PP5 bidirectional GPIO port P bit 5, 3.3-V LVCMOS; alternate functions U3CTS, I2C2SCL, USB0D6.
107 PN0 bidirectional GPIO port N bit 0, 3.3-V LVCMOS; alternate function U1RTS.
108 PN1 bidirectional GPIO port N bit 1, 3.3-V LVCMOS; alternate function U1CTS.
109 PN2 bidirectional GPIO port N bit 2, 3.3-V LVCMOS; alternate functions EPI0S29, U1DCD, U2RTS.
110 PN3 bidirectional GPIO port N bit 3, 3.3-V LVCMOS; alternate functions EPI0S30, U1DSR, U2CTS.
111 PN4 bidirectional GPIO port N bit 4, 3.3-V LVCMOS; alternate functions EPI0S34, I2C2SDA, U3RTS, U1DTR.
112 PN5 bidirectional GPIO port N bit 5, 3.3-V LVCMOS; alternate functions EPI0S35, I2C2SCL, U3CTS, U1RI.
113 VDD power_in Positive supply for I/O and some logic; 2.97 V to 3.63 V (3.3 V nominal).
114 GND power_in Ground reference for logic and I/O pins.
115 VDDC power_out Core logic supply generated by the on-chip LDO at 1.2 V (1.14 V to 1.32 V in run mode); connect only to the other VDDC pins and the external capacitor specified in the LDO characteristics.
116 PJ0 bidirectional GPIO port J bit 0, 3.3-V LVCMOS; alternate functions EN0PPS, U3Rx.
117 PJ1 bidirectional GPIO port J bit 1, slow GPIO pad with 2-mA drive; alternate function U3Tx.
118 PP0 bidirectional GPIO port P bit 0, 3.3-V LVCMOS; alternate functions SSI3XDAT2, U6Rx, C2+ (analog comparator 2 positive input).
119 PP1 bidirectional GPIO port P bit 1, 3.3-V LVCMOS; alternate functions SSI3XDAT3, U6Tx, C2- (analog comparator 2 negative input).
120 PB5 bidirectional GPIO port B bit 5, 3.3-V LVCMOS; alternate functions AIN11 (analog), U0RTS, I2C5SDA, SSI1Clk.
121 PB4 bidirectional GPIO port B bit 4, 3.3-V LVCMOS, high-impedance after reset; alternate functions AIN10 (analog), I2C5SCL, SSI1Fss, U0CTS.
122 VDD power_in Positive supply for I/O and some logic; 2.97 V to 3.63 V (3.3 V nominal).
123 PE4 bidirectional GPIO port E bit 4, 3.3-V LVCMOS, high-impedance after reset; alternate functions AIN9 (analog), SSI1XDAT0, U1RI.
124 PE5 bidirectional GPIO port E bit 5, 3.3-V LVCMOS, high-impedance after reset; alternate functions AIN8 (analog), SSI1XDAT1.
125 PD4 bidirectional GPIO port D bit 4, 3.3-V LVCMOS, high-impedance after reset; alternate functions AIN7 (analog), SSI1XDAT2, T3CCP0, U2Rx.
126 PD5 bidirectional GPIO port D bit 5, 3.3-V LVCMOS, high-impedance after reset; alternate functions AIN6 (analog), SSI1XDAT3, T3CCP1, U2Tx.
127 PD6 bidirectional GPIO port D bit 6, 3.3-V LVCMOS, high-impedance after reset; alternate functions AIN5 (analog), SSI2XDAT3, T4CCP0, U2RTS, USB0EPEN.
128 PD7 bidirectional GPIO port D bit 7, 3.3-V LVCMOS, high-impedance after reset; alternate functions AIN4 (analog), NMI, SSI2XDAT2, T4CCP1, U2CTS, USB0PFLT.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TQFP-128(14x14)
Category Embedded Processors & Controllers
Pins 128

CAD (KiCad official)

  • Symbol: MSP432E401YTPDTR
  • Footprint: Package_QFP:TQFP-128_14x14mm_P0.4mm
  • 3D model: TQFP-128(14x14) (KiCad packages3D, STEP)
  • 3D model files: msp432e401ytpdtr-etched.step / msp432e401ytpdtr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); msp432e401ytpdtr.step / msp432e401ytpdtr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (157 pp, sha256 67cd8a2b4daa368b, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF