component
MSP432E401YTPDTR
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), TQFP-128(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+165@@ -0,0 +1,165 @@+# MSP432E401YTPDTR++**Texas Instruments** · Microcontrollers (MCU/MPU/SOC) · TQFP-128(14x14)++MSP432E401YTPDTR from Texas Instruments, in a TQFP-128(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | PD0 | bidirectional | GPIO port D bit 0, 3.3-V LVCMOS, high-impedance after reset; alternate functions AIN15 (analog), I2C7SCL, T0CCP0, C0o, SSI2XDAT1. |+| 2 | PD1 | bidirectional | GPIO port D bit 1, 3.3-V LVCMOS, high-impedance after reset; alternate functions AIN14 (analog), I2C7SDA, T0CCP1, C1o, SSI2XDAT0. |+| 3 | PD2 | bidirectional | GPIO port D bit 2, 3.3-V LVCMOS, high-impedance after reset; alternate functions AIN13 (analog), C2o, I2C8SCL, SSI2Fss, T1CCP0. |+| 4 | PD3 | bidirectional | GPIO port D bit 3, 3.3-V LVCMOS, high-impedance after reset; alternate functions AIN12 (analog), I2C8SDA, SSI2Clk, T1CCP1. |+| 5 | PQ0 | bidirectional | GPIO port Q bit 0, 3.3-V LVCMOS, high-impedance after reset; alternate functions EPI0S20, SSI3Clk. |+| 6 | PQ1 | bidirectional | GPIO port Q bit 1, 3.3-V LVCMOS; alternate functions EPI0S21, SSI3Fss. |+| 7 | VDD | power_in | Positive supply for I/O and some logic; 2.97 V to 3.63 V (3.3 V nominal). |+| 8 | VDDA | power_in | Positive supply for analog circuits (ADC, analog comparators); 2.97 V to 3.63 V, and must be powered on before VDD if sourced from a different supply. |+| 9 | VREFA+ | input | ADC reference voltage that sets the code-4095 full-scale level; must stay within the ADC electrical specification range and connect to VDDA when unused per Table 4-6. |+| 10 | GNDA | power_in | Ground reference for analog circuits (ADC, analog comparators), kept separate from GND to limit noise on analog functions. |+| 11 | PQ2 | bidirectional | GPIO port Q bit 2, 3.3-V LVCMOS; alternate functions EPI0S22, SSI3XDAT0. |+| 12 | PE3 | bidirectional | GPIO port E bit 3, 3.3-V LVCMOS, high-impedance after reset; alternate functions AIN0 (analog), U1DTR. |+| 13 | PE2 | bidirectional | GPIO port E bit 2, 3.3-V LVCMOS, high-impedance after reset; alternate functions AIN1 (analog), U1DCD. |+| 14 | PE1 | bidirectional | GPIO port E bit 1, 3.3-V LVCMOS, high-impedance after reset; alternate functions AIN2 (analog), U1DSR. |+| 15 | PE0 | bidirectional | GPIO port E bit 0, 3.3-V LVCMOS, high-impedance after reset; alternate functions AIN3 (analog), U1RTS. |+| 16 | VDD | power_in | Positive supply for I/O and some logic; 2.97 V to 3.63 V (3.3 V nominal). |+| 17 | GND | power_in | Ground reference for logic and I/O pins. |+| 18 | PK0 | bidirectional | GPIO port K bit 0, 3.3-V LVCMOS; alternate functions AIN16 (analog), EPI0S0, U4Rx. |+| 19 | PK1 | bidirectional | GPIO port K bit 1, 3.3-V LVCMOS; alternate functions AIN17 (analog), EPI0S1, U4Tx. |+| 20 | PK2 | bidirectional | GPIO port K bit 2, 3.3-V LVCMOS; alternate functions AIN18 (analog), EPI0S2, U4RTS. |+| 21 | PK3 | bidirectional | GPIO port K bit 3, 3.3-V LVCMOS; alternate functions AIN19 (analog), EPI0S3, U4CTS. |+| 22 | PC7 | bidirectional | GPIO port C bit 7, 3.3-V LVCMOS; alternate functions C0- (analog comparator 0 negative input), EPI0S4, U5Tx. |+| 23 | PC6 | bidirectional | GPIO port C bit 6, 3.3-V LVCMOS; alternate functions C0+ (analog comparator 0 positive input), EPI0S5, U5Rx. |+| 24 | PC5 | bidirectional | GPIO port C bit 5, 3.3-V LVCMOS; alternate functions C1+ (analog comparator 1 positive input), EPI0S6, U7Tx, RTCCLK. |+| 25 | PC4 | bidirectional | GPIO port C bit 4, 3.3-V LVCMOS; alternate functions C1- (analog comparator 1 negative input), EPI0S7, U7Rx. |+| 26 | VDD | power_in | Positive supply for I/O and some logic; 2.97 V to 3.63 V (3.3 V nominal). |+| 27 | PQ3 | bidirectional | GPIO port Q bit 3, 3.3-V LVCMOS; alternate functions EPI0S23, SSI3XDAT1. |+| 28 | VDD | power_in | Positive supply for I/O and some logic; 2.97 V to 3.63 V (3.3 V nominal). |+| 29 | PH0 | bidirectional | GPIO port H bit 0, 3.3-V LVCMOS; alternate function U0RTS (UART0 request to send). |+| 30 | PH1 | bidirectional | GPIO port H bit 1, 3.3-V LVCMOS; alternate function U0CTS (UART0 clear to send). |+| 31 | PH2 | bidirectional | GPIO port H bit 2, 3.3-V LVCMOS; alternate function U0DCD (UART0 data carrier detect). |+| 32 | PH3 | bidirectional | GPIO port H bit 3, 3.3-V LVCMOS; alternate function U0DSR (UART0 data set ready). |+| 33 | PA0 | bidirectional | GPIO port A bit 0, 3.3-V LVCMOS; alternate functions U0Rx, I2C9SCL, T0CCP0, CAN0Rx. |+| 34 | PA1 | bidirectional | GPIO port A bit 1, 3.3-V LVCMOS; alternate functions U0Tx, I2C9SDA, T0CCP1, CAN0Tx; the ROM bootloader may drive it as an output if no flash code is present and PA0 receives a valid boot signature, so do not tie it directly to GND. |+| 35 | PA2 | bidirectional | GPIO port A bit 2, 3.3-V LVCMOS; alternate functions U4Rx, I2C8SCL, T1CCP0, SSI0Clk. |+| 36 | PA3 | bidirectional | GPIO port A bit 3, 3.3-V LVCMOS; alternate functions U4Tx, I2C8SDA, T1CCP1, SSI0Fss. |+| 37 | PA4 | bidirectional | GPIO port A bit 4, 3.3-V LVCMOS; alternate functions U3Rx, I2C7SCL, T2CCP0, SSI0XDAT0; the ROM bootloader may enable it as an output, so do not tie it directly to GND. |+| 38 | PA5 | bidirectional | GPIO port A bit 5, 3.3-V LVCMOS; alternate functions U3Tx, I2C7SDA, T2CCP1, SSI0XDAT1. |+| 39 | VDD | power_in | Positive supply for I/O and some logic; 2.97 V to 3.63 V (3.3 V nominal). |+| 40 | PA6 | bidirectional | GPIO port A bit 6, 3.3-V LVCMOS; alternate functions U2Rx, I2C6SCL, T3CCP0, USB0EPEN, SSI0XDAT2, EPI0S8. |+| 41 | PA7 | bidirectional | GPIO port A bit 7, 3.3-V LVCMOS; alternate functions U2Tx, I2C6SDA, T3CCP1, USB0PFLT, USB0EPEN, SSI0XDAT3, EPI0S9. |+| 42 | PF0 | bidirectional | GPIO port F bit 0, 3.3-V LVCMOS; alternate functions M0PWM0, TRD2, EN0LED0, SSI3XDAT1. |+| 43 | PF1 | bidirectional | GPIO port F bit 1, 3.3-V LVCMOS; alternate functions M0PWM1, TRD1, EN0LED2, SSI3XDAT0. |+| 44 | PF2 | bidirectional | GPIO port F bit 2, 3.3-V LVCMOS; alternate functions M0PWM2, TRD0, SSI3Fss. |+| 45 | PF3 | bidirectional | GPIO port F bit 3, 3.3-V LVCMOS; alternate functions M0PWM3, TRCLK, SSI3Clk. |+| 46 | PF4 | bidirectional | GPIO port F bit 4, 3.3-V LVCMOS; alternate functions M0FAULT0, TRD3, EN0LED1, SSI3XDAT2. |+| 47 | VDD | power_in | Positive supply for I/O and some logic; 2.97 V to 3.63 V (3.3 V nominal). |+| 48 | GND | power_in | Ground reference for logic and I/O pins. |+| 49 | PG0 | bidirectional | GPIO port G bit 0, 3.3-V LVCMOS; alternate functions I2C1SCL, M0PWM4, EN0PPS, EPI0S11. |+| 50 | PG1 | bidirectional | GPIO port G bit 1, 3.3-V LVCMOS; alternate functions I2C1SDA, M0PWM5, EPI0S10. |+| 51 | VDD | power_in | Positive supply for I/O and some logic; 2.97 V to 3.63 V (3.3 V nominal). |+| 52 | VDD | power_in | Positive supply for I/O and some logic; 2.97 V to 3.63 V (3.3 V nominal). |+| 53 | EN0RXIN | bidirectional | Ethernet PHY negative receive differential input; leave unconnected (NC) when Ethernet is unused. |+| 54 | EN0RXIP | bidirectional | Ethernet PHY positive receive differential input; leave unconnected (NC) when Ethernet is unused. |+| 55 | GND | power_in | Ground reference for logic and I/O pins. |+| 56 | EN0TXON | bidirectional | Ethernet PHY negative transmit differential output; leave unconnected (NC) when Ethernet is unused. |+| 57 | EN0TXOP | bidirectional | Ethernet PHY positive transmit differential output; leave unconnected (NC) when Ethernet is unused. |+| 58 | GND | power_in | Ground reference for logic and I/O pins. |+| 59 | RBIAS | passive | Ethernet PHY bias: connect to ground through a 4.87-kΩ, 1% precision resistor. |+| 60 | PK7 | bidirectional | GPIO port K bit 7, 3.3-V LVCMOS; alternate functions EPI0S24, I2C4SDA, M0FAULT2, RTCCLK, U0RI. |+| 61 | PK6 | bidirectional | GPIO port K bit 6, 3.3-V LVCMOS; alternate functions EPI0S25, I2C4SCL, M0FAULT1, EN0LED1. |+| 62 | PK5 | bidirectional | GPIO port K bit 5, 3.3-V LVCMOS; alternate functions EPI0S31, I2C3SDA, M0PWM7, EN0LED2. |+| 63 | PK4 | bidirectional | GPIO port K bit 4, 3.3-V LVCMOS; alternate functions EPI0S32, I2C3SCL, M0PWM6, EN0LED0. |+| 64 | WAKE | input | External input that brings the processor out of Hibernate mode when asserted; GND is the preferred connection when unused. |+| 65 | HIB | output | Output indicating the processor is in Hibernate mode; leave unconnected (NC) when unused. |+| 66 | XOSC0 | input | Hibernation oscillator crystal input or 32.768-kHz external clock reference; GND is the preferred connection when unused. |+| 67 | XOSC1 | output | Hibernation oscillator crystal output; leave unconnected when using a single-ended clock source. |+| 68 | VBAT | power_in | Battery backup and power source for the Hibernation module, absolute maximum 0 V to 4 V; VDD is the preferred connection when Hibernation is unused. |+| 69 | VDD | power_in | Positive supply for I/O and some logic; 2.97 V to 3.63 V (3.3 V nominal). |+| 70 | RST | input | System reset input; pull up to VDD through a 0 to 100-kΩ resistor per Table 4-6. |+| 71 | PM7 | bidirectional | GPIO port M bit 7, fast pad supporting only 2-, 4-, 6- and 8-mA drive; alternate functions T5CCP1, U0RI, TMPR0. |+| 72 | PM6 | bidirectional | GPIO port M bit 6, fast pad supporting only 2-, 4-, 6- and 8-mA drive; alternate functions T5CCP0, U0DSR, TMPR1. |+| 73 | PM5 | bidirectional | GPIO port M bit 5, fast pad supporting only 2-, 4-, 6- and 8-mA drive; alternate functions T4CCP1, U0DCD, TMPR2. |+| 74 | PM4 | bidirectional | GPIO port M bit 4, fast pad supporting only 2-, 4-, 6- and 8-mA drive; alternate functions T4CCP0, U0CTS, TMPR3. |+| 75 | PM3 | bidirectional | GPIO port M bit 3, 3.3-V LVCMOS; alternate functions EPI0S12, T3CCP1. |+| 76 | PM2 | bidirectional | GPIO port M bit 2, 3.3-V LVCMOS; alternate functions EPI0S13, T3CCP0. |+| 77 | PM1 | bidirectional | GPIO port M bit 1, 3.3-V LVCMOS; alternate functions EPI0S14, T2CCP1. |+| 78 | PM0 | bidirectional | GPIO port M bit 0, 3.3-V LVCMOS; alternate functions EPI0S15, T2CCP0. |+| 79 | VDD | power_in | Positive supply for I/O and some logic; 2.97 V to 3.63 V (3.3 V nominal). |+| 80 | GND | power_in | Ground reference for logic and I/O pins. |+| 81 | PL0 | bidirectional | GPIO port L bit 0, 3.3-V LVCMOS; alternate functions I2C2SDA, USB0D0, EPI0S16, M0FAULT3. |+| 82 | PL1 | bidirectional | GPIO port L bit 1, 3.3-V LVCMOS; alternate functions I2C2SCL, USB0D1, EPI0S17, PhA0. |+| 83 | PL2 | bidirectional | GPIO port L bit 2, 3.3-V LVCMOS; alternate functions C0o, USB0D2, EPI0S18, PhB0. |+| 84 | PL3 | bidirectional | GPIO port L bit 3, 3.3-V LVCMOS; alternate functions C1o, USB0D3, EPI0S19, IDX0. |+| 85 | PL4 | bidirectional | GPIO port L bit 4, 3.3-V LVCMOS; alternate functions T0CCP0, USB0D4, EPI0S26. |+| 86 | PL5 | bidirectional | GPIO port L bit 5, 3.3-V LVCMOS; alternate functions T0CCP1, USB0D5, EPI0S33. |+| 87 | VDDC | power_out | Core logic supply generated by the on-chip LDO at 1.2 V (1.14 V to 1.32 V in run mode); connect only to the other VDDC pins and the external capacitor specified in the LDO characteristics. |+| 88 | OSC0 | input | Main oscillator crystal input or external clock reference; GND is the preferred connection when unused. |+| 89 | OSC1 | output | Main oscillator crystal output; leave unconnected when using a single-ended clock source. |+| 90 | VDD | power_in | Positive supply for I/O and some logic; 2.97 V to 3.63 V (3.3 V nominal). |+| 91 | PB2 | bidirectional | GPIO port B bit 2, 3.3-V LVCMOS; alternate functions I2C0SCL, T5CCP0, USB0STP, EPI0S27. |+| 92 | PB3 | bidirectional | GPIO port B bit 3, 3.3-V LVCMOS; alternate functions I2C0SDA, T5CCP1, USB0CLK, EPI0S28. |+| 93 | PL7 | bidirectional | GPIO port L bit 7 (fast pad, 4-mA drive only), also USB0DM; unused pins should be pulled down to GND through 1 kΩ per Table 4-6; alternate function T1CCP1. |+| 94 | PL6 | bidirectional | GPIO port L bit 6 (fast pad, 4-mA drive only), also USB0DP; unused pins should be pulled down to GND through 1 kΩ per Table 4-6; alternate function T1CCP0. |+| 95 | PB0 | bidirectional | GPIO port B bit 0, 3.3-V LVCMOS; alternate functions USB0ID, U1Rx, I2C5SCL, T4CCP0, CAN1Rx. |+| 96 | PB1 | bidirectional | GPIO port B bit 1, 3.3-V LVCMOS; alternate functions USB0VBUS, U1Tx, I2C5SDA, T4CCP1, CAN1Tx. |+| 97 | PC3 | bidirectional | GPIO port C bit 3, 3.3-V LVCMOS; default function JTAG TDO/SWO. |+| 98 | PC2 | bidirectional | GPIO port C bit 2, 3.3-V LVCMOS; default function JTAG TDI. |+| 99 | PC1 | bidirectional | GPIO port C bit 1, 3.3-V LVCMOS; default function JTAG TMS/SWDIO. |+| 100 | PC0 | bidirectional | GPIO port C bit 0, 3.3-V LVCMOS; default function JTAG TCK/SWCLK. |+| 101 | VDD | power_in | Positive supply for I/O and some logic; 2.97 V to 3.63 V (3.3 V nominal). |+| 102 | PQ4 | bidirectional | GPIO port Q bit 4, 3.3-V LVCMOS; alternate functions DIVSCLK (optionally divided reference clock output), U1Rx. |+| 103 | PP2 | bidirectional | GPIO port P bit 2, 3.3-V LVCMOS; alternate functions EPI0S29, U0DTR, USB0NXT. |+| 104 | PP3 | bidirectional | GPIO port P bit 3, 3.3-V LVCMOS; alternate functions EPI0S30, U0DCD, U1CTS, USB0DIR, RTCCLK. |+| 105 | PP4 | bidirectional | GPIO port P bit 4, 3.3-V LVCMOS; alternate functions U0DSR, U3RTS, USB0D7. |+| 106 | PP5 | bidirectional | GPIO port P bit 5, 3.3-V LVCMOS; alternate functions U3CTS, I2C2SCL, USB0D6. |+| 107 | PN0 | bidirectional | GPIO port N bit 0, 3.3-V LVCMOS; alternate function U1RTS. |+| 108 | PN1 | bidirectional | GPIO port N bit 1, 3.3-V LVCMOS; alternate function U1CTS. |+| 109 | PN2 | bidirectional | GPIO port N bit 2, 3.3-V LVCMOS; alternate functions EPI0S29, U1DCD, U2RTS. |+| 110 | PN3 | bidirectional | GPIO port N bit 3, 3.3-V LVCMOS; alternate functions EPI0S30, U1DSR, U2CTS. |+| 111 | PN4 | bidirectional | GPIO port N bit 4, 3.3-V LVCMOS; alternate functions EPI0S34, I2C2SDA, U3RTS, U1DTR. |+| 112 | PN5 | bidirectional | GPIO port N bit 5, 3.3-V LVCMOS; alternate functions EPI0S35, I2C2SCL, U3CTS, U1RI. |+| 113 | VDD | power_in | Positive supply for I/O and some logic; 2.97 V to 3.63 V (3.3 V nominal). |+| 114 | GND | power_in | Ground reference for logic and I/O pins. |+| 115 | VDDC | power_out | Core logic supply generated by the on-chip LDO at 1.2 V (1.14 V to 1.32 V in run mode); connect only to the other VDDC pins and the external capacitor specified in the LDO characteristics. |+| 116 | PJ0 | bidirectional | GPIO port J bit 0, 3.3-V LVCMOS; alternate functions EN0PPS, U3Rx. |+| 117 | PJ1 | bidirectional | GPIO port J bit 1, slow GPIO pad with 2-mA drive; alternate function U3Tx. |+| 118 | PP0 | bidirectional | GPIO port P bit 0, 3.3-V LVCMOS; alternate functions SSI3XDAT2, U6Rx, C2+ (analog comparator 2 positive input). |+| 119 | PP1 | bidirectional | GPIO port P bit 1, 3.3-V LVCMOS; alternate functions SSI3XDAT3, U6Tx, C2- (analog comparator 2 negative input). |+| 120 | PB5 | bidirectional | GPIO port B bit 5, 3.3-V LVCMOS; alternate functions AIN11 (analog), U0RTS, I2C5SDA, SSI1Clk. |+| 121 | PB4 | bidirectional | GPIO port B bit 4, 3.3-V LVCMOS, high-impedance after reset; alternate functions AIN10 (analog), I2C5SCL, SSI1Fss, U0CTS. |+| 122 | VDD | power_in | Positive supply for I/O and some logic; 2.97 V to 3.63 V (3.3 V nominal). |+| 123 | PE4 | bidirectional | GPIO port E bit 4, 3.3-V LVCMOS, high-impedance after reset; alternate functions AIN9 (analog), SSI1XDAT0, U1RI. |+| 124 | PE5 | bidirectional | GPIO port E bit 5, 3.3-V LVCMOS, high-impedance after reset; alternate functions AIN8 (analog), SSI1XDAT1. |+| 125 | PD4 | bidirectional | GPIO port D bit 4, 3.3-V LVCMOS, high-impedance after reset; alternate functions AIN7 (analog), SSI1XDAT2, T3CCP0, U2Rx. |+| 126 | PD5 | bidirectional | GPIO port D bit 5, 3.3-V LVCMOS, high-impedance after reset; alternate functions AIN6 (analog), SSI1XDAT3, T3CCP1, U2Tx. |+| 127 | PD6 | bidirectional | GPIO port D bit 6, 3.3-V LVCMOS, high-impedance after reset; alternate functions AIN5 (analog), SSI2XDAT3, T4CCP0, U2RTS, USB0EPEN. |+| 128 | PD7 | bidirectional | GPIO port D bit 7, 3.3-V LVCMOS, high-impedance after reset; alternate functions AIN4 (analog), NMI, SSI2XDAT2, T4CCP1, U2CTS, USB0PFLT. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TQFP-128(14x14) |+| Category | Embedded Processors & Controllers |+| Pins | 128 |++## CAD (KiCad official)++- Symbol: `MSP432E401YTPDTR`+- Footprint: `Package_QFP:TQFP-128_14x14mm_P0.4mm`+- 3D model: TQFP-128(14x14) (KiCad packages3D, STEP)+- 3D model files: `msp432e401ytpdtr-etched.step` / `msp432e401ytpdtr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `msp432e401ytpdtr.step` / `msp432e401ytpdtr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/msp432e401y) (157 pp, sha256 `67cd8a2b4daa368b`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/msp432e401ytpdtr-datasheet.pdf)
page.jsonadded+919@@ -0,0 +1,919 @@+{+ "slug": "msp432e401ytpdtr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Microcontrollers (MCU/MPU/SOC), TQFP-128(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "embedded processors & controllers",+ "msp432e401ytpdtr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "msp432e401ytpdtr.kicad_sym",+ "msp432e401ytpdtr.kicad_mod",+ "msp432e401ytpdtr.glb",+ "msp432e401ytpdtr.step",+ "msp432e401ytpdtr.lbr",+ "docs/hero.png",+ "docs/msp432e401ytpdtr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "msp432e401ytpdtr-hero.glb",+ "msp432e401ytpdtr-hero.overlay.json"+ ],+ "component": {+ "mpn": "MSP432E401YTPDTR",+ "manufacturer": "Texas Instruments",+ "package": "TQFP-128(14x14)",+ "pin_count": 128,+ "category": "Embedded Processors & Controllers",+ "subcategory": "Microcontrollers (MCU/MPU/SOC)",+ "datasheet": "https://www.ti.com/cn/lit/gpn/msp432e401y",+ "parts": {+ "symbol": "msp432e401ytpdtr.kicad_sym",+ "footprint": "msp432e401ytpdtr.kicad_mod",+ "model_3d": "msp432e401ytpdtr-hero.glb",+ "model_3d_plain": "msp432e401ytpdtr.glb",+ "model_3d_step": "msp432e401ytpdtr-etched.step",+ "model_3d_step_plain": "msp432e401ytpdtr.step",+ "lbr": "msp432e401ytpdtr.lbr"+ },+ "distributor_links": {+ "lcsc": "C1340001",+ "digikey": "296-47509-2-ND",+ "mouser": "595-MSP432E401YTPDTR"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T20:00:48Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-47509-2-ND",+ "status": "found"+ },+ "mouser": {+ "pn": "595-MSP432E401YTPDTR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "PD0",+ "type": "bidirectional",+ "description": "GPIO port D bit 0, 3.3-V LVCMOS, high-impedance after reset; alternate functions AIN15 (analog), I2C7SCL, T0CCP0, C0o, SSI2XDAT1."+ },+ {+ "number": "2",+ "name": "PD1",+ "type": "bidirectional",+ "description": "GPIO port D bit 1, 3.3-V LVCMOS, high-impedance after reset; alternate functions AIN14 (analog), I2C7SDA, T0CCP1, C1o, SSI2XDAT0."+ },+ {+ "number": "3",+ "name": "PD2",+ "type": "bidirectional",+ "description": "GPIO port D bit 2, 3.3-V LVCMOS, high-impedance after reset; alternate functions AIN13 (analog), C2o, I2C8SCL, SSI2Fss, T1CCP0."+ },+ {+ "number": "4",+ "name": "PD3",+ "type": "bidirectional",+ "description": "GPIO port D bit 3, 3.3-V LVCMOS, high-impedance after reset; alternate functions AIN12 (analog), I2C8SDA, SSI2Clk, T1CCP1."+ },+ {+ "number": "5",+ "name": "PQ0",+ "type": "bidirectional",+ "description": "GPIO port Q bit 0, 3.3-V LVCMOS, high-impedance after reset; alternate functions EPI0S20, SSI3Clk."+ },+ {+ "number": "6",+ "name": "PQ1",+ "type": "bidirectional",+ "description": "GPIO port Q bit 1, 3.3-V LVCMOS; alternate functions EPI0S21, SSI3Fss."+ },+ {+ "number": "7",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply for I/O and some logic; 2.97 V to 3.63 V (3.3 V nominal)."+ },+ {+ "number": "8",+ "name": "VDDA",+ "type": "power_in",+ "description": "Positive supply for analog circuits (ADC, analog comparators); 2.97 V to 3.63 V, and must be powered on before VDD if sourced from a different supply."+ },+ {+ "number": "9",+ "name": "VREFA+",+ "type": "input",+ "description": "ADC reference voltage that sets the code-4095 full-scale level; must stay within the ADC electrical specification range and connect to VDDA when unused per Table 4-6."+ },+ {+ "number": "10",+ "name": "GNDA",+ "type": "power_in",+ "description": "Ground reference for analog circuits (ADC, analog comparators), kept separate from GND to limit noise on analog functions."+ },+ {+ "number": "11",+ "name": "PQ2",+ "type": "bidirectional",+ "description": "GPIO port Q bit 2, 3.3-V LVCMOS; alternate functions EPI0S22, SSI3XDAT0."+ },+ {+ "number": "12",+ "name": "PE3",+ "type": "bidirectional",+ "description": "GPIO port E bit 3, 3.3-V LVCMOS, high-impedance after reset; alternate functions AIN0 (analog), U1DTR."+ },+ {+ "number": "13",+ "name": "PE2",+ "type": "bidirectional",+ "description": "GPIO port E bit 2, 3.3-V LVCMOS, high-impedance after reset; alternate functions AIN1 (analog), U1DCD."+ },+ {+ "number": "14",+ "name": "PE1",+ "type": "bidirectional",+ "description": "GPIO port E bit 1, 3.3-V LVCMOS, high-impedance after reset; alternate functions AIN2 (analog), U1DSR."+ },+ {+ "number": "15",+ "name": "PE0",+ "type": "bidirectional",+ "description": "GPIO port E bit 0, 3.3-V LVCMOS, high-impedance after reset; alternate functions AIN3 (analog), U1RTS."+ },+ {+ "number": "16",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply for I/O and some logic; 2.97 V to 3.63 V (3.3 V nominal)."+ },+ {+ "number": "17",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference for logic and I/O pins."+ },+ {+ "number": "18",+ "name": "PK0",+ "type": "bidirectional",+ "description": "GPIO port K bit 0, 3.3-V LVCMOS; alternate functions AIN16 (analog), EPI0S0, U4Rx."+ },+ {+ "number": "19",+ "name": "PK1",+ "type": "bidirectional",+ "description": "GPIO port K bit 1, 3.3-V LVCMOS; alternate functions AIN17 (analog), EPI0S1, U4Tx."+ },+ {+ "number": "20",+ "name": "PK2",+ "type": "bidirectional",+ "description": "GPIO port K bit 2, 3.3-V LVCMOS; alternate functions AIN18 (analog), EPI0S2, U4RTS."+ },+ {+ "number": "21",+ "name": "PK3",+ "type": "bidirectional",+ "description": "GPIO port K bit 3, 3.3-V LVCMOS; alternate functions AIN19 (analog), EPI0S3, U4CTS."+ },+ {+ "number": "22",+ "name": "PC7",+ "type": "bidirectional",+ "description": "GPIO port C bit 7, 3.3-V LVCMOS; alternate functions C0- (analog comparator 0 negative input), EPI0S4, U5Tx."+ },+ {+ "number": "23",+ "name": "PC6",+ "type": "bidirectional",+ "description": "GPIO port C bit 6, 3.3-V LVCMOS; alternate functions C0+ (analog comparator 0 positive input), EPI0S5, U5Rx."+ },+ {+ "number": "24",+ "name": "PC5",+ "type": "bidirectional",+ "description": "GPIO port C bit 5, 3.3-V LVCMOS; alternate functions C1+ (analog comparator 1 positive input), EPI0S6, U7Tx, RTCCLK."+ },+ {+ "number": "25",+ "name": "PC4",+ "type": "bidirectional",+ "description": "GPIO port C bit 4, 3.3-V LVCMOS; alternate functions C1- (analog comparator 1 negative input), EPI0S7, U7Rx."+ },+ {+ "number": "26",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply for I/O and some logic; 2.97 V to 3.63 V (3.3 V nominal)."+ },+ {+ "number": "27",+ "name": "PQ3",+ "type": "bidirectional",+ "description": "GPIO port Q bit 3, 3.3-V LVCMOS; alternate functions EPI0S23, SSI3XDAT1."+ },+ {+ "number": "28",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply for I/O and some logic; 2.97 V to 3.63 V (3.3 V nominal)."+ },+ {+ "number": "29",+ "name": "PH0",+ "type": "bidirectional",+ "description": "GPIO port H bit 0, 3.3-V LVCMOS; alternate function U0RTS (UART0 request to send)."+ },+ {+ "number": "30",+ "name": "PH1",+ "type": "bidirectional",+ "description": "GPIO port H bit 1, 3.3-V LVCMOS; alternate function U0CTS (UART0 clear to send)."+ },+ {+ "number": "31",+ "name": "PH2",+ "type": "bidirectional",+ "description": "GPIO port H bit 2, 3.3-V LVCMOS; alternate function U0DCD (UART0 data carrier detect)."+ },+ {+ "number": "32",+ "name": "PH3",+ "type": "bidirectional",+ "description": "GPIO port H bit 3, 3.3-V LVCMOS; alternate function U0DSR (UART0 data set ready)."+ },+ {+ "number": "33",+ "name": "PA0",+ "type": "bidirectional",+ "description": "GPIO port A bit 0, 3.3-V LVCMOS; alternate functions U0Rx, I2C9SCL, T0CCP0, CAN0Rx."+ },+ {+ "number": "34",+ "name": "PA1",+ "type": "bidirectional",+ "description": "GPIO port A bit 1, 3.3-V LVCMOS; alternate functions U0Tx, I2C9SDA, T0CCP1, CAN0Tx; the ROM bootloader may drive it as an output if no flash code is present and PA0 receives a valid boot signature, so do not tie it directly to GND."+ },+ {+ "number": "35",+ "name": "PA2",+ "type": "bidirectional",+ "description": "GPIO port A bit 2, 3.3-V LVCMOS; alternate functions U4Rx, I2C8SCL, T1CCP0, SSI0Clk."+ },+ {+ "number": "36",+ "name": "PA3",+ "type": "bidirectional",+ "description": "GPIO port A bit 3, 3.3-V LVCMOS; alternate functions U4Tx, I2C8SDA, T1CCP1, SSI0Fss."+ },+ {+ "number": "37",+ "name": "PA4",+ "type": "bidirectional",+ "description": "GPIO port A bit 4, 3.3-V LVCMOS; alternate functions U3Rx, I2C7SCL, T2CCP0, SSI0XDAT0; the ROM bootloader may enable it as an output, so do not tie it directly to GND."+ },+ {+ "number": "38",+ "name": "PA5",+ "type": "bidirectional",+ "description": "GPIO port A bit 5, 3.3-V LVCMOS; alternate functions U3Tx, I2C7SDA, T2CCP1, SSI0XDAT1."+ },+ {+ "number": "39",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply for I/O and some logic; 2.97 V to 3.63 V (3.3 V nominal)."+ },+ {+ "number": "40",+ "name": "PA6",+ "type": "bidirectional",+ "description": "GPIO port A bit 6, 3.3-V LVCMOS; alternate functions U2Rx, I2C6SCL, T3CCP0, USB0EPEN, SSI0XDAT2, EPI0S8."+ },+ {+ "number": "41",+ "name": "PA7",+ "type": "bidirectional",+ "description": "GPIO port A bit 7, 3.3-V LVCMOS; alternate functions U2Tx, I2C6SDA, T3CCP1, USB0PFLT, USB0EPEN, SSI0XDAT3, EPI0S9."+ },+ {+ "number": "42",+ "name": "PF0",+ "type": "bidirectional",+ "description": "GPIO port F bit 0, 3.3-V LVCMOS; alternate functions M0PWM0, TRD2, EN0LED0, SSI3XDAT1."+ },+ {+ "number": "43",+ "name": "PF1",+ "type": "bidirectional",+ "description": "GPIO port F bit 1, 3.3-V LVCMOS; alternate functions M0PWM1, TRD1, EN0LED2, SSI3XDAT0."+ },+ {+ "number": "44",+ "name": "PF2",+ "type": "bidirectional",+ "description": "GPIO port F bit 2, 3.3-V LVCMOS; alternate functions M0PWM2, TRD0, SSI3Fss."+ },+ {+ "number": "45",+ "name": "PF3",+ "type": "bidirectional",+ "description": "GPIO port F bit 3, 3.3-V LVCMOS; alternate functions M0PWM3, TRCLK, SSI3Clk."+ },+ {+ "number": "46",+ "name": "PF4",+ "type": "bidirectional",+ "description": "GPIO port F bit 4, 3.3-V LVCMOS; alternate functions M0FAULT0, TRD3, EN0LED1, SSI3XDAT2."+ },+ {+ "number": "47",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply for I/O and some logic; 2.97 V to 3.63 V (3.3 V nominal)."+ },+ {+ "number": "48",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference for logic and I/O pins."+ },+ {+ "number": "49",+ "name": "PG0",+ "type": "bidirectional",+ "description": "GPIO port G bit 0, 3.3-V LVCMOS; alternate functions I2C1SCL, M0PWM4, EN0PPS, EPI0S11."+ },+ {+ "number": "50",+ "name": "PG1",+ "type": "bidirectional",+ "description": "GPIO port G bit 1, 3.3-V LVCMOS; alternate functions I2C1SDA, M0PWM5, EPI0S10."+ },+ {+ "number": "51",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply for I/O and some logic; 2.97 V to 3.63 V (3.3 V nominal)."+ },+ {+ "number": "52",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply for I/O and some logic; 2.97 V to 3.63 V (3.3 V nominal)."+ },+ {+ "number": "53",+ "name": "EN0RXIN",+ "type": "bidirectional",+ "description": "Ethernet PHY negative receive differential input; leave unconnected (NC) when Ethernet is unused."+ },+ {+ "number": "54",+ "name": "EN0RXIP",+ "type": "bidirectional",+ "description": "Ethernet PHY positive receive differential input; leave unconnected (NC) when Ethernet is unused."+ },+ {+ "number": "55",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference for logic and I/O pins."+ },+ {+ "number": "56",+ "name": "EN0TXON",+ "type": "bidirectional",+ "description": "Ethernet PHY negative transmit differential output; leave unconnected (NC) when Ethernet is unused."+ },+ {+ "number": "57",+ "name": "EN0TXOP",+ "type": "bidirectional",+ "description": "Ethernet PHY positive transmit differential output; leave unconnected (NC) when Ethernet is unused."+ },+ {+ "number": "58",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference for logic and I/O pins."+ },+ {+ "number": "59",+ "name": "RBIAS",+ "type": "passive",+ "description": "Ethernet PHY bias: connect to ground through a 4.87-kΩ, 1% precision resistor."+ },+ {+ "number": "60",+ "name": "PK7",+ "type": "bidirectional",+ "description": "GPIO port K bit 7, 3.3-V LVCMOS; alternate functions EPI0S24, I2C4SDA, M0FAULT2, RTCCLK, U0RI."+ },+ {+ "number": "61",+ "name": "PK6",+ "type": "bidirectional",+ "description": "GPIO port K bit 6, 3.3-V LVCMOS; alternate functions EPI0S25, I2C4SCL, M0FAULT1, EN0LED1."+ },+ {+ "number": "62",+ "name": "PK5",+ "type": "bidirectional",+ "description": "GPIO port K bit 5, 3.3-V LVCMOS; alternate functions EPI0S31, I2C3SDA, M0PWM7, EN0LED2."+ },+ {+ "number": "63",+ "name": "PK4",+ "type": "bidirectional",+ "description": "GPIO port K bit 4, 3.3-V LVCMOS; alternate functions EPI0S32, I2C3SCL, M0PWM6, EN0LED0."+ },+ {+ "number": "64",+ "name": "WAKE",+ "type": "input",+ "description": "External input that brings the processor out of Hibernate mode when asserted; GND is the preferred connection when unused."+ },+ {+ "number": "65",+ "name": "HIB",+ "type": "output",+ "description": "Output indicating the processor is in Hibernate mode; leave unconnected (NC) when unused."+ },+ {+ "number": "66",+ "name": "XOSC0",+ "type": "input",+ "description": "Hibernation oscillator crystal input or 32.768-kHz external clock reference; GND is the preferred connection when unused."+ },+ {+ "number": "67",+ "name": "XOSC1",+ "type": "output",+ "description": "Hibernation oscillator crystal output; leave unconnected when using a single-ended clock source."+ },+ {+ "number": "68",+ "name": "VBAT",+ "type": "power_in",+ "description": "Battery backup and power source for the Hibernation module, absolute maximum 0 V to 4 V; VDD is the preferred connection when Hibernation is unused."+ },+ {+ "number": "69",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply for I/O and some logic; 2.97 V to 3.63 V (3.3 V nominal)."+ },+ {+ "number": "70",+ "name": "RST",+ "type": "input",+ "description": "System reset input; pull up to VDD through a 0 to 100-kΩ resistor per Table 4-6."+ },+ {+ "number": "71",+ "name": "PM7",+ "type": "bidirectional",+ "description": "GPIO port M bit 7, fast pad supporting only 2-, 4-, 6- and 8-mA drive; alternate functions T5CCP1, U0RI, TMPR0."+ },+ {+ "number": "72",+ "name": "PM6",+ "type": "bidirectional",+ "description": "GPIO port M bit 6, fast pad supporting only 2-, 4-, 6- and 8-mA drive; alternate functions T5CCP0, U0DSR, TMPR1."+ },+ {+ "number": "73",+ "name": "PM5",+ "type": "bidirectional",+ "description": "GPIO port M bit 5, fast pad supporting only 2-, 4-, 6- and 8-mA drive; alternate functions T4CCP1, U0DCD, TMPR2."+ },+ {+ "number": "74",+ "name": "PM4",+ "type": "bidirectional",+ "description": "GPIO port M bit 4, fast pad supporting only 2-, 4-, 6- and 8-mA drive; alternate functions T4CCP0, U0CTS, TMPR3."+ },+ {+ "number": "75",+ "name": "PM3",+ "type": "bidirectional",+ "description": "GPIO port M bit 3, 3.3-V LVCMOS; alternate functions EPI0S12, T3CCP1."+ },+ {+ "number": "76",+ "name": "PM2",+ "type": "bidirectional",+ "description": "GPIO port M bit 2, 3.3-V LVCMOS; alternate functions EPI0S13, T3CCP0."+ },+ {+ "number": "77",+ "name": "PM1",+ "type": "bidirectional",+ "description": "GPIO port M bit 1, 3.3-V LVCMOS; alternate functions EPI0S14, T2CCP1."+ },+ {+ "number": "78",+ "name": "PM0",+ "type": "bidirectional",+ "description": "GPIO port M bit 0, 3.3-V LVCMOS; alternate functions EPI0S15, T2CCP0."+ },+ {+ "number": "79",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply for I/O and some logic; 2.97 V to 3.63 V (3.3 V nominal)."+ },+ {+ "number": "80",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference for logic and I/O pins."+ },+ {+ "number": "81",+ "name": "PL0",+ "type": "bidirectional",+ "description": "GPIO port L bit 0, 3.3-V LVCMOS; alternate functions I2C2SDA, USB0D0, EPI0S16, M0FAULT3."+ },+ {+ "number": "82",+ "name": "PL1",+ "type": "bidirectional",+ "description": "GPIO port L bit 1, 3.3-V LVCMOS; alternate functions I2C2SCL, USB0D1, EPI0S17, PhA0."+ },+ {+ "number": "83",+ "name": "PL2",+ "type": "bidirectional",+ "description": "GPIO port L bit 2, 3.3-V LVCMOS; alternate functions C0o, USB0D2, EPI0S18, PhB0."+ },+ {+ "number": "84",+ "name": "PL3",+ "type": "bidirectional",+ "description": "GPIO port L bit 3, 3.3-V LVCMOS; alternate functions C1o, USB0D3, EPI0S19, IDX0."+ },+ {+ "number": "85",+ "name": "PL4",+ "type": "bidirectional",+ "description": "GPIO port L bit 4, 3.3-V LVCMOS; alternate functions T0CCP0, USB0D4, EPI0S26."+ },+ {+ "number": "86",+ "name": "PL5",+ "type": "bidirectional",+ "description": "GPIO port L bit 5, 3.3-V LVCMOS; alternate functions T0CCP1, USB0D5, EPI0S33."+ },+ {+ "number": "87",+ "name": "VDDC",+ "type": "power_out",+ "description": "Core logic supply generated by the on-chip LDO at 1.2 V (1.14 V to 1.32 V in run mode); connect only to the other VDDC pins and the external capacitor specified in the LDO characteristics."+ },+ {+ "number": "88",+ "name": "OSC0",+ "type": "input",+ "description": "Main oscillator crystal input or external clock reference; GND is the preferred connection when unused."+ },+ {+ "number": "89",+ "name": "OSC1",+ "type": "output",+ "description": "Main oscillator crystal output; leave unconnected when using a single-ended clock source."+ },+ {+ "number": "90",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply for I/O and some logic; 2.97 V to 3.63 V (3.3 V nominal)."+ },+ {+ "number": "91",+ "name": "PB2",+ "type": "bidirectional",+ "description": "GPIO port B bit 2, 3.3-V LVCMOS; alternate functions I2C0SCL, T5CCP0, USB0STP, EPI0S27."+ },+ {+ "number": "92",+ "name": "PB3",+ "type": "bidirectional",+ "description": "GPIO port B bit 3, 3.3-V LVCMOS; alternate functions I2C0SDA, T5CCP1, USB0CLK, EPI0S28."+ },+ {+ "number": "93",+ "name": "PL7",+ "type": "bidirectional",+ "description": "GPIO port L bit 7 (fast pad, 4-mA drive only), also USB0DM; unused pins should be pulled down to GND through 1 kΩ per Table 4-6; alternate function T1CCP1."+ },+ {+ "number": "94",+ "name": "PL6",+ "type": "bidirectional",+ "description": "GPIO port L bit 6 (fast pad, 4-mA drive only), also USB0DP; unused pins should be pulled down to GND through 1 kΩ per Table 4-6; alternate function T1CCP0."+ },+ {+ "number": "95",+ "name": "PB0",+ "type": "bidirectional",+ "description": "GPIO port B bit 0, 3.3-V LVCMOS; alternate functions USB0ID, U1Rx, I2C5SCL, T4CCP0, CAN1Rx."+ },+ {+ "number": "96",+ "name": "PB1",+ "type": "bidirectional",+ "description": "GPIO port B bit 1, 3.3-V LVCMOS; alternate functions USB0VBUS, U1Tx, I2C5SDA, T4CCP1, CAN1Tx."+ },+ {+ "number": "97",+ "name": "PC3",+ "type": "bidirectional",+ "description": "GPIO port C bit 3, 3.3-V LVCMOS; default function JTAG TDO/SWO."+ },+ {+ "number": "98",+ "name": "PC2",+ "type": "bidirectional",+ "description": "GPIO port C bit 2, 3.3-V LVCMOS; default function JTAG TDI."+ },+ {+ "number": "99",+ "name": "PC1",+ "type": "bidirectional",+ "description": "GPIO port C bit 1, 3.3-V LVCMOS; default function JTAG TMS/SWDIO."+ },+ {+ "number": "100",+ "name": "PC0",+ "type": "bidirectional",+ "description": "GPIO port C bit 0, 3.3-V LVCMOS; default function JTAG TCK/SWCLK."+ },+ {+ "number": "101",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply for I/O and some logic; 2.97 V to 3.63 V (3.3 V nominal)."+ },+ {+ "number": "102",+ "name": "PQ4",+ "type": "bidirectional",+ "description": "GPIO port Q bit 4, 3.3-V LVCMOS; alternate functions DIVSCLK (optionally divided reference clock output), U1Rx."+ },+ {+ "number": "103",+ "name": "PP2",+ "type": "bidirectional",+ "description": "GPIO port P bit 2, 3.3-V LVCMOS; alternate functions EPI0S29, U0DTR, USB0NXT."+ },+ {+ "number": "104",+ "name": "PP3",+ "type": "bidirectional",+ "description": "GPIO port P bit 3, 3.3-V LVCMOS; alternate functions EPI0S30, U0DCD, U1CTS, USB0DIR, RTCCLK."+ },+ {+ "number": "105",+ "name": "PP4",+ "type": "bidirectional",+ "description": "GPIO port P bit 4, 3.3-V LVCMOS; alternate functions U0DSR, U3RTS, USB0D7."+ },+ {+ "number": "106",+ "name": "PP5",+ "type": "bidirectional",+ "description": "GPIO port P bit 5, 3.3-V LVCMOS; alternate functions U3CTS, I2C2SCL, USB0D6."+ },+ {+ "number": "107",+ "name": "PN0",+ "type": "bidirectional",+ "description": "GPIO port N bit 0, 3.3-V LVCMOS; alternate function U1RTS."+ },+ {+ "number": "108",+ "name": "PN1",+ "type": "bidirectional",+ "description": "GPIO port N bit 1, 3.3-V LVCMOS; alternate function U1CTS."+ },+ {+ "number": "109",+ "name": "PN2",+ "type": "bidirectional",+ "description": "GPIO port N bit 2, 3.3-V LVCMOS; alternate functions EPI0S29, U1DCD, U2RTS."+ },+ {+ "number": "110",+ "name": "PN3",+ "type": "bidirectional",+ "description": "GPIO port N bit 3, 3.3-V LVCMOS; alternate functions EPI0S30, U1DSR, U2CTS."+ },+ {+ "number": "111",+ "name": "PN4",+ "type": "bidirectional",+ "description": "GPIO port N bit 4, 3.3-V LVCMOS; alternate functions EPI0S34, I2C2SDA, U3RTS, U1DTR."+ },+ {+ "number": "112",+ "name": "PN5",+ "type": "bidirectional",+ "description": "GPIO port N bit 5, 3.3-V LVCMOS; alternate functions EPI0S35, I2C2SCL, U3CTS, U1RI."+ },+ {+ "number": "113",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply for I/O and some logic; 2.97 V to 3.63 V (3.3 V nominal)."+ },+ {+ "number": "114",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference for logic and I/O pins."+ },+ {+ "number": "115",+ "name": "VDDC",+ "type": "power_out",+ "description": "Core logic supply generated by the on-chip LDO at 1.2 V (1.14 V to 1.32 V in run mode); connect only to the other VDDC pins and the external capacitor specified in the LDO characteristics."+ },+ {+ "number": "116",+ "name": "PJ0",+ "type": "bidirectional",+ "description": "GPIO port J bit 0, 3.3-V LVCMOS; alternate functions EN0PPS, U3Rx."+ },+ {+ "number": "117",+ "name": "PJ1",+ "type": "bidirectional",+ "description": "GPIO port J bit 1, slow GPIO pad with 2-mA drive; alternate function U3Tx."+ },+ {+ "number": "118",+ "name": "PP0",+ "type": "bidirectional",+ "description": "GPIO port P bit 0, 3.3-V LVCMOS; alternate functions SSI3XDAT2, U6Rx, C2+ (analog comparator 2 positive input)."+ },+ {+ "number": "119",+ "name": "PP1",+ "type": "bidirectional",+ "description": "GPIO port P bit 1, 3.3-V LVCMOS; alternate functions SSI3XDAT3, U6Tx, C2- (analog comparator 2 negative input)."+ },+ {+ "number": "120",+ "name": "PB5",+ "type": "bidirectional",+ "description": "GPIO port B bit 5, 3.3-V LVCMOS; alternate functions AIN11 (analog), U0RTS, I2C5SDA, SSI1Clk."+ },+ {+ "number": "121",+ "name": "PB4",+ "type": "bidirectional",+ "description": "GPIO port B bit 4, 3.3-V LVCMOS, high-impedance after reset; alternate functions AIN10 (analog), I2C5SCL, SSI1Fss, U0CTS."+ },+ {+ "number": "122",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply for I/O and some logic; 2.97 V to 3.63 V (3.3 V nominal)."+ },+ {+ "number": "123",+ "name": "PE4",+ "type": "bidirectional",+ "description": "GPIO port E bit 4, 3.3-V LVCMOS, high-impedance after reset; alternate functions AIN9 (analog), SSI1XDAT0, U1RI."+ },+ {+ "number": "124",+ "name": "PE5",+ "type": "bidirectional",+ "description": "GPIO port E bit 5, 3.3-V LVCMOS, high-impedance after reset; alternate functions AIN8 (analog), SSI1XDAT1."+ },+ {+ "number": "125",+ "name": "PD4",+ "type": "bidirectional",+ "description": "GPIO port D bit 4, 3.3-V LVCMOS, high-impedance after reset; alternate functions AIN7 (analog), SSI1XDAT2, T3CCP0, U2Rx."+ },+ {+ "number": "126",+ "name": "PD5",+ "type": "bidirectional",+ "description": "GPIO port D bit 5, 3.3-V LVCMOS, high-impedance after reset; alternate functions AIN6 (analog), SSI1XDAT3, T3CCP1, U2Tx."+ },+ {+ "number": "127",+ "name": "PD6",+ "type": "bidirectional",+ "description": "GPIO port D bit 6, 3.3-V LVCMOS, high-impedance after reset; alternate functions AIN5 (analog), SSI2XDAT3, T4CCP0, U2RTS, USB0EPEN."+ },+ {+ "number": "128",+ "name": "PD7",+ "type": "bidirectional",+ "description": "GPIO port D bit 7, 3.3-V LVCMOS, high-impedance after reset; alternate functions AIN4 (analog), NMI, SSI2XDAT2, T4CCP1, U2CTS, USB0PFLT."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Only 30 of 157 datasheet pages were supplied. Pin-number-to-name mapping for pins 6-120 was not read; Alternate-function lists are taken from Table 4-3 (signal descriptions). Table 4-4 (GPIO pin multipl; Pin type judgement: VDDC (pins 87, 115) is the output of the on-chip LDO, so it is typed power_out r"+ ],+ "pages_sent": 30,+ "cost_usd": 0.2702,+ "at": "2026-10-08T20:00:00"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/msp432e401y",+ "pages": 157,+ "sha256": "67cd8a2b4daa368b",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 128,+ "described": 128,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "msp432e401ytpdtr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 16,+ 16,+ 1.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "3b8d257b30f25cdf1e0f6a8c639d98f6174f71f83f9b50ea0ca10c4bbb58ee28",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "msp432e401ytpdtr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 16,+ 16,+ 1.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "7a657212caac1ec926272284278fda39158824bd12d5068e5c41e5eafb3ca1d6",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}