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MSP432E401YTPDT

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Texas Instruments Microcontrollers (MCU/MPU/SOC), TQFP-128(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersmsp432e401ytpdtfactory-2.0.0extractor-text
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Contents

README

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MSP432E401YTPDT

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · TQFP-128(14x14)

MSP432E401YTPDT from Texas Instruments, in a TQFP-128(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PD0 bidirectional GPIO port D bit 0 (LVCMOS 3.3 V, high-impedance after reset); analog input AIN15 with alternate functions C0o, I2C7SCL, SSI2XDAT1 and T0CCP0.
2 PD1 bidirectional GPIO port D bit 1 (LVCMOS 3.3 V, high-impedance after reset); analog input AIN14 with alternate functions C1o, I2C7SDA, SSI2XDAT0 and T0CCP1.
3 PD2 bidirectional GPIO port D bit 2 (LVCMOS 3.3 V, high-impedance after reset); analog input AIN13 with alternate functions C2o, I2C8SCL, SSI2Fss and T1CCP0.
4 PD3 bidirectional GPIO port D bit 3 (LVCMOS 3.3 V, high-impedance after reset); analog input AIN12 with alternate functions I2C8SDA, SSI2Clk and T1CCP1.
5 PQ0 bidirectional GPIO port Q bit 0 (LVCMOS 3.3 V, high-impedance after reset) with alternate functions EPI0S20 and SSI3Clk.
6 PQ1 bidirectional GPIO port Q bit 1 with alternate functions EPI0S21 and SSI3Fss.
7 VDD power_in Positive supply for I/O and some logic; 2.97 V to 3.63 V (3.3 V nominal).
8 VDDA power_in Positive supply for analog circuits (ADC, analog comparators), separated from VDD; 2.97 V to 3.63 V, and power VDDA before VDD if sourced from a different supply.
9 VREFA+ input ADC reference voltage that sets the full-scale point (AINn converts to 4095), limited to the ADC electrical specification range; connect to VDDA if unused.
10 GNDA power_in Ground reference for analog circuits (ADC, analog comparators), kept separate from GND to reduce noise coupling.
11 PQ2 bidirectional GPIO port Q bit 2 with alternate functions EPI0S22 and SSI3XDAT0.
12 PE3 bidirectional GPIO port E bit 3 (LVCMOS 3.3 V); analog input AIN0.
13 PE2 bidirectional GPIO port E bit 2 (LVCMOS 3.3 V); analog input AIN1 with alternate function U1DCD.
14 PE1 bidirectional GPIO port E bit 1 (LVCMOS 3.3 V); analog input AIN2 with alternate function U1DSR.
15 PE0 bidirectional GPIO port E bit 0 (LVCMOS 3.3 V); analog input AIN3 with alternate function U1RTS.
16 VDD power_in Positive supply for I/O and some logic; 2.97 V to 3.63 V (3.3 V nominal).
17 GND power_in Ground reference for logic and I/O pins.
18 PK0 bidirectional GPIO port K bit 0 (LVCMOS 3.3 V); analog input AIN16 with alternate functions U4Rx and EPI0S0.
19 PK1 bidirectional GPIO port K bit 1 (LVCMOS 3.3 V); analog input AIN17 with alternate functions U4Tx and EPI0S1.
20 PK2 bidirectional GPIO port K bit 2 (LVCMOS 3.3 V); analog input AIN18 with alternate functions U4RTS and EPI0S2.
21 PK3 bidirectional GPIO port K bit 3 (LVCMOS 3.3 V); analog input AIN19 with alternate functions U4CTS and EPI0S3.
22 PC7 bidirectional GPIO port C bit 7 (3.3-V tolerant); analog comparator 0 negative input C0- with alternate functions U5Tx and EPI0S4.
23 PC6 bidirectional GPIO port C bit 6 (3.3-V tolerant); analog comparator 0 positive input C0+ with alternate functions U5Rx and EPI0S5.
24 PC5 bidirectional GPIO port C bit 5 (3.3-V tolerant); analog comparator 1 positive input C1+ with alternate functions U7Tx, RTCCLK and EPI0S6.
25 PC4 bidirectional GPIO port C bit 4 (3.3-V tolerant); analog comparator 1 negative input C1- with alternate functions U7Rx and EPI0S7.
26 VDD power_in Positive supply for I/O and some logic; 2.97 V to 3.63 V (3.3 V nominal).
27 PQ3 bidirectional GPIO port Q bit 3 with alternate functions EPI0S23 and SSI3XDAT1.
28 VDD power_in Positive supply for I/O and some logic; 2.97 V to 3.63 V (3.3 V nominal).
29 PH0 bidirectional GPIO port H bit 0 with alternate functions EPI0S0 and U0RTS.
30 PH1 bidirectional GPIO port H bit 1 with alternate functions EPI0S1 and U0CTS.
31 PH2 bidirectional GPIO port H bit 2 with alternate functions EPI0S2 and U0DCD.
32 PH3 bidirectional GPIO port H bit 3 with alternate functions EPI0S3 and U0DSR.
33 PA0 bidirectional GPIO port A bit 0 with alternate functions U0Rx, I2C9SCL, T0CCP0 and CAN0Rx (LVCMOS 3.3 V; ROM bootloader may use this pin as UART receive).
34 PA1 bidirectional GPIO port A bit 1 with alternate functions U0Tx, I2C9SDA, T0CCP1 and CAN0Tx; the ROM bootloader may enable it as an output, so do not tie it directly to GND.
35 PA2 bidirectional GPIO port A bit 2 with alternate functions U4Rx, I2C8SCL, T1CCP0 and SSI0Clk.
36 PA3 bidirectional GPIO port A bit 3 with alternate functions U4Tx, I2C8SDA, T1CCP1 and SSI0Fss.
37 PA4 bidirectional GPIO port A bit 4 with alternate functions U3Rx, I2C7SCL, T2CCP0 and SSI0XDAT0; the ROM bootloader may enable it as an output, so do not tie it directly to GND.
38 PA5 bidirectional GPIO port A bit 5 with alternate functions U3Tx, I2C7SDA, T2CCP1 and SSI0XDAT1.
39 VDD power_in Positive supply for I/O and some logic; 2.97 V to 3.63 V (3.3 V nominal).
40 PA6 bidirectional GPIO port A bit 6 with alternate functions U2Rx, I2C6SCL, T3CCP0, USB0EPEN, SSI0XDAT2 and EPI0S8.
41 PA7 bidirectional GPIO port A bit 7 with alternate functions U2Tx, I2C6SDA, T3CCP1, USB0PFLT, USB0EPEN, SSI0XDAT3 and EPI0S9.
42 PF0 bidirectional GPIO port F bit 0 with alternate functions M0PWM0, TRD2, EN0LED2 and SSI3XDAT1.
43 PF1 bidirectional GPIO port F bit 1 with alternate functions M0PWM1, TRD1 and SSI3XDAT0.
44 PF2 bidirectional GPIO port F bit 2 with alternate functions M0PWM2, TRD0 and SSI3Fss.
45 PF3 bidirectional GPIO port F bit 3 with alternate functions M0PWM3, TRCLK and SSI3Clk.
46 PF4 bidirectional GPIO port F bit 4 with alternate functions M0FAULT0, TRD3 and SSI3XDAT2.
47 VDD power_in Positive supply for I/O and some logic; 2.97 V to 3.63 V (3.3 V nominal).
48 GND power_in Ground reference for logic and I/O pins.
49 PG0 bidirectional GPIO port G bit 0 with alternate functions EN0PPS, I2C1SCL, M0PWM4 and EPI0S11.
50 PG1 bidirectional GPIO port G bit 1 with alternate functions I2C1SDA, M0PWM5 and EPI0S10.
51 VDD power_in Positive supply for I/O and some logic; 2.97 V to 3.63 V (3.3 V nominal).
52 VDD power_in Positive supply for I/O and some logic; 2.97 V to 3.63 V (3.3 V nominal).
53 EN0RXIN bidirectional Ethernet PHY negative receive differential input; leave unconnected (NC) when Ethernet is unused.
54 EN0RXIP bidirectional Ethernet PHY positive receive differential input; leave unconnected (NC) when Ethernet is unused.
55 GND power_in Ground reference for logic and I/O pins.
56 EN0TXON bidirectional Ethernet PHY negative transmit differential output; leave unconnected (NC) when Ethernet is unused.
57 EN0TXOP bidirectional Ethernet PHY positive transmit differential output; leave unconnected (NC) when Ethernet is unused.
58 GND power_in Ground reference for logic and I/O pins.
59 RBIAS passive Ethernet PHY bias: connect to ground through a 4.87-kΩ, 1% precision resistor.
60 PK7 bidirectional GPIO port K bit 7 with alternate functions I2C4SDA, EPI0S24, M0FAULT2, U0RI and RTCCLK.
61 PK6 bidirectional GPIO port K bit 6 with alternate functions I2C4SCL, EPI0S25, M0FAULT1 and EN0LED1.
62 PK5 bidirectional GPIO port K bit 5 with alternate functions I2C3SDA, EPI0S31 and M0PWM7.
63 PK4 bidirectional GPIO port K bit 4 with alternate functions I2C3SCL, EPI0S32, M0PWM6 and EN0LED0.
64 WAKE input External input that brings the processor out of Hibernate mode when asserted; connect to GND if unused.
65 HIB output Output that indicates the processor is in Hibernate mode; leave unconnected if unused.
66 XOSC0 input Hibernation oscillator crystal input or 32.768-kHz external clock reference for the Hibernation RTC; connect to GND if unused.
67 XOSC1 output Hibernation oscillator crystal output; leave unconnected when using a single-ended clock source.
68 VBAT power_in Power source for the Hibernation module, normally the battery positive terminal; absolute maximum 0 to 4 V; connect to VDD if unused.
69 VDD power_in Positive supply for I/O and some logic; 2.97 V to 3.63 V (3.3 V nominal).
70 RST input System reset input; pull up to VDD through a 0 to 100-kΩ resistor (preferred practice).
71 PM7 bidirectional GPIO port M bit 7 with alternate functions TMPR0, T5CCP1 and U0RI; drive strength limited to 2, 4, 6 and 8 mA.
72 PM6 bidirectional GPIO port M bit 6 with alternate functions TMPR1, T5CCP0 and U0DSR; drive strength limited to 2, 4, 6 and 8 mA.
73 PM5 bidirectional GPIO port M bit 5 with alternate functions TMPR2, T4CCP1 and U0DCD; drive strength limited to 2, 4, 6 and 8 mA.
74 PM4 bidirectional GPIO port M bit 4 with alternate functions TMPR3, T4CCP0 and U0CTS; drive strength limited to 2, 4, 6 and 8 mA.
75 PM3 bidirectional GPIO port M bit 3 with alternate function T3CCP1.
76 PM2 bidirectional GPIO port M bit 2 with alternate function T3CCP0.
77 PM1 bidirectional GPIO port M bit 1 with alternate function T2CCP1.
78 PM0 bidirectional GPIO port M bit 0 with alternate function T2CCP0.
79 VDD power_in Positive supply for I/O and some logic; 2.97 V to 3.63 V (3.3 V nominal).
80 GND power_in Ground reference for logic and I/O pins.
81 PL0 bidirectional GPIO port L bit 0 with alternate functions I2C2SDA, USB0D0, M0FAULT3 and EPI0S16.
82 PL1 bidirectional GPIO port L bit 1 with alternate functions I2C2SCL, USB0D1, PhA0 and EPI0S17.
83 PL2 bidirectional GPIO port L bit 2 with alternate functions USB0D2, PhB0, C0o and EPI0S18.
84 PL3 bidirectional GPIO port L bit 3 with alternate functions USB0D3, IDX0, C1o and EPI0S19.
85 PL4 bidirectional GPIO port L bit 4 with alternate functions USB0D4, T0CCP0 and EPI0S26.
86 PL5 bidirectional GPIO port L bit 5 with alternate functions USB0D5, T0CCP1 and EPI0S33.
87 VDDC power_in 1.2-V core supply from the on-chip LDO (run mode 1.14 V to 1.32 V); connect only to the other VDDC pins and the external capacitor specified for the LDO.
88 OSC0 input Main oscillator crystal input or external clock reference input; connect to GND if unused (preferred practice).
89 OSC1 output Main oscillator crystal output; leave unconnected when using a single-ended clock source.
90 VDD power_in Positive supply for I/O and some logic; 2.97 V to 3.63 V (3.3 V nominal).
91 PB2 bidirectional GPIO port B bit 2 with alternate functions I2C0SCL, T5CCP0, USB0STP and EPI0S27.
92 PB3 bidirectional GPIO port B bit 3 with alternate functions I2C0SDA, T5CCP1, USB0CLK and EPI0S28.
93 PL7 bidirectional GPIO port L bit 7 (fast pad, 4-mA drive only) with alternate functions USB0DM and T1CCP1.
94 PL6 bidirectional GPIO port L bit 6 (fast pad, 4-mA drive only) with alternate functions USB0DP and T1CCP0.
95 PB0 bidirectional GPIO port B bit 0 with alternate functions USB0ID, U1Rx, I2C5SCL, T4CCP0 and CAN1Rx.
96 PB1 bidirectional GPIO port B bit 1 with alternate functions USB0VBUS, U1Tx, I2C5SDA, T4CCP1 and CAN1Tx.
97 PC3/TDO/SWO output JTAG TDO and SWO trace output (default JTAG/SWD function after reset).
98 PC2/TDI input JTAG TDI test data input (default JTAG/SWD function after reset).
99 PC1/TMS/SWDIO bidirectional JTAG TMS and SWDIO test mode select / serial wire data I/O (default JTAG/SWD function after reset).
100 PC0/TCK/SWCLK input JTAG/SWD clock input (default JTAG/SWD function after reset).
101 VDD power_in Positive supply for I/O and some logic; 2.97 V to 3.63 V (3.3 V nominal).
102 PQ4 bidirectional GPIO port Q bit 4 with alternate functions DIVSCLK (optionally divided reference clock output) and U1Rx.
103 PP2 bidirectional GPIO port P bit 2 with alternate functions EPI0S29, U0DTR and USB0NXT.
104 PP3 bidirectional GPIO port P bit 3 with alternate functions EPI0S30, U1CTS, U0DCD, USB0DIR and RTCCLK.
105 PP4 bidirectional GPIO port P bit 4 with alternate functions U3RTS, U0DSR and USB0D7.
106 PP5 bidirectional GPIO port P bit 5 with alternate functions U3CTS, USB0D6 and I2C2SCL.
107 PN0 bidirectional GPIO port N bit 0 with alternate function U1RTS.
108 PN1 bidirectional GPIO port N bit 1 with alternate function U1CTS.
109 PN2 bidirectional GPIO port N bit 2 with alternate functions U1DCD and U2RTS.
110 PN3 bidirectional GPIO port N bit 3 with alternate functions U1DSR and U2CTS.
111 PN4 bidirectional GPIO port N bit 4 with alternate functions U1DTR, U3RTS and I2C2SDA.
112 PN5 bidirectional GPIO port N bit 5 with alternate functions U1RI, U3CTS and I2C2SCL.
113 VDD power_in Positive supply for I/O and some logic; 2.97 V to 3.63 V (3.3 V nominal).
114 GND power_in Ground reference for logic and I/O pins.
115 VDDC power_in 1.2-V core supply from the on-chip LDO (run mode 1.14 V to 1.32 V); connect only to the other VDDC pins and the external capacitor specified for the LDO.
116 PJ0 bidirectional GPIO port J bit 0 with alternate function U3Rx.
117 PJ1 bidirectional GPIO port J bit 1 (slow pad, 2-mA drive) with alternate function U3Tx.
118 PP0 bidirectional GPIO port P bit 0 with alternate functions U6Rx and SSI3XDAT2.
119 PP1 bidirectional GPIO port P bit 1 with alternate functions U6Tx and SSI3XDAT3.
120 PB5 bidirectional GPIO port B bit 5; analog input AIN11 with alternate functions U0RTS, I2C5SDA and SSI1Clk.
121 PB4 bidirectional GPIO port B bit 4; analog input AIN10 with alternate functions U0CTS, I2C5SCL and SSI1Fss.
122 VDD power_in Positive supply for I/O and some logic; 2.97 V to 3.63 V (3.3 V nominal).
123 PE4 bidirectional GPIO port E bit 4; analog input AIN9 with alternate functions SSI1XDAT0 and U1RI.
124 PE5 bidirectional GPIO port E bit 5; analog input AIN8 with alternate function SSI1XDAT1.
125 PD4 bidirectional GPIO port D bit 4; analog input AIN7 with alternate functions SSI1XDAT2, T3CCP0 and U2Rx.
126 PD5 bidirectional GPIO port D bit 5; analog input AIN6 with alternate functions SSI1XDAT3, T3CCP1 and U2Tx.
127 PD6 bidirectional GPIO port D bit 6; analog input AIN5 with alternate functions SSI2XDAT3, T4CCP0, U2RTS and USB0EPEN.
128 PD7 bidirectional GPIO port D bit 7 (locked as GPIO after reset); analog input AIN4 with alternate functions NMI, SSI2XDAT2, T4CCP1, U2CTS and USB0PFLT.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TQFP-128(14x14)
Category Embedded Processors & Controllers
Pins 128

CAD (KiCad official)

  • Symbol: MSP432E401YTPDT
  • Footprint: Package_QFP:TQFP-128_14x14mm_P0.4mm
  • 3D model: TQFP-128(14x14) (KiCad packages3D, STEP)
  • 3D model files: msp432e401ytpdt-etched.step / msp432e401ytpdt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); msp432e401ytpdt.step / msp432e401ytpdt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (157 pp, sha256 67cd8a2b4daa368b, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF