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MSP430I2041TRHBR
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), VQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMSP430I2041TRHBR
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · VQFN-32-EP(5x5)
MSP430I2041TRHBR from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A0.0+ | input | SD24 positive analog input A0.0 |
| 2 | A0.0- | input | SD24 negative analog input A0.0 |
| 3 | A1.0+ | input | SD24 positive analog input A1.0 |
| 4 | A1.0- | input | SD24 negative analog input A1.0 |
| 5 | A2.0+ | input | SD24 positive analog input A2.0 |
| 6 | A2.0- | input | SD24 negative analog input A2.0 |
| 7 | A3.0+ | input | SD24 positive analog input A3.0 |
| 8 | A3.0- | input | SD24 negative analog input A3.0 |
| 9 | VREF | power_in | SD24 external reference voltage input; connect 100 nF capacitor to AVSS when using internal reference |
| 10 | AVSS | power_in | Analog supply voltage negative terminal (ground) |
| 11 | ROSC | passive | External resistor connection for DCO frequency tuning; connect 20 kΩ resistor to AVSS for external mode or connect to AVSS for internal mode |
| 12 | DVSS | power_in | Digital supply voltage negative terminal (ground) |
| 13 | VCC | power_in | Analog and digital supply voltage positive terminal, 2.2 V to 3.6 V |
| 14 | VCORE | power_in | Regulated core power supply 1.8 V output for internal use only; connect 470 nF capacitor to AVSS |
| 15 | RST/NMI/SBWTDIO | bidirectional | Reset or nonmaskable interrupt input; Spy-Bi-Wire test data input/output for device programming and test |
| 16 | TEST/SBWTCK | input | JTAG test mode enable input; Spy-Bi-Wire test clock input for device programming and test |
| 17 | P1.0/UCA0STE/MCLK/TCK | bidirectional | Programmable port P1.0 I/O; MCLK clock output; JTAG test clock |
| 18 | P1.1/UCA0CLK/SMCLK/TMS | bidirectional | Programmable port P1.1 I/O; SMCLK clock output; JTAG test mode select |
| 19 | P1.2/UCA0RXD/UCA0SOMI/ACLK/TDI/TCLK | bidirectional | Programmable port P1.2 I/O; ACLK clock output; eUSCI_A0 UART receive or SPI slave out; JTAG test data or clock input |
| 20 | P1.3/UCA0TXD/UCA0SIMO/TA0CLK/TDO/TDI | bidirectional | Programmable port P1.3 I/O; Timer TA0 external clock input; eUSCI_A0 UART transmit or SPI slave in; JTAG test data output |
| 21 | P1.4/UCB0STE/TA0.0 | bidirectional | Programmable port P1.4 I/O; Timer TA0 CCR0 capture input or compare output |
| 22 | P1.5/UCB0CLK/TA0.1 | bidirectional | Programmable port P1.5 I/O; Timer TA0 CCR1 capture input or compare output |
| 23 | P1.6/UCB0SCL/UCB0SOMI/TA0.2 | bidirectional | Programmable port P1.6 I/O; Timer TA0 CCR2 capture input or compare output; eUSCI_B0 I2C clock or SPI slave out/master in |
| 24 | P1.7/UCB0SDA/UCB0SIMO/TA1CLK | bidirectional | Programmable port P1.7 I/O; Timer TA1 external clock input; eUSCI_B0 I2C data or SPI slave input/master output |
| 25 | P2.0/TA1.0/CLKIN | bidirectional | Programmable port P2.0 I/O; Timer TA1 CCR0 capture input or compare output; DCO bypass clock input |
| 26 | P2.1/TA1.1 | bidirectional | Programmable port P2.1 I/O; Timer TA1 CCR1 capture input or compare output; LPM4.5 wake-up capable |
| 27 | P2.2/TA1.2 | bidirectional | Programmable port P2.2 I/O; Timer TA1 CCR2 capture input or compare output; LPM4.5 wake-up capable |
| 28 | P2.3/VMONIN | bidirectional | Programmable port P2.3 I/O or external voltage monitor input |
| 29 | P2.4/TA1.0 | bidirectional | Programmable port P2.4 I/O (RHB only); Timer TA1 CCR0 capture input or compare output |
| 30 | P2.5/TA0.0 | bidirectional | Programmable port P2.5 I/O (RHB only); Timer TA0 CCR0 capture input or compare output |
| 31 | P2.6/TA0.1 | bidirectional | Programmable port P2.6 I/O (RHB only); Timer TA0 CCR1 compare output |
| 32 | P2.7/TA0.2 | bidirectional | Programmable port P2.7 I/O (RHB only); Timer TA0 CCR2 compare output |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-32-EP(5x5) |
| Category | Embedded Processors & Controllers |
| Pins | 33 |
CAD (KiCad official)
- Symbol:
MSP430I2041TRHBR - Footprint:
Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm - 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
- 3D model files:
msp430i2041trhbr-etched.step/msp430i2041trhbr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);msp430i2041trhbr.step/msp430i2041trhbr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (81 pp, sha256
491d1dfb5ddef2e2, retrieved 2026-09-26, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-4-6(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).