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MSP430G2755IRHA40T

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Texas Instruments Microcontrollers (MCU/MPU/SOC), VQFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MSP430G2755IRHA40T

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · VQFN-40-EP(6x6)

MSP430G2755IRHA40T from Texas Instruments, in a VQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DVSS power_in Digital ground reference; connection of the QFN pad to DVSS is recommended.
2 XOUT/P2.7 bidirectional Output terminal of the crystal oscillator, also general-purpose digital I/O P2.7; if used as an input, excess current flows until P2SEL.7 is cleared because the oscillator output driver is connected to this pad after reset.
3 XIN/P2.6 bidirectional Input terminal of the crystal oscillator, also general-purpose digital I/O P2.6.
4 DVSS power_in Digital ground reference.
5 RST/NMI/SBWTDIO input Reset or nonmaskable interrupt input; also carries Spy-Bi-Wire test data input/output during programming and test.
6 P2.0/TA1CLK/ACLK/A0 bidirectional General-purpose digital I/O with alternate functions Timer1_A3.TACLK input, ACLK output, and ADC10 analog input A0.
7 P2.1/TA0INCLK/SMCLK/A1 bidirectional General-purpose digital I/O with alternate functions Timer_A INCLK clock input, SMCLK output, and ADC10 analog input A1.
8 P2.2/TA0.0/A2 bidirectional General-purpose digital I/O with alternate functions Timer_A CCI0B input or BSL receive, OUT0 output, and ADC10 analog input A2.
9 P3.0/UCB0STE/UCA0CLK/A5 bidirectional General-purpose digital I/O with alternate functions USCI_B0 slave transmit enable, USCI_A0 clock input/output, and ADC10 analog input A5.
10 P3.1/UCB0SIMO/UCB0SDA bidirectional General-purpose digital I/O with alternate functions USCI_B0 slave in/master out in SPI mode or USCI_B0 SDA data in I2C mode.
11 P3.2/UCB0SOMI/UCB0SCL bidirectional General-purpose digital I/O with alternate functions USCI_B0 slave out/master in in SPI mode or USCI_B0 SCL clock in I2C mode.
12 P3.3/UCB0CLK/UCA0STE bidirectional General-purpose digital I/O with alternate functions USCI_B0 clock input/output or USCI_A0 slave transmit enable.
13 AVSS power_in Analog ground reference.
14 AVCC power_in Analog supply voltage; the device supply range is stated as 1.8 V to 3.6 V.
15 P4.0/TB0.0/CA0 bidirectional General-purpose digital I/O with alternate functions Timer_B CCI0A input/OUT0 output and Comparator_A+ input CA0.
16 P4.1/TB0.1/CA1 bidirectional General-purpose digital I/O with alternate functions Timer_B CCI1A input/OUT1 output and Comparator_A+ input CA1.
17 P4.2/TB0.2/CA2 bidirectional General-purpose digital I/O with alternate functions Timer_B CCI2A input/OUT2 output and Comparator_A+ input CA2.
18 P4.3/TB0.0/A12/CA3 bidirectional General-purpose digital I/O with alternate functions Timer_B CCI0B input/OUT0 output, ADC10 analog input A12, and Comparator_A+ input CA3.
19 P4.4/TB0.1/A13/CA4 bidirectional General-purpose digital I/O with alternate functions Timer_B CCI1B input/OUT1 output, ADC10 analog input A13, and Comparator_A+ input CA4.
20 P4.5/TB0.2/A14/CA5 bidirectional General-purpose digital I/O with alternate functions Timer_B OUT2 output, ADC10 analog input A14, and Comparator_A+ input CA5.
21 P4.6/TB0OUTH/A15/CA6 bidirectional General-purpose digital I/O with alternate functions Timer_B TBOUTH (switches all TB0 to TB3 outputs to high impedance), Comparator_A+ output CAOUT, ADC10 analog input A15, and Comparator_A+ input CA6.
22 P4.7/TB0CLK/CAOUT/CA7 bidirectional General-purpose digital I/O with alternate functions Timer_B TBCLK clock input, Comparator_A+ output CAOUT, and Comparator_A+ input CA7.
23 P3.4/UCA0TXD/UCA0SIMO bidirectional General-purpose digital I/O with alternate functions USCI_A0 transmit data output in UART mode or USCI_A0 slave in/master out in SPI mode.
24 P3.5/UCA0RXD/UCA0SOMI bidirectional General-purpose digital I/O with alternate functions USCI_A0 receive data input in UART mode or USCI_A0 slave out/master in in SPI mode.
25 P3.6/TA1.1/A6 bidirectional General-purpose digital I/O with alternate functions Timer_A CCI1B input or BSL receive, Timer_A compare output, and ADC10 analog input A6.
26 P3.7/TA1.2/A7 bidirectional General-purpose digital I/O with alternate functions Timer_A CCI2B input or BSL receive, Timer_A compare output, and ADC10 analog input A7.
27 P2.3/TA0.1/A3/VREF-/VEREF- bidirectional General-purpose digital I/O with alternate functions Timer_A CCI1B input/OUT1 output, ADC10 analog input A3, and negative reference voltage output VREF- or input VEREF-.
28 P2.4/TA0.2/A4/VREF+/VEREF+ bidirectional General-purpose digital I/O with alternate functions Timer_A OUT2 output, ADC10 analog input A4, and positive reference voltage output VREF+ or input VEREF+.
29 P1.0/TA0CLK/ADC10CLK bidirectional General-purpose digital I/O with alternate functions Timer_A clock input TACLK and ADC10 conversion clock.
30 P1.1/TA0.0 bidirectional General-purpose digital I/O with alternate functions Timer_A capture CCI0A input, compare OUT0 output, or BSL transmit.
31 P1.2/TA0.1 bidirectional General-purpose digital I/O with alternate functions Timer_A capture CCI1A input and compare OUT1 output.
32 P1.3/TA0.2 bidirectional General-purpose digital I/O with alternate functions Timer_A capture CCI2A input and compare OUT2 output.
33 P1.4/SMCLK/TCK bidirectional General-purpose digital I/O with alternate functions SMCLK signal output and JTAG test clock input for device programming and test.
34 P1.5/TA0.0/TMS bidirectional General-purpose digital I/O with alternate functions Timer_A compare OUT0 output and JTAG test mode select input for device programming and test.
35 P1.6/TA0.1/TDI/TCLK bidirectional General-purpose digital I/O with alternate functions Timer_A compare OUT1 output and JTAG test data input/test clock input during programming and test.
36 P1.7/TA0.2/TDO/TDI bidirectional General-purpose digital I/O with alternate functions Timer_A compare OUT2 output and JTAG test data output/input during programming and test, selected via JTAG instruction.
37 TEST/SBWTCK input Selects test mode for the JTAG pins on Port 1, with the device protection fuse connected to TEST; also the Spy-Bi-Wire test clock input during programming and test.
38 DVCC power_in Digital supply voltage; the device supply range is stated as 1.8 V to 3.6 V.
39 DVCC power_in Digital supply voltage; the device supply range is stated as 1.8 V to 3.6 V.
40 P2.5/TA1.0/ROSC bidirectional General-purpose digital I/O with alternate functions Timer_A CCI0B input or BSL receive, OUT0 output, and input for an external DCO resistor that defines the DCO frequency.
41 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-40-EP(6x6)
Category Embedded Processors & Controllers
Pins 41

CAD (KiCad official)

  • Symbol: MSP430G2755IRHA40T
  • Footprint: Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
  • 3D model: VQFN-40-EP(6x6) (KiCad packages3D, STEP)
  • 3D model files: msp430g2755irha40t-etched.step / msp430g2755irha40t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); msp430g2755irha40t.step / msp430g2755irha40t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (81 pp, sha256 628b461f79fca3b5, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF