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MSP430G2553IRHB32T
Public Made by Adomby adom
Texas Instruments Microcontroller Units (MCUs/MPUs/SOCs), VQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMSP430G2553IRHB32T
Texas Instruments · Microcontroller Units (MCUs/MPUs/SOCs) · VQFN-32-EP(5x5)
MSP430G2553IRHB32T from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P1.1/TA0.0/UCA0RXD/UCA0SOMI/A1/CA1 | bidirectional | General-purpose digital I/O pin supporting Timer0_A capture/compare, USCI_A0 UART receive or SPI master-in/slave-out, ADC10 analog input channel A1, and Comparator_A input channel CA1. |
| 2 | P1.2/TA0.1/UCA0TXD/UCA0SIMO/A2/CA2 | bidirectional | General-purpose digital I/O pin supporting Timer0_A capture/compare, USCI_A0 UART transmit or SPI master-out/slave-in, ADC10 analog input channel A2, and Comparator_A input channel CA2. |
| 3 | P1.3/ADC10CLK/CAOUT/VREF-/VEREF-/A3/CA3 | bidirectional | General-purpose digital I/O pin supporting ADC10 conversion clock output, Comparator_A output, ADC10 negative reference voltage input, ADC10 analog input channel A3, and Comparator_A input channel CA3. |
| 4 | P1.4/SMCLK/UCB0STE/UCA0CLK/VREF+/VEREF+/A4/CA4/TCK | bidirectional | General-purpose digital I/O pin supporting SMCLK system clock output, USCI_B0 slave transmit enable, USCI_A0 bit clock, ADC10 positive reference voltage input, ADC10 analog input channel A4, Comparator_A input channel CA4, and JTAG test clock input. |
| 5 | P1.5/TA0.0/UCB0CLK/UCA0STE/A5/CA5/TMS | bidirectional | General-purpose digital I/O pin supporting Timer0_A compare output, USCI_B0 clock, USCI_A0 slave transmit enable, ADC10 analog input channel A5, Comparator_A input channel CA5, and JTAG test mode select input. |
| 6 | P3.1/TA1.0 | bidirectional | General-purpose digital I/O pin supporting Timer1_A compare output. |
| 7 | P3.0/TA0.2 | bidirectional | General-purpose digital I/O pin supporting Timer0_A capture input and compare output. |
| 8 | NC | unconnected | No connection pad for QFN package; recommended to leave unconnected or connect to VSS. |
| 9 | P2.0/TA1.0 | bidirectional | General-purpose digital I/O pin supporting Timer1_A capture input and compare output. |
| 10 | P2.1/TA1.1 | bidirectional | General-purpose digital I/O pin supporting Timer1_A capture input and compare output. |
| 11 | P2.2/TA1.1 | bidirectional | General-purpose digital I/O pin supporting Timer1_A capture input and compare output. |
| 12 | P3.2/TA1.1 | bidirectional | General-purpose digital I/O pin supporting Timer1_A compare output. |
| 13 | P3.3/TA1.2 | bidirectional | General-purpose digital I/O pin supporting Timer1_A compare output. |
| 14 | P3.4/TA0.0 | bidirectional | General-purpose digital I/O pin supporting Timer0_A compare output. |
| 15 | P2.3/TA1.0 | bidirectional | General-purpose digital I/O pin supporting Timer1_A capture input and compare output. |
| 16 | P2.4/TA1.2 | bidirectional | General-purpose digital I/O pin supporting Timer1_A capture input and compare output. |
| 17 | P2.5/TA1.2 | bidirectional | General-purpose digital I/O pin supporting Timer1_A capture input and compare output. |
| 18 | P3.5/TA0.1 | bidirectional | General-purpose digital I/O pin supporting Timer0_A compare output. |
| 19 | P3.6/TA0.2 | bidirectional | General-purpose digital I/O pin supporting Timer0_A compare output. |
| 20 | P3.7/TA1CLK/CAOUT | bidirectional | General-purpose digital I/O pin supporting Timer1_A clock input and Comparator_A output. |
| 21 | P1.6/TA0.1/UCB0SOMI/UCB0SCL/A6/CA6/TDI/TCLK | bidirectional | General-purpose digital I/O pin supporting Timer0_A compare output, USCI_B0 SPI master-in/slave-out or I2C clock, ADC10 analog input channel A6, Comparator_A input channel CA6, and JTAG test data input or test clock. |
| 22 | P1.7/CAOUT/UCB0SIMO/UCB0SDA/A7/CA7/TDO/TDI | bidirectional | General-purpose digital I/O pin supporting Comparator_A output, USCI_B0 SPI master-out/slave-in or I2C data, ADC10 analog input channel A7, Comparator_A input channel CA7, and JTAG test data output or input. |
| 23 | RST/NMI/SBWTDIO | input | Reset input, non-maskable interrupt input, and Spy-Bi-Wire serial debug data input/output terminal for in-circuit programming and emulation. |
| 24 | TEST/SBWTCK | input | Test mode select input for JTAG interface and Spy-Bi-Wire serial debug clock input terminal for device programming and testing. |
| 25 | XOUT/P2.7 | bidirectional | Crystal oscillator output terminal or general-purpose digital I/O pin P2.7; oscillator output should be left unused when configured as I/O to avoid excessive current draw. |
| 26 | XIN/P2.6/TA0.1 | bidirectional | Crystal oscillator input terminal or general-purpose digital I/O pin P2.6 supporting Timer0_A compare output when configured as I/O. |
| 27 | AVSS | power_in | Analog ground reference for ADC10 converter, Comparator_A module, and internal voltage reference circuits; connect to system ground. |
| 28 | DVSS | power_in | Digital ground reference for digital circuits and system clock oscillators; connect to system ground. |
| 29 | AVCC | power_in | Analog power supply voltage input with operating range 2.2 V to 3.6 V for ADC10, Comparator_A, and internal reference circuits. |
| 30 | DVCC | power_in | Digital power supply voltage input with operating range 1.8 V to 3.6 V for digital circuits and system oscillators. |
| 31 | P1.0/TA0CLK/ACLK/A0/CA0 | bidirectional | General-purpose digital I/O pin supporting Timer0_A clock input, auxiliary clock output, ADC10 analog input channel A0, and Comparator_A input channel CA0. |
| 32 | NC | unconnected | No connection pad for QFN package; recommended to leave unconnected or connect to VSS. |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-32-EP(5x5) |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 33 |
CAD (KiCad official)
- Symbol:
MSP430G2553IRHB32T - Footprint:
Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm - 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
- 3D model files:
msp430g2553irhb32t-etched.step/msp430g2553irhb32t-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);msp430g2553irhb32t.step/msp430g2553irhb32t.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (88 pp, sha256
6b2ec0d3ff2ce347, retrieved 2026-10-07, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).