component
MSP430G2553IPW20
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownMSP430G2553IPW20
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · TSSOP-20
MSP430G2553IPW20 from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DVCC | power_in | Digital supply voltage, 1.8 V to 3.6 V during program execution and 2.2 V to 3.6 V during flash programming or erase. |
| 2 | P1.0/TA0CLK/ACLK/A0/CA0 | bidirectional | General-purpose digital I/O with Timer0_A TACLK input, ACLK output, ADC10 analog input A0 (MSP430G2x53 only) and Comparator_A+ input CA0. |
| 3 | P1.1/TA0.0/UCA0RXD/UCA0SOMI/A1/CA1 | bidirectional | General-purpose digital I/O with Timer0_A CCI0A input or Out0 output, USCI_A0 UART receive data input or SPI slave-out/master-in, ADC10 analog input A1 (MSP430G2x53 only) and Comparator_A+ input CA1; also the BSL data-transmit pin. |
| 4 | P1.2/TA0.1/UCA0TXD/UCA0SIMO/A2/CA2 | bidirectional | General-purpose digital I/O with Timer0_A CCI1A input or Out1 output, USCI_A0 UART transmit data output or SPI slave-in/master-out, ADC10 analog input A2 (MSP430G2x53 only) and Comparator_A+ input CA2. |
| 5 | P1.3/ADC10CLK/CAOUT/VREF-/VEREF-/A3/CA3 | bidirectional | General-purpose digital I/O with ADC10 conversion clock output, Comparator_A+ output CAOUT, ADC10 negative reference VREF-/VEREF-, analog input A3 and Comparator_A+ input CA3 (ADC10 functions on MSP430G2x53 only). |
| 6 | P1.4/SMCLK/UCB0STE/UCA0CLK/VREF+/VEREF+/A4/CA4/TCK | bidirectional | General-purpose digital I/O with SMCLK output, USCI_B0 slave transmit enable, USCI_A0 clock input/output, ADC10 positive reference VREF+/VEREF+, analog input A4 (MSP430G2x53 only), Comparator_A+ input CA4, and JTAG test clock TCK for device programming and test. |
| 7 | P1.5/TA0.0/UCB0CLK/UCA0STE/A5/CA5/TMS | bidirectional | General-purpose digital I/O with Timer0_A Out0 output, USCI_B0 clock input/output, USCI_A0 slave transmit enable, ADC10 analog input A5 (MSP430G2x53 only), Comparator_A+ input CA5, and JTAG test mode select TMS; also the BSL data-receive pin. |
| 8 | P2.0/TA1.0 | bidirectional | General-purpose digital I/O with Timer1_A3 CCI0A input or Out0 output. |
| 9 | P2.1/TA1.1 | bidirectional | General-purpose digital I/O with Timer1_A3 CCI1A input or Out1 output. |
| 10 | P2.2/TA1.1 | bidirectional | General-purpose digital I/O with Timer1_A3 CCI1B input or Out1 output. |
| 11 | P2.3/TA1.0 | bidirectional | General-purpose digital I/O with Timer1_A3 CCI0B input or Out0 output. |
| 12 | P2.4/TA1.2 | bidirectional | General-purpose digital I/O with Timer1_A3 CCI2A input or Out2 output. |
| 13 | P2.5/TA1.2 | bidirectional | General-purpose digital I/O with Timer1_A3 CCI2B input or Out2 output. |
| 14 | P1.6/TA0.1/UCB0SOMI/UCB0SCL/A6/CA6/TDI/TCLK | bidirectional | General-purpose digital I/O with Timer0_A Out1 output, USCI_B0 SPI slave-out/master-in or I2C SCL clock, ADC10 analog input A6 (MSP430G2x53 only), Comparator_A+ input CA6, and JTAG test data input or test clock input during programming and test. |
| 15 | P1.7/CAOUT/UCB0SIMO/UCB0SDA/A7/CA7/TDO/TDI | bidirectional | General-purpose digital I/O with Comparator_A+ output CAOUT, USCI_B0 SPI slave-in/master-out or I2C SDA data, ADC10 analog input A7 (MSP430G2x53 only), Comparator_A+ input CA7, and JTAG test data output TDO or test data input TDI during programming and test. |
| 16 | RST/NMI/SBWTDIO | input | Reset input, nonmaskable interrupt input, and Spy-Bi-Wire test data input/output during programming and test. |
| 17 | TEST/SBWTCK | input | Selects the test mode for the Port 1 JTAG pins, with the device protection fuse connected to TEST, and serves as the Spy-Bi-Wire test clock input during programming and test. |
| 18 | XOUT/P2.7 | bidirectional | Crystal oscillator output terminal, or general-purpose digital I/O P2.7; if used as an input, excessive current flows until P2SEL.7 is cleared because the oscillator output driver is connected to the pad after reset. |
| 19 | XIN/P2.6/TA0.1 | bidirectional | Crystal oscillator input terminal, or general-purpose digital I/O P2.6 with Timer0_A Out1 output. |
| 20 | DVSS | power_in | Digital ground reference. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-20 |
| Category | Embedded Processors & Controllers |
| Pins | 20 |
CAD (KiCad official)
- Symbol:
MSP430G2553IPW20 - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files:
msp430g2553ipw20-etched.step/msp430g2553ipw20-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);msp430g2553ipw20.step/msp430g2553ipw20.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (88 pp, sha256
6b2ec0d3ff2ce347, retrieved 2026-10-10, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).