# MSP430G2553IPW0RQ1

**Texas Instruments** · Microcontrollers (MCU/MPU/SOC) · TSSOP-20

MSP430G2553IPW0RQ1 from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DVCC | power_in | Digital supply voltage; the Features list gives the low supply-voltage range as 1.8 V to 3.6 V. |
| 2 | P1.0/TA0CLK/ACLK/A0/CA0 | bidirectional | General-purpose digital I/O P1.0, also Timer0_A TACLK input, ACLK output, ADC10 analog input A0 and Comparator_A+ input CA0. |
| 3 | P1.1/TA0.0/UCA0RXD/UCA0SOMI/A1/CA1 | bidirectional | General-purpose digital I/O P1.1, also Timer0_A CCI0A capture / Out0 compare, USCI_A0 UART receive data input or SPI slave out/master in, ADC10 input A1 and comparator input CA1. |
| 4 | P1.2/TA0.1/UCA0TXD/UCA0SIMO/A2/CA2 | bidirectional | General-purpose digital I/O P1.2, also Timer0_A CCI1A capture / Out1 compare, USCI_A0 UART transmit data output or SPI slave in/master out, ADC10 input A2 and comparator input CA2. |
| 5 | P1.3/ADC10CLK/CAOUT/VREF-/VEREF-/A3/CA3 | bidirectional | General-purpose digital I/O P1.3, also ADC10 conversion clock output, ADC10 input A3, ADC10 negative reference VREF-/VEREF-, comparator input CA3 and Comparator_A+ output CAOUT. |
| 6 | P1.4/SMCLK/UCB0STE/UCA0CLK/VREF+/VEREF+/A4/CA4/TCK | bidirectional | General-purpose digital I/O P1.4, also SMCLK output, USCI_B0 slave transmit enable, USCI_A0 clock input/output, ADC10 input A4, ADC10 positive reference VREF+/VEREF+, comparator input CA4 and JTAG test clock TCK for device programming and test. |
| 7 | P1.5/TA0.0/UCB0CLK/UCA0STE/A5/CA5/TMS | bidirectional | General-purpose digital I/O P1.5, also Timer0_A compare Out0, USCI_B0 clock input/output, USCI_A0 slave transmit enable, ADC10 input A5, comparator input CA5 and JTAG test mode select TMS. |
| 8 | P2.0/TA1.0 | bidirectional | General-purpose digital I/O P2.0, also Timer1_A CCI0A capture input and Out0 compare output. |
| 9 | P2.1/TA1.1 | bidirectional | General-purpose digital I/O P2.1, also Timer1_A CCI1A capture input and Out1 compare output. |
| 10 | P2.2/TA1.1 | bidirectional | General-purpose digital I/O P2.2, also Timer1_A CCI1B capture input and Out1 compare output. |
| 11 | P2.3/TA1.0 | bidirectional | General-purpose digital I/O P2.3, also Timer1_A CCI0B capture input and Out0 compare output. |
| 12 | P2.4/TA1.2 | bidirectional | General-purpose digital I/O P2.4, also Timer1_A CCI2A capture input and Out2 compare output. |
| 13 | P2.5/TA1.2 | bidirectional | General-purpose digital I/O P2.5, also Timer1_A CCI2B capture input and Out2 compare output. |
| 14 | P1.6/TA0.1/A6/CA6/UCB0SOMI/UCB0SCL/TDI/TCLK | bidirectional | General-purpose digital I/O P1.6, also Timer0_A compare Out1, ADC10 input A6, comparator input CA6, USCI_B0 SPI slave out/master in or I2C SCL, and JTAG TDI/TCLK input during programming and test. |
| 15 | P1.7/CAOUT/A7/CA7/UCB0SIMO/UCB0SDA/TDO/TDI | bidirectional | General-purpose digital I/O P1.7, also Comparator_A+ output CAOUT, ADC10 input A7, comparator input CA7, USCI_B0 SPI slave in/master out or I2C SDA, and JTAG TDO/TDI terminal during programming and test. |
| 16 | RST/NMI/SBWTDIO | input | Device reset, nonmaskable interrupt input (NMI), and Spy-Bi-Wire test data input/output during programming and test. |
| 17 | TEST/SBWTCK | input | Selects test mode for the JTAG pins on Port 1; the device protection fuse is connected to TEST, and it is the Spy-Bi-Wire test clock input during programming and test. |
| 18 | XOUT/P2.7 | bidirectional | Output terminal of the crystal oscillator, also general-purpose digital I/O P2.7; if used as an input, excess current flows until P2SEL.7 is cleared because the oscillator output driver is connected after reset. |
| 19 | XIN/P2.6/TA0.1 | bidirectional | Input terminal of the crystal oscillator, also general-purpose digital I/O P2.6 with Timer0_A compare Out1 output. |
| 20 | DVSS | power_in | Ground reference for the digital supply. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-20 |
| Category | Embedded Processors & Controllers |
| Pins | 20 |

## CAD (KiCad official)

- Symbol: `MSP430G2553IPW0RQ1`
- Footprint: `Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm`
- 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files: `msp430g2553ipw0rq1-etched.step` / `msp430g2553ipw0rq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `msp430g2553ipw0rq1.step` / `msp430g2553ipw0rq1.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/msp430g2553-q1) (69 pp, sha256 `2680991a33f1b05c`, retrieved 2026-10-07, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/msp430g2553ipw0rq1-datasheet.pdf)