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MSP430G2452IPW20R
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMSP430G2452IPW20R
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · TSSOP-20
MSP430G2452IPW20R from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DVCC | power_in | Digital supply voltage, 1.8 V to 3.6 V nominal. |
| 2 | P1.0/TA0CLK/ACLK/A0/CA0 | bidirectional | Port 1 bit 0, general-purpose digital I/O pin; Timer0_A clock input (TA0CLK); ACLK output; ADC10 analog input A0 (MSP430G2x52 only); Comparator_A+ input CA0. |
| 3 | P1.1/TA0.0/A1/CA1 | bidirectional | Port 1 bit 1, general-purpose digital I/O pin; Timer0_A capture/compare signal (TA0.0); ADC10 analog input A1 (MSP430G2x52 only); Comparator_A+ input CA1. |
| 4 | P1.2/TA0.1/A2/CA2 | bidirectional | Port 1 bit 2, general-purpose digital I/O pin; Timer0_A capture/compare signal (TA0.1); ADC10 analog input A2 (MSP430G2x52 only); Comparator_A+ input CA2. |
| 5 | P1.3/ADC10CLK/CAOUT/A3/VREF-/VEREF-/CA3 | bidirectional | Port 1 bit 3, general-purpose digital I/O pin; ADC10 conversion clock output (MSP430G2x52 only); Comparator_A+ output (CAOUT); ADC10 analog input A3 or negative reference input (MSP430G2x52 only); Comparator_A+ input CA3. |
| 6 | P1.4/SMCLK/TA0.2/A4/VREF+/VEREF+/CA4/TCK | bidirectional | Port 1 bit 4, general-purpose digital I/O pin; SMCLK output; Timer0_A capture/compare signal (TA0.2); ADC10 analog input A4 or positive reference output (MSP430G2x52 only); Comparator_A+ input CA4; JTAG test clock input (TCK). |
| 7 | P1.5/TA0.0/SCLK/A5/CA5/TMS | bidirectional | Port 1 bit 5, general-purpose digital I/O pin; Timer0_A compare output (TA0.0); USI serial clock input/output in SPI mode or clock input in I2C mode (SCLK); ADC10 analog input A5 (MSP430G2x52 only); Comparator_A+ input CA5; JTAG test mode select input (TMS). |
| 8 | P2.0 | bidirectional | Port 2 bit 0, general-purpose digital I/O pin with configurable pullup/pulldown resistor. |
| 9 | P2.1 | bidirectional | Port 2 bit 1, general-purpose digital I/O pin with configurable pullup/pulldown resistor. |
| 10 | P2.2 | bidirectional | Port 2 bit 2, general-purpose digital I/O pin with configurable pullup/pulldown resistor. |
| 11 | P2.3 | bidirectional | Port 2 bit 3, general-purpose digital I/O pin with configurable pullup/pulldown resistor. |
| 12 | P2.4 | bidirectional | Port 2 bit 4, general-purpose digital I/O pin with configurable pullup/pulldown resistor. |
| 13 | P2.5 | bidirectional | Port 2 bit 5, general-purpose digital I/O pin with configurable pullup/pulldown resistor. |
| 14 | P1.6/TA0.1/SDO/SCL/A6/CA6/TDI/TCLK | bidirectional | Port 1 bit 6, general-purpose digital I/O pin; Timer0_A capture/compare signal (TA0.1); USI serial data output in SPI mode (SDO) or I2C clock line in I2C mode (SCL); ADC10 analog input A6 (MSP430G2x52 only); Comparator_A+ input CA6; JTAG test data input or test clock input during programming (TDI/TCLK). |
| 15 | P1.7/CAOUT/SDI/SDA/A7/CA7/TDO/TDI | bidirectional | Port 1 bit 7, general-purpose digital I/O pin; Comparator_A+ output (CAOUT); USI serial data input in SPI mode (SDI) or I2C data line in I2C mode (SDA); ADC10 analog input A7 (MSP430G2x52 only); Comparator_A+ input CA7; JTAG test data output or test data input terminal (TDO/TDI). |
| 16 | RST/NMI/SBWTDIO | input | Reset input, nonmaskable interrupt (NMI) input; Spy-Bi-Wire test data input/output terminal during programming and test; minimum reset pulse width of 2 µs. |
| 17 | TEST/SBWTCK | input | Test mode select for JTAG pins on port 1; device protection fuse connection; Spy-Bi-Wire test clock input during programming and test. |
| 18 | XOUT/P2.7 | output | Crystal oscillator output terminal or Port 2 bit 7 general-purpose I/O pin; excess current flows if XOUT/P2.7 is used as input until P2SEL.7 is cleared. |
| 19 | XIN/P2.6/TA0.1 | input | Crystal oscillator input terminal or Port 2 bit 6 general-purpose I/O pin; Timer0_A compare output (TA0.1). |
| 20 | DVSS | power_in | Digital ground reference (0 V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-20 |
| Category | Embedded Processors & Controllers |
| Pins | 20 |
CAD (KiCad official)
- Symbol:
MSP430G2452IPW20R - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files:
msp430g2452ipw20r-etched.step/msp430g2452ipw20r-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);msp430g2452ipw20r.step/msp430g2452ipw20r.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (78 pp, sha256
213d8b0d2e936702, retrieved 2026-09-24, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).