component
MSP430G2231IPW14R
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 3d ago |
| viewers | 8d ago |
| msp430g2231ipw14r-etched.fit.json | 3d ago |
| msp430g2231ipw14r-etched.glb | 3d ago |
| msp430g2231ipw14r-etched.step | 3d ago |
| msp430g2231ipw14r.glb | 8d ago |
| msp430g2231ipw14r.kicad_mod | 8d ago |
| msp430g2231ipw14r.kicad_sym | 8d ago |
| msp430g2231ipw14r.lbr | 8d ago |
| msp430g2231ipw14r.step | 8d ago |
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| README.md | 8d ago |
MSP430G2231IPW14R
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · TSSOP-14
MSP430G2231IPW14R from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DVCC | power_in | Digital power supply voltage (1.8 V to 3.6 V during program execution; 2.2 V to 3.6 V during flash memory programming). |
| 2 | P1.0/TA0CLK/ACLK/A0 | bidirectional | General-purpose digital I/O pin; alternate functions include Timer0_A clock signal input (TA0CLK), auxiliary clock signal output (ACLK), or ADC10 analog input channel A0. |
| 3 | P1.1/TA0.0/A1 | bidirectional | General-purpose digital I/O pin; alternate functions include Timer0_A capture input CCI0A or compare output Out0, or ADC10 analog input channel A1. |
| 4 | P1.2/TA0.1/A2 | bidirectional | General-purpose digital I/O pin; alternate functions include Timer0_A capture input CCI1A or compare output Out1, or ADC10 analog input channel A2. |
| 5 | P1.3/ADC10CLK/A3/VREF-/VEREF- | bidirectional | General-purpose digital I/O pin; alternate functions include ADC10 conversion clock output, ADC10 analog input channel A3, or ADC10 negative reference voltage (VREF- or VEREF-). |
| 6 | P1.4/SMCLK/A4/VREF+/VEREF+/TCK | bidirectional | General-purpose digital I/O pin; alternate functions include subsystem master clock signal output (SMCLK), ADC10 analog input channel A4, ADC10 positive reference voltage (VREF+ or VEREF+), or JTAG test clock input (TCK) during device programming and testing. |
| 7 | P1.5/TA0.0/A5/SCLK/TMS | bidirectional | General-purpose digital I/O pin; alternate functions include Timer0_A compare output Out0, ADC10 analog input channel A5, USI serial clock (SCLK) in I2C or SPI mode, or JTAG test mode select input (TMS) during device programming and testing. |
| 8 | P1.6/TA0.1/A6/SDO/SCL/TDI/TCLK | bidirectional | General-purpose digital I/O pin; alternate functions include Timer0_A capture input CCI1A or compare output Out1, ADC10 analog input channel A6, USI SPI serial data output (SDO) or I2C clock (SCL), or JTAG test data input (TDI) or test clock input (TCLK) during device programming and testing. |
| 9 | P1.7/A7/SDI/SDA/TDO/TDI | bidirectional | General-purpose digital I/O pin; alternate functions include ADC10 analog input channel A7, USI SPI serial data input (SDI) or I2C data (SDA), or JTAG test data output (TDO) or test data input (TDI) during device programming and testing. |
| 10 | RST/NMI/SBWTDIO | input | Reset input pin with non-maskable interrupt (NMI) capability; also serves as Spy-Bi-Wire two-wire test data input/output (SBWTDIO) during device programming and testing. |
| 11 | TEST/SBWTCK | input | Test mode select input pin for JTAG pins on port 1 (device protection fuse connected); also serves as Spy-Bi-Wire two-wire test clock input (SBWTCK) during device programming and testing. |
| 12 | XOUT/P2.7 | output | Crystal oscillator output pin; can also function as general-purpose digital I/O pin (P2.7) or Timer0_A compare output, but excessive current will occur if used as input before P2SEL.7 is cleared due to oscillator output driver connection after reset. |
| 13 | XIN/P2.6/TA0.1 | input | Crystal oscillator input pin (32768 Hz watch crystal or external digital clock source); can also function as general-purpose digital I/O pin (P2.6) or Timer0_A compare output. |
| 14 | DVSS | power_in | Digital ground reference (negative power supply reference for core logic). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-14 |
| Category | Embedded Processors & Controllers |
| Pins | 14 |
CAD (KiCad official)
- Symbol:
MSP430G2231IPW14R - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
msp430g2231ipw14r-etched.step/msp430g2231ipw14r-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);msp430g2231ipw14r.step/msp430g2231ipw14r.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (65 pp, sha256
ef4532c802ec17fb, retrieved 2026-09-27, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-4-6(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).