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MSP430FR6989IPNR

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Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-80(12x12). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MSP430FR6989IPNR

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-80(12x12)

MSP430FR6989IPNR from Texas Instruments, in a LQFP-80(12x12). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P4.3/UCA0SOMI/UCA0RXD/UCB1STE bidirectional General-purpose digital I/O, also USCI_A0 SPI slave-out/master-in or UART receive and USCI_B1 SPI slave transmit enable.
2 P1.4/UCB0CLK/UCA0STE/TA1.0/S3 bidirectional General-purpose digital I/O, also USCI_B0 SPI clock, USCI_A0 slave transmit enable, Timer_A TA1 CCR0 capture/compare, and LCD segment S3.
3 P1.5/UCB0STE/UCA0CLK/TA0.0/S2 bidirectional General-purpose digital I/O, also USCI_B0 SPI slave transmit enable, USCI_A0 SPI clock, Timer_A TA0 CCR0 capture/compare, and LCD segment S2.
4 P1.6/UCB0SIMO/UCB0SDA/TA0.1/S1 bidirectional General-purpose digital I/O, also USCI_B0 SPI master-out/slave-in or I2C data, BSL data for I2C BSL devices, Timer_A TA0 CCR1, and LCD segment S1.
5 P1.7/UCB0SOMI/UCB0SCL/TA0.2/S0 bidirectional General-purpose digital I/O, also USCI_B0 SPI slave-out/master-in or I2C clock, BSL clock for I2C BSL devices, Timer_A TA0 CCR2, and LCD segment S0.
6 R33/LCDCAP bidirectional Input/output port of the most positive analog LCD voltage (V1) and LCD capacitor connection; if unused it may be tied to DVSS or DVCC.
7 P6.0/R23 bidirectional General-purpose digital I/O, also input/output port of the second most positive analog LCD voltage (V2).
8 P6.1/R13/LCDREF bidirectional General-purpose digital I/O, also input/output port of the third most positive LCD voltage (V3 or V4) and external reference input for the regulated LCD voltage.
9 P6.2/COUT/R03 bidirectional General-purpose digital I/O, also comparator output (COUT) and input/output port of the lowest analog LCD voltage (V5).
10 P6.3/COM0 bidirectional General-purpose digital I/O, also LCD common output COM0 for the LCD backplane.
11 P6.4/TB0.0/COM1/S36 bidirectional General-purpose digital I/O, also Timer_B TB0 CCR0 capture/compare, LCD common output COM1, and LCD segment S36.
12 P6.5/TB0.1/COM2/S35 bidirectional General-purpose digital I/O, also Timer_B TB0 CCR1 capture/compare, LCD common output COM2, and LCD segment S35.
13 P6.6/TB0.2/COM3/S34 bidirectional General-purpose digital I/O, also Timer_B TB0 CCR2 capture/compare, LCD common output COM3, and LCD segment S34.
14 P2.4/TB0.3/COM4/S33 bidirectional General-purpose digital I/O, also Timer_B TB0 CCR3 capture/compare, LCD common output COM4, and LCD segment S33.
15 P2.5/TB0.4/COM5/S32 bidirectional General-purpose digital I/O, also Timer_B TB0 CCR4 capture/compare, LCD common output COM5, and LCD segment S32.
16 P2.6/TB0.5/ESIC1OUT/COM6/S31 bidirectional General-purpose digital I/O, also Timer_B TB0 CCR5 capture/compare, ESI comparator 1 output, LCD common output COM6, and LCD segment S31.
17 P2.7/TB0.6/ESIC2OUT/COM7/S30 bidirectional General-purpose digital I/O, also Timer_B TB0 CCR6 capture/compare, ESI comparator 2 output, LCD common output COM7, and LCD segment S30.
18 P3.0/UCB1CLK/S29 bidirectional General-purpose digital I/O, also USCI_B1 SPI clock (slave input or master output) and LCD segment S29.
19 P3.1/UCB1SIMO/UCB1SDA/S28 bidirectional General-purpose digital I/O, also USCI_B1 SPI master-out/slave-in or I2C data, and LCD segment S28.
20 P3.2/UCB1SOMI/UCB1SCL/S27 bidirectional General-purpose digital I/O, also USCI_B1 SPI slave-out/master-in or I2C clock, and LCD segment S27.
21 DVSS1 power_in Digital ground supply; connect to VSS.
22 DVCC1 power_in Digital power supply, 1.8 V to 3.6 V recommended operating range, decoupled with 1 µF plus 100 nF low-ESR capacitors.
23 TEST/SBWTCK input Test mode pin selecting digital I/O on JTAG pins and Spy-Bi-Wire input clock; it always has an internal pulldown enabled.
24 RST/NMI/SBWTDIO bidirectional Active-low reset input, nonmaskable interrupt input, and Spy-Bi-Wire data input/output; recommended termination is DVCC or VCC with 47 kΩ pullup or internal pullup.
25 PJ.0/TDO/TB0OUTH/SMCLK/SRSCG1 bidirectional General-purpose digital I/O, also JTAG test data output, Timer_B TB0 output-high-impedance control, SMCLK output, and low-power debug CPU status bit SCG1.
26 PJ.1/TDI/TCLK/MCLK/SRSCG0 bidirectional General-purpose digital I/O, also JTAG test data input or test clock, MCLK output, and low-power debug CPU status bit SCG0.
27 PJ.2/TMS/ACLK/SROSCOFF bidirectional General-purpose digital I/O, also JTAG test mode select, ACLK output, and low-power debug CPU status bit OSCOFF.
28 PJ.3/TCK/COUT/SRCPUOFF bidirectional General-purpose digital I/O, also JTAG test clock, comparator output, and low-power debug CPU status bit CPUOFF.
29 P6.7/TA0CLK/S26 bidirectional General-purpose digital I/O, also Timer_A TA0 clock input (TA0CLK) and LCD segment S26.
30 P7.5/TA0.2/S25 bidirectional General-purpose digital I/O, also Timer_A TA0 CCR2 capture/compare and LCD segment S25.
31 P7.6/TA0.1/S24 bidirectional General-purpose digital I/O, also Timer_A TA0 CCR1 capture/compare and LCD segment S24.
32 P7.7/TA1.2/TB0OUTH/S23 bidirectional General-purpose digital I/O, also Timer_A TA1 CCR2 capture/compare, Timer_B TB0 output-high-impedance control, and LCD segment S23.
33 P3.3/TA1.1/TB0CLK/S22 bidirectional General-purpose digital I/O, also Timer_A TA1 CCR1 capture/compare, Timer_B TB0 clock input (TB0CLK), and LCD segment S22.
34 P3.4/UCA1SIMO/UCA1TXD/TB0.0/S21 bidirectional General-purpose digital I/O, also USCI_A1 SPI master-out/slave-in or UART transmit, Timer_B TB0 CCR0 capture/compare, and LCD segment S21.
35 P3.5/UCA1SOMI/UCA1RXD/TB0.1/S20 bidirectional General-purpose digital I/O, also USCI_A1 SPI slave-out/master-in or UART receive, Timer_B TB0 CCR1 capture/compare, and LCD segment S20.
36 P3.6/UCA1CLK/TB0.2/S19 bidirectional General-purpose digital I/O, also USCI_A1 SPI clock, Timer_B TB0 CCR2 capture/compare, and LCD segment S19.
37 P3.7/UCA1STE/TB0.3/S18 bidirectional General-purpose digital I/O, also USCI_A1 SPI slave transmit enable, Timer_B TB0 CCR3 capture/compare, and LCD segment S18.
38 P2.3/UCA0STE/TB0OUTH/S17 bidirectional General-purpose digital I/O, also USCI_A0 SPI slave transmit enable, Timer_B TB0 output-high-impedance control, and LCD segment S17.
39 P2.2/UCA0CLK/TB0.4/RTCCLK/S16 bidirectional General-purpose digital I/O, also USCI_A0 SPI clock, Timer_B TB0 CCR4 capture/compare, RTC clock output for calibration, and LCD segment S16.
40 P2.1/UCA0SOMI/UCA0RXD/TB0.5/DMAE0/S15 bidirectional General-purpose digital I/O, also USCI_A0 SPI slave-out/master-in or UART receive, UART BSL receive, Timer_B TB0 CCR5, DMA external trigger, and LCD segment S15.
41 P2.0/UCA0SIMO/UCA0TXD/TB0.6/TB0CLK/S14 bidirectional General-purpose digital I/O, also USCI_A0 SPI master-out/slave-in or UART transmit, UART BSL transmit, Timer_B TB0 CCR6, Timer_B TB0 clock input, and LCD segment S14.
42 P7.0/TA0CLK/S13 bidirectional General-purpose digital I/O, also Timer_A TA0 clock input (TA0CLK) and LCD segment S13.
43 P7.1/TA0.0/ACLK/S12 bidirectional General-purpose digital I/O, also Timer_A TA0 CCR0 capture/compare, ACLK output, and LCD segment S12.
44 P7.2/TA0.1/S11 bidirectional General-purpose digital I/O, also Timer_A TA0 CCR1 capture/compare and LCD segment S11.
45 P7.3/TA0.2/S10 bidirectional General-purpose digital I/O, also Timer_A TA0 CCR2 capture/compare and LCD segment S10.
46 DVSS2 power_in Digital ground supply; connect to VSS.
47 DVCC2 power_in Digital power supply, 1.8 V to 3.6 V recommended operating range, decoupled with 1 µF plus 100 nF low-ESR capacitors.
48 P1.3/TA1.2/ESITEST4/A3/C3 bidirectional General-purpose digital I/O, also ESI test signal 4, Timer_A TA1 CCR2 capture/compare, ADC analog input A3, and comparator input C3.
49 P1.2/TA1.1/TA0CLK/COUT/A2/C2 bidirectional General-purpose digital I/O, also Timer_A TA1 CCR1 capture/compare, Timer_A TA0 clock input, comparator output, ADC analog input A2, and comparator input C2.
50 P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+ bidirectional General-purpose digital I/O, also Timer_A TA0 CCR2, Timer_A TA1 clock input, comparator output, ADC analog input A1, comparator input C1, and positive reference voltage output or external positive reference input.
51 P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/VREF-/VeREF- bidirectional General-purpose digital I/O, also Timer_A TA0 CCR1 capture/compare, DMA external trigger, RTC clock output for calibration, ADC analog input A0, comparator input C0, and negative reference voltage output or external negative reference input.
52 P9.0/ESICH0/ESITEST0/A8/C8 bidirectional General-purpose digital I/O, also ESI channel 0 sensor excitation output and signal input, ESI test signal 0, ADC analog input A8, and comparator input C8.
53 P9.1/ESICH1/ESITEST1/A9/C9 bidirectional General-purpose digital I/O, also ESI channel 1 sensor excitation output and signal input, ESI test signal 1, ADC analog input A9, and comparator input C9.
54 P9.2/ESICH2/ESITEST2/A10/C10 bidirectional General-purpose digital I/O, also ESI channel 2 sensor excitation output and signal input, ESI test signal 2, ADC analog input A10, and comparator input C10.
55 P9.3/ESICH3/ESITEST3/A11/C11 bidirectional General-purpose digital I/O, also ESI channel 3 sensor excitation output and signal input, ESI test signal 3, ADC analog input A11, and comparator input C11.
56 P9.4/ESICI0/A12/C12 bidirectional General-purpose digital I/O, also ESI channel 0 signal input to comparator, ADC analog input A12, and comparator input C12.
57 P9.5/ESICI1/A13/C13 bidirectional General-purpose digital I/O, also ESI channel 1 signal input to comparator, ADC analog input A13, and comparator input C13.
58 P9.6/ESICI2/A14/C14 bidirectional General-purpose digital I/O, also ESI channel 2 signal input to comparator, ADC analog input A14, and comparator input C14.
59 P9.7/ESICI3/A15/C15 bidirectional General-purpose digital I/O, also ESI channel 3 signal input to comparator, ADC analog input A15, and comparator input C15.
60 ESIDVCC power_in ESI power supply; TI recommends powering it from the same source as DVCC and AVCC, with decoupling as for DVCC.
61 ESIDVSS power_in ESI ground supply; connect to VSS.
62 ESICI input ESI scan interface input to the comparator; leave open if unused.
63 ESICOM passive ESI common termination for scan interface sensors; leave open if unused.
64 AVCC1 power_in Analog power supply, 1.8 V to 3.6 V recommended operating range, must not differ from DVCC by more than ±0.3 V.
65 AVSS3 power_in Analog ground supply; connect to VSS.
66 PJ.7/HFXOUT bidirectional General-purpose digital I/O, or output terminal of the high-frequency crystal oscillator XT2.
67 PJ.6/HFXIN bidirectional General-purpose digital I/O, or input terminal of the high-frequency crystal oscillator XT2 (also accepts a bypass clock in HFXT bypass mode).
68 AVSS1 power_in Analog ground supply; connect to VSS.
69 PJ.4/LFXIN bidirectional General-purpose digital I/O, or input terminal of the 32 kHz crystal oscillator XT1 (also accepts a bypass clock in LFXT bypass mode).
70 PJ.5/LFXOUT bidirectional General-purpose digital I/O, or output terminal of the 32 kHz crystal oscillator XT1.
71 AVSS2 power_in Analog ground supply; connect to VSS.
72 P4.4/UCB1STE/TA1CLK/S9 bidirectional General-purpose digital I/O, also USCI_B1 SPI slave transmit enable, Timer_A TA1 clock input, and LCD segment S9.
73 P4.5/UCB1CLK/TA1.0/S8 bidirectional General-purpose digital I/O, also USCI_B1 SPI clock, Timer_A TA1 CCR0 capture/compare, and LCD segment S8.
74 P4.6/UCB1SIMO/UCB1SDA/TA1.1/S7 bidirectional General-purpose digital I/O, also USCI_B1 SPI master-out/slave-in or I2C data, Timer_A TA1 CCR1 capture/compare, and LCD segment S7.
75 P4.7/UCB1SOMI/UCB1SCL/TA1.2/S6 bidirectional General-purpose digital I/O, also USCI_B1 SPI slave-out/master-in or I2C clock, Timer_A TA1 CCR2 capture/compare, and LCD segment S6.
76 P4.0/UCB1SIMO/UCB1SDA/MCLK/S5 bidirectional General-purpose digital I/O, also USCI_B1 SPI master-out/slave-in or I2C data, MCLK output, and LCD segment S5.
77 P4.1/UCB1SOMI/UCB1SCL/ACLK/S4 bidirectional General-purpose digital I/O, also USCI_B1 SPI slave-out/master-in or I2C clock, ACLK output, and LCD segment S4.
78 DVSS3 power_in Digital ground supply; connect to VSS.
79 DVCC3 power_in Digital power supply, 1.8 V to 3.6 V recommended operating range, decoupled with 1 µF plus 100 nF low-ESR capacitors.
80 P4.2/UCA0SIMO/UCA0TXD/UCB1CLK bidirectional General-purpose digital I/O, also USCI_A0 SPI master-out/slave-in or UART transmit, and USCI_B1 SPI clock.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-80(12x12)
Category Embedded Processors & Controllers
Pins 80

CAD (KiCad official)

  • Symbol: MSP430FR6989IPNR
  • Footprint: Package_QFP:LQFP-80_12x12mm_P0.5mm
  • 3D model: LQFP-80(12x12) (KiCad packages3D, STEP)
  • 3D model files: msp430fr6989ipnr-etched.step / msp430fr6989ipnr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); msp430fr6989ipnr.step / msp430fr6989ipnr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (190 pp, sha256 868055019a26de9e, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF