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MSP430FR6970IPMR
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMSP430FR6970IPMR
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)
MSP430FR6970IPMR from Texas Instruments, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P4.3/UCA0SOMI/UCA0RXD/UCB1STE/S4 | bidirectional | General-purpose digital I/O on DVCC (LVCMOS, 3.0 V nominal) with reset state OFF, multiplexed with USCI_A0 and USCI_B1 functions and LCD segment S4. |
| 2 | P1.4/UCB0CLK/UCA0STE/TA1.0/S3 | bidirectional | General-purpose digital I/O on DVCC (LVCMOS) with reset state OFF, multiplexed with USCI_B0/USCI_A0 and Timer_A1 functions and LCD segment S3. |
| 3 | P1.5/UCB0STE/UCA0CLK/TA0.0/S2 | bidirectional | General-purpose digital I/O on DVCC (LVCMOS) with reset state OFF, multiplexed with USCI_B0/USCI_A0 and Timer_A0 functions and LCD segment S2. |
| 4 | P1.6/UCB0SIMO/UCB0SDA/TA0.1/S1 | bidirectional | General-purpose digital I/O on DVCC (LVCMOS) with reset state OFF, multiplexed with USCI_B0 SIMO/SDA and Timer_A0 functions, LCD segment S1; also used as BSL_DAT on I2C BSL devices. |
| 5 | P1.7/UCB0SOMI/UCB0SCL/TA0.2/S0 | bidirectional | General-purpose digital I/O on DVCC (LVCMOS) with reset state OFF, multiplexed with USCI_B0 SOMI/SCL and Timer_A0 functions, LCD segment S0; also used as BSL_CLK on I2C BSL devices. |
| 6 | R33/LCDCAP | bidirectional | R33 is the most positive analog LCD voltage (V1) port; LCDCAP is the LCD charge-pump capacitor connection, and if unused the pin can be tied to DVSS or DVCC. |
| 7 | P6.0/R23 | bidirectional | General-purpose digital I/O on DVCC with reset state OFF, or analog LCD voltage port R23 (second most positive LCD voltage, V2). |
| 8 | P6.1/R13/LCDREF | bidirectional | General-purpose digital I/O with reset state OFF, or R13 analog LCD voltage port (V3 or V4), with LCDREF as external reference input for the regulated LCD voltage. |
| 9 | P6.2/COUT/R03 | bidirectional | General-purpose digital I/O with reset state OFF, or comparator output COUT, or R03 analog LCD port (lowest LCD voltage, V5). |
| 10 | P6.3/COM0 | bidirectional | General-purpose digital I/O with reset state OFF, or LCD common output COM0 for the LCD backplane. |
| 11 | P6.4/TB0.0/COM1/S30 | bidirectional | General-purpose digital I/O with reset state OFF, or Timer_B0 CCR0 capture/compare, LCD common output COM1, and LCD segment S30. |
| 12 | P6.5/TB0.1/COM2/S29 | bidirectional | General-purpose digital I/O with reset state OFF, or Timer_B0 CCR1 capture/compare, LCD common output COM2, and LCD segment S29. |
| 13 | P6.6/TB0.2/COM3/S28 | bidirectional | General-purpose digital I/O with reset state OFF, or Timer_B0 CCR2 capture/compare, LCD common output COM3, and LCD segment S28. |
| 14 | P3.0/UCB1CLK/TA3.2/S27 | bidirectional | General-purpose digital I/O with reset state OFF, multiplexed with USCI_B1 clock, Timer_A3 CCR2, and LCD segment S27. |
| 15 | P3.1/UCB1SIMO/UCB1SDA/TA3.3/S26 | bidirectional | General-purpose digital I/O with reset state OFF, multiplexed with USCI_B1 SIMO/SDA, Timer_A3 CCR3, and LCD segment S26. |
| 16 | P3.2/UCB1SOMI/UCB1SCL/TA3.4/S25 | bidirectional | General-purpose digital I/O with reset state OFF, multiplexed with USCI_B1 SOMI/SCL, Timer_A3 CCR4, and LCD segment S25. |
| 17 | DVSS1 | power_in | Digital ground supply (VSS = 0 V reference for all DVSS and AVSS pins). |
| 18 | DVCC1 | power_in | Digital power supply; VCC is specified from 1.8 V to 3.6 V at all DVCC and AVCC pins, with a 1 µF plus 100 nF decoupling pair recommended per supply. |
| 19 | TEST/SBWTCK | input | Test mode pin that selects digital I/O on the JTAG pins and also carries the Spy-Bi-Wire clock; it always has an internal pulldown enabled and should be left open when unused. |
| 20 | RST/NMI/SBWTDIO | bidirectional | Active-low reset input (RST), configurable as nonmaskable interrupt input (NMI), and carrying Spy-Bi-Wire data input/output; typically pulled up to DVCC with 47 kΩ or the internal pullup. |
| 21 | PJ.0/TDO/TB0OUTH/SMCLK/SRSCG1 | bidirectional | General-purpose digital I/O (reset state OFF) that serves as JTAG test data output TDO, with alternate functions TB0OUTH, SMCLK output, and low-power debug signal SRSCG1. |
| 22 | PJ.1/TDI/TCLK/MCLK/SRSCG0 | bidirectional | General-purpose digital I/O (reset state OFF) that serves as JTAG test data input TDI/TCLK, with alternate functions MCLK output and low-power debug signal SRSCG0. |
| 23 | PJ.2/TMS/ACLK/SROSCOFF | bidirectional | General-purpose digital I/O (reset state OFF) that serves as JTAG test mode select TMS, with alternate functions ACLK output and low-power debug signal SROSCOFF. |
| 24 | PJ.3/TCK/COUT/SRCPUOFF | bidirectional | General-purpose digital I/O (reset state OFF) that serves as JTAG test clock TCK, with alternate functions COUT output and low-power debug signal SRCPUOFF. |
| 25 | P3.3/TA1.1/TB0CLK/S24 | bidirectional | General-purpose digital I/O with reset state OFF, multiplexed with Timer_A1 CCR1, Timer_B0 clock input, and LCD segment S24. |
| 26 | P3.4/UCA1SIMO/UCA1TXD/TB0.0/S23 | bidirectional | General-purpose digital I/O with reset state OFF, multiplexed with USCI_A1 SIMO/TXD, Timer_B0 CCR0, and LCD segment S23. |
| 27 | P3.5/UCA1SOMI/UCA1RXD/TB0.1/S22 | bidirectional | General-purpose digital I/O with reset state OFF, multiplexed with USCI_A1 SOMI/RXD, Timer_B0 CCR1, and LCD segment S22. |
| 28 | P3.6/UCA1CLK/TB0.2/S21 | bidirectional | General-purpose digital I/O with reset state OFF, multiplexed with USCI_A1 clock, Timer_B0 CCR2, and LCD segment S21. |
| 29 | P3.7/UCA1STE/TB0.3/S20 | bidirectional | General-purpose digital I/O with reset state OFF, multiplexed with USCI_A1 STE, Timer_B0 CCR3, and LCD segment S20. |
| 30 | P2.3/UCA0STE/TB0OUTH/S19 | bidirectional | General-purpose digital I/O with reset state OFF, multiplexed with USCI_A0 STE, the Timer_B0 all-outputs-high-impedance input TB0OUTH, and LCD segment S19. |
| 31 | P2.2/UCA0CLK/TB0.4/RTCCLK/S18 | bidirectional | General-purpose digital I/O with reset state OFF, multiplexed with USCI_A0 clock, Timer_B0 CCR4, RTC clock output RTCCLK, and LCD segment S18. |
| 32 | P2.1/UCA0SOMI/UCA0RXD/TB0.5/DMAE0/S17 | bidirectional | General-purpose digital I/O with reset state OFF, multiplexed with USCI_A0 SOMI/RXD, Timer_B0 CCR5, DMA external trigger DMAE0, and LCD segment S17; also BSL_RX on UART BSL devices. |
| 33 | P2.0/UCA0SIMO/UCA0TXD/TB0.6/TB0CLK/S16 | bidirectional | General-purpose digital I/O with reset state OFF, multiplexed with USCI_A0 SIMO/TXD, Timer_B0 CCR6 and clock, and LCD segment S16; also BSL_TX on UART BSL devices. |
| 34 | P7.0/TA0CLK/S15 | bidirectional | General-purpose digital I/O with reset state OFF, multiplexed with Timer_A0 clock input TA0CLK and LCD segment S15. |
| 35 | P7.1/TA0.0/ACLK/S14 | bidirectional | General-purpose digital I/O with reset state OFF, multiplexed with Timer_A0 CCR0, ACLK output, and LCD segment S14. |
| 36 | P7.2/TA0.1/S13 | bidirectional | General-purpose digital I/O with reset state OFF, multiplexed with Timer_A0 CCR1 and LCD segment S13. |
| 37 | P7.3/TA0.2/S12 | bidirectional | General-purpose digital I/O with reset state OFF, multiplexed with Timer_A0 CCR2 and LCD segment S12. |
| 38 | P7.4/SMCLK/S11 | bidirectional | General-purpose digital I/O with reset state OFF, multiplexed with SMCLK output and LCD segment S11. |
| 39 | DVSS2 | power_in | Digital ground supply (VSS = 0 V reference). |
| 40 | DVCC2 | power_in | Digital power supply; VCC is specified from 1.8 V to 3.6 V at all DVCC and AVCC pins, decoupled with 1 µF plus 100 nF. |
| 41 | P1.3/TA1.2/A3/C3 | bidirectional | General-purpose digital I/O with reset state OFF, or Timer_A1 CCR2, or ADC analog input A3 and comparator input C3 (AVCC supply). |
| 42 | P1.2/TA1.1/TA0CLK/COUT/A2/C2 | bidirectional | General-purpose digital I/O with reset state OFF, or Timer_A1 CCR1, Timer_A0 clock, comparator output COUT, ADC analog input A2, and comparator input C2. |
| 43 | P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+ | bidirectional | General-purpose digital I/O with reset state OFF, or Timer_A0 CCR2, Timer_A1 clock, COUT, ADC analog input A1, comparator input C1, positive reference output VREF+, or external positive reference input VeREF+. |
| 44 | P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/VREF-/VeREF- | bidirectional | General-purpose digital I/O with reset state OFF, or Timer_A0 CCR1, DMA trigger DMAE0, RTC clock output, ADC analog input A0, comparator input C0, negative reference output VREF-, or external negative reference input VeREF-. |
| 45 | P9.4/A12/C12 | bidirectional | General-purpose digital I/O with reset state OFF, or ADC analog input A12 and comparator input C12 (AVCC supply). |
| 46 | P9.5/A13/C13 | bidirectional | General-purpose digital I/O with reset state OFF, or ADC analog input A13 and comparator input C13 (AVCC supply). |
| 47 | P9.6/A14/C14 | bidirectional | General-purpose digital I/O with reset state OFF, or ADC analog input A14 and comparator input C14 (AVCC supply). |
| 48 | P9.7/A15/C15 | bidirectional | General-purpose digital I/O with reset state OFF, or ADC analog input A15 and comparator input C15 (AVCC supply). |
| 49 | AVCC1 | power_in | Analog power supply; VCC is specified from 1.8 V to 3.6 V and AVCC and DVCC should be powered from the same source, with their difference kept within ±0.3 V. |
| 50 | AVSS1 | power_in | Analog ground supply (VSS = 0 V reference). |
| 51 | PJ.4/LFXIN | input | Input terminal for the 32-kHz crystal oscillator XT1 (LFXIN), or bypass clock input when LFXTBYPASS is selected; otherwise general-purpose I/O PJ.4. |
| 52 | PJ.5/LFXOUT | output | Output terminal of the 32-kHz crystal oscillator XT1 (LFXOUT) in crystal mode, otherwise general-purpose I/O PJ.5. |
| 53 | AVSS2 | power_in | Analog ground supply (VSS = 0 V reference). |
| 54 | PJ.7/HFXOUT | output | Output terminal of the high-frequency crystal oscillator XT2 (HFXOUT) in crystal mode, otherwise general-purpose I/O PJ.7. |
| 55 | PJ.6/HFXIN | input | Input terminal of the high-frequency crystal oscillator XT2 (HFXIN), or bypass clock input when HFXTBYPASS is selected; otherwise general-purpose I/O PJ.6. |
| 56 | AVSS3 | power_in | Analog ground supply (VSS = 0 V reference). |
| 57 | P5.7/UCA1STE/TB0CLK/S10 | bidirectional | General-purpose digital I/O with reset state OFF, multiplexed with USCI_A1 STE, Timer_B0 clock input, and LCD segment S10. |
| 58 | P4.4/UCB1STE/TA1CLK/S9 | bidirectional | General-purpose digital I/O with reset state OFF, multiplexed with USCI_B1 STE, Timer_A1 clock input, and LCD segment S9. |
| 59 | P4.5/UCB1CLK/TA1.0/S8 | bidirectional | General-purpose digital I/O with reset state OFF, multiplexed with USCI_B1 clock, Timer_A1 CCR0, and LCD segment S8. |
| 60 | P4.6/UCB1SIMO/UCB1SDA/TA1.1/S7 | bidirectional | General-purpose digital I/O with reset state OFF, multiplexed with USCI_B1 SIMO/SDA, Timer_A1 CCR1, and LCD segment S7. |
| 61 | P4.7/UCB1SOMI/UCB1SCL/TA1.2/S6 | bidirectional | General-purpose digital I/O with reset state OFF, multiplexed with USCI_B1 SOMI/SCL, Timer_A1 CCR2, and LCD segment S6. |
| 62 | DVSS3 | power_in | Digital ground supply (VSS = 0 V reference). |
| 63 | DVCC3 | power_in | Digital power supply; VCC is specified from 1.8 V to 3.6 V at all DVCC and AVCC pins, decoupled with 1 µF plus 100 nF. |
| 64 | P4.2/UCA0SIMO/UCA0TXD/UCB1CLK/S5 | bidirectional | General-purpose digital I/O with reset state OFF, multiplexed with USCI_A0 SIMO/TXD, USCI_B1 clock, and LCD segment S5. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | LQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |
CAD (KiCad official)
- Symbol:
MSP430FR6970IPMR - Footprint:
Package_QFP:LQFP-64_10x10mm_P0.5mm - 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files:
msp430fr6970ipmr-etched.step/msp430fr6970ipmr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);msp430fr6970ipmr.step/msp430fr6970ipmr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (164 pp, sha256
acfa8c28f070a26c, retrieved 2026-10-11, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).