component
MSP430FR6820IPMR
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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MSP430FR6820IPMR
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)
MSP430FR6820IPMR from Texas Instruments, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P4.3 | bidirectional | General-purpose I/O P4.3 (reset state OFF after BOR) that also carries UCA0SOMI/UCA0RXD and UCB1STE functions, with LVCMOS levels referenced to DVCC. |
| 2 | P1.4 | bidirectional | General-purpose I/O P1.4 (reset state OFF) shared with UCB0CLK, UCA0STE and TA1.0 functions, with LVCMOS levels referenced to DVCC. |
| 3 | P1.5 | bidirectional | General-purpose I/O P1.5 (reset state OFF) shared with UCB0STE, UCA0CLK and TA0.0 functions. |
| 4 | P1.6 | bidirectional | General-purpose I/O P1.6 (reset state OFF) shared with UCB0SIMO/UCB0SDA and TA0.1 functions, and with BSL_DAT on devices with the I2C bootloader. |
| 5 | P1.7 | bidirectional | General-purpose I/O P1.7 (reset state OFF) shared with UCB0SOMI/UCB0SCL and TA0.2 functions, and with BSL_CLK on devices with the I2C bootloader. |
| 6 | R33/LCDCAP | bidirectional | Analog LCD voltage pin R33 (most positive LCD voltage V1) that is also the LCD charge-pump capacitor connection LCDCAP; if unused it can be tied to DVSS or DVCC. |
| 7 | P6.0/R23 | bidirectional | General-purpose I/O P6.0 (reset state OFF) that also serves as analog LCD voltage pin R23 (second most positive LCD voltage V2). |
| 8 | P6.1/R13/LCDREF | bidirectional | General-purpose I/O P6.1 (reset state OFF) that also serves as analog LCD voltage pin R13 (V3 or V4) and as the external reference input LCDREF for the regulated LCD voltage. |
| 9 | P6.2/COUT/R03 | bidirectional | General-purpose I/O P6.2 (reset state OFF) that also carries the comparator output COUT and analog LCD voltage pin R03 (lowest LCD voltage V5). |
| 10 | P6.3/COM0 | bidirectional | General-purpose I/O P6.3 (reset state OFF) that is also LCD common output COM0 for the LCD backplane. |
| 11 | P6.4/TB0.0/COM1/S31 | bidirectional | General-purpose I/O P6.4 (reset state OFF) with Timer_B TB0.0 and LCD common output COM1 functions, and LCD segment S31 on this package. |
| 12 | P6.5/TB0.1/COM2/S30 | bidirectional | General-purpose I/O P6.5 (reset state OFF) with Timer_B TB0.1 and LCD common output COM2 functions, and LCD segment S30 on this package. |
| 13 | P6.6/TB0.2/COM3/S29 | bidirectional | General-purpose I/O P6.6 (reset state OFF) with Timer_B TB0.2 and LCD common output COM3 functions, and LCD segment S29 on this package. |
| 14 | P3.0/UCB1CLK/S28 | bidirectional | General-purpose I/O P3.0 (reset state OFF) with UCB1CLK function and LCD segment S28; TA3.2 is not available on this 64-pin FR692x/FR682x package. |
| 15 | P3.1/UCB1SIMO/UCB1SDA/S27 | bidirectional | General-purpose I/O P3.1 (reset state OFF) with UCB1SIMO/UCB1SDA function and LCD segment S27; TA3.3 is not available on this 64-pin package. |
| 16 | P3.2/UCB1SOMI/UCB1SCL/S26 | bidirectional | General-purpose I/O P3.2 (reset state OFF) with UCB1SOMI/UCB1SCL function and LCD segment S26; TA3.4 is not available on this 64-pin package. |
| 17 | DVSS1 | power_in | Digital ground supply for the digital I/O and core; connect to system VSS. |
| 18 | DVCC1 | power_in | Digital power supply; VCC is specified from 1.8 V to 3.6 V at all DVCC and AVCC pins and should be decoupled per the layout guidance. |
| 19 | TEST/SBWTCK | input | TEST pin selects digital I/O on the JTAG pins and always has an internal pulldown enabled; SBWTCK is the Spy-Bi-Wire input clock. |
| 20 | RST/NMI/SBWTDIO | input | Active-low reset input RST (also NMI and Spy-Bi-Wire data I/O SBWTDIO); a 47 kΩ pullup or internal pullup with a 10 nF (2.2 nF in Spy-Bi-Wire) pulldown is recommended. |
| 21 | PJ.0/TDO/TB0OUTH/SMCLK/SRSCG1 | bidirectional | Port PJ.0 (reset state OFF) that is the JTAG test data output TDO, and also carries TB0OUTH, SMCLK output and SRSCG1 functions. |
| 22 | PJ.1/TDI/TCLK/MCLK/SRSCG0 | bidirectional | Port PJ.1 (reset state OFF) that is the JTAG test data input TDI/TCLK, and also carries MCLK output and SRSCG0 functions; leave open when used for JTAG. |
| 23 | PJ.2/TMS/ACLK/SROSCOFF | bidirectional | Port PJ.2 (reset state OFF) that is the JTAG test mode select TMS, and also carries ACLK output and SROSCOFF functions; leave open when used for JTAG. |
| 24 | PJ.3/TCK/COUT/SRCPUOFF | bidirectional | Port PJ.3 (reset state OFF) that is the JTAG test clock TCK, and also carries COUT and SRCPUOFF functions; leave open when used for JTAG. |
| 25 | P3.3/TA1.1/TB0CLK/S25 | bidirectional | General-purpose I/O P3.3 (reset state OFF) with Timer_A TA1.1, Timer_B TB0CLK and LCD segment S25 functions. |
| 26 | P3.4/UCA1SIMO/UCA1TXD/TB0.0/S24 | bidirectional | General-purpose I/O P3.4 (reset state OFF) with UCA1SIMO/UCA1TXD, Timer_B TB0.0 and LCD segment S24 functions. |
| 27 | P3.5/UCA1SOMI/UCA1RXD/TB0.1/S23 | bidirectional | General-purpose I/O P3.5 (reset state OFF) with UCA1SOMI/UCA1RXD, Timer_B TB0.1 and LCD segment S23 functions. |
| 28 | P3.6/UCA1CLK/TB0.2/S22 | bidirectional | General-purpose I/O P3.6 (reset state OFF) with UCA1CLK, Timer_B TB0.2 and LCD segment S22 functions. |
| 29 | P3.7/UCA1STE/TB0.3/S21 | bidirectional | General-purpose I/O P3.7 (reset state OFF) with UCA1STE, Timer_B TB0.3 and LCD segment S21 functions. |
| 30 | P2.3/UCA0STE/TB0OUTH/S20 | bidirectional | General-purpose I/O P2.3 (reset state OFF) with UCA0STE, TB0OUTH input (switches PWM outputs high impedance) and LCD segment S20 functions. |
| 31 | P2.2/UCA0CLK/TB0.4/RTCCLK/S19 | bidirectional | General-purpose I/O P2.2 (reset state OFF) with UCA0CLK, Timer_B TB0.4, RTC clock output RTCCLK and LCD segment S19 functions. |
| 32 | P2.1/UCA0SOMI/UCA0RXD/TB0.5/DMAE0/S18 | bidirectional | General-purpose I/O P2.1 (reset state OFF) with UCA0SOMI/UCA0RXD, TB0.5, DMA external trigger DMAE0 and LCD segment S18; on the UART-bootloader device this pin is BSL_RX. |
| 33 | P2.0/UCA0SIMO/UCA0TXD/TB0.6/TB0CLK/S17 | bidirectional | General-purpose I/O P2.0 (reset state OFF) with UCA0SIMO/UCA0TXD, TB0.6, TB0CLK and LCD segment S17 functions; on the UART-bootloader device this pin is BSL_TX. |
| 34 | P7.0/TA0CLK/S16 | bidirectional | General-purpose I/O P7.0 (reset state OFF) with Timer_A TA0CLK input and LCD segment S16 functions. |
| 35 | P7.1/TA0.0/ACLK/S15 | bidirectional | General-purpose I/O P7.1 (reset state OFF) with Timer_A TA0.0, ACLK output and LCD segment S15 functions. |
| 36 | P7.2/TA0.1/S14 | bidirectional | General-purpose I/O P7.2 (reset state OFF) with Timer_A TA0.1 and LCD segment S14 functions. |
| 37 | P7.3/TA0.2/S13 | bidirectional | General-purpose I/O P7.3 (reset state OFF) with Timer_A TA0.2 and LCD segment S13 functions. |
| 38 | P7.4/SMCLK/S12 | bidirectional | General-purpose I/O P7.4 (reset state OFF) with SMCLK output and LCD segment S12 functions. |
| 39 | DVSS2 | power_in | Digital ground supply; connect to system VSS. |
| 40 | DVCC2 | power_in | Digital power supply; VCC is specified from 1.8 V to 3.6 V at all DVCC and AVCC pins. |
| 41 | P1.3/TA1.2/A3/C3 | bidirectional | General-purpose I/O P1.3 (reset state OFF) with Timer_A TA1.2 function, ADC analog input A3 and comparator input C3. |
| 42 | P1.2/TA1.1/TA0CLK/COUT/A2/C2 | bidirectional | General-purpose I/O P1.2 (reset state OFF) with Timer_A TA1.1, TA0CLK, comparator output COUT, ADC input A2 and comparator input C2. |
| 43 | P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+ | bidirectional | General-purpose I/O P1.1 (reset state OFF) with Timer_A TA0.2, TA1CLK, COUT, ADC input A1, comparator input C1, reference output VREF+ and external positive reference input VeREF+. |
| 44 | P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/VREF-/VeREF- | bidirectional | General-purpose I/O P1.0 (reset state OFF) with Timer_A TA0.1, DMAE0, RTCCLK, ADC input A0, comparator input C0, reference output VREF- and external negative reference input VeREF-. |
| 45 | P9.4/A12/C12 | bidirectional | General-purpose I/O P9.4 (reset state OFF) with ADC analog input A12 and comparator input C12. |
| 46 | P9.5/A13/C13 | bidirectional | General-purpose I/O P9.5 (reset state OFF) with ADC analog input A13 and comparator input C13. |
| 47 | P9.6/A14/C14 | bidirectional | General-purpose I/O P9.6 (reset state OFF) with ADC analog input A14 and comparator input C14. |
| 48 | P9.7/A15/C15 | bidirectional | General-purpose I/O P9.7 (reset state OFF) with ADC analog input A15 and comparator input C15. |
| 49 | AVCC1 | power_in | Analog power supply; it should be sourced from the same supply as DVCC, and the AVCC-to-DVCC difference must stay within ±0.3 V. |
| 50 | AVSS1 | power_in | Analog ground supply; connect to system VSS. |
| 51 | PJ.4/LFXIN | bidirectional | Port PJ.4 that is the low-frequency crystal input LFXIN (32 kHz) in crystal mode or the bypass clock input in LFXTBYPASS mode, otherwise general-purpose I/O. |
| 52 | PJ.5/LFXOUT | bidirectional | Port PJ.5 that is the low-frequency crystal output LFXOUT in crystal mode, otherwise general-purpose I/O. |
| 53 | AVSS2 | power_in | Analog ground supply; connect to system VSS. |
| 54 | P5.4/UCA1SIMO/UCA1TXD/S11 | bidirectional | General-purpose I/O P5.4 (reset state OFF) with UCA1SIMO/UCA1TXD and LCD segment S11 functions. |
| 55 | P5.5/UCA1SOMI/UCA1RXD/S10 | bidirectional | General-purpose I/O P5.5 (reset state OFF) with UCA1SOMI/UCA1RXD and LCD segment S10 functions. |
| 56 | P5.6/UCA1CLK/S9 | bidirectional | General-purpose I/O P5.6 (reset state OFF) with UCA1CLK and LCD segment S9 functions. |
| 57 | P5.7/UCA1STE/TB0CLK/S8 | bidirectional | General-purpose I/O P5.7 (reset state OFF) with UCA1STE, TB0CLK and LCD segment S8 functions. |
| 58 | P4.4/UCB1STE/TA1CLK/S7 | bidirectional | General-purpose I/O P4.4 (reset state OFF) with UCB1STE, TA1CLK and LCD segment S7 functions. |
| 59 | P4.5/UCB1CLK/TA1.0/S6 | bidirectional | General-purpose I/O P4.5 (reset state OFF) with UCB1CLK, Timer_A TA1.0 and LCD segment S6 functions. |
| 60 | P4.6/UCB1SIMO/UCB1SDA/TA1.1/S5 | bidirectional | General-purpose I/O P4.6 (reset state OFF) with UCB1SIMO/UCB1SDA, Timer_A TA1.1 and LCD segment S5 functions. |
| 61 | P4.7/UCB1SOMI/UCB1SCL/TA1.2/S4 | bidirectional | General-purpose I/O P4.7 (reset state OFF) with UCB1SOMI/UCB1SCL, Timer_A TA1.2 and LCD segment S4 functions. |
| 62 | DVSS3 | power_in | Digital ground supply; connect to system VSS. |
| 63 | DVCC3 | power_in | Digital power supply; VCC is specified from 1.8 V to 3.6 V at all DVCC and AVCC pins. |
| 64 | P4.2/UCA0SIMO/UCA0TXD/UCB1CLK | bidirectional | General-purpose I/O P4.2 (reset state OFF) with UCA0SIMO/UCA0TXD and UCB1CLK functions; no LCD segment is assigned to this pin in the FR692x/FR682x 64-pin figure. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | LQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |
CAD (KiCad official)
- Symbol:
MSP430FR6820IPMR - Footprint:
Package_QFP:LQFP-64_10x10mm_P0.5mm - 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files:
msp430fr6820ipmr-etched.step/msp430fr6820ipmr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);msp430fr6820ipmr.step/msp430fr6820ipmr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (164 pp, sha256
acfa8c28f070a26c, retrieved 2026-10-11, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# MSP430FR6820IPMR
**Texas Instruments** · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)
MSP430FR6820IPMR from Texas Instruments, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P4.3 | bidirectional | General-purpose I/O P4.3 (reset state OFF after BOR) that also carries UCA0SOMI/UCA0RXD and UCB1STE functions, with LVCMOS levels referenced to DVCC. |
| 2 | P1.4 | bidirectional | General-purpose I/O P1.4 (reset state OFF) shared with UCB0CLK, UCA0STE and TA1.0 functions, with LVCMOS levels referenced to DVCC. |
| 3 | P1.5 | bidirectional | General-purpose I/O P1.5 (reset state OFF) shared with UCB0STE, UCA0CLK and TA0.0 functions. |
| 4 | P1.6 | bidirectional | General-purpose I/O P1.6 (reset state OFF) shared with UCB0SIMO/UCB0SDA and TA0.1 functions, and with BSL_DAT on devices with the I2C bootloader. |
| 5 | P1.7 | bidirectional | General-purpose I/O P1.7 (reset state OFF) shared with UCB0SOMI/UCB0SCL and TA0.2 functions, and with BSL_CLK on devices with the I2C bootloader. |
| 6 | R33/LCDCAP | bidirectional | Analog LCD voltage pin R33 (most positive LCD voltage V1) that is also the LCD charge-pump capacitor connection LCDCAP; if unused it can be tied to DVSS or DVCC. |
| 7 | P6.0/R23 | bidirectional | General-purpose I/O P6.0 (reset state OFF) that also serves as analog LCD voltage pin R23 (second most positive LCD voltage V2). |
| 8 | P6.1/R13/LCDREF | bidirectional | General-purpose I/O P6.1 (reset state OFF) that also serves as analog LCD voltage pin R13 (V3 or V4) and as the external reference input LCDREF for the regulated LCD voltage. |
| 9 | P6.2/COUT/R03 | bidirectional | General-purpose I/O P6.2 (reset state OFF) that also carries the comparator output COUT and analog LCD voltage pin R03 (lowest LCD voltage V5). |
| 10 | P6.3/COM0 | bidirectional | General-purpose I/O P6.3 (reset state OFF) that is also LCD common output COM0 for the LCD backplane. |
| 11 | P6.4/TB0.0/COM1/S31 | bidirectional | General-purpose I/O P6.4 (reset state OFF) with Timer_B TB0.0 and LCD common output COM1 functions, and LCD segment S31 on this package. |
| 12 | P6.5/TB0.1/COM2/S30 | bidirectional | General-purpose I/O P6.5 (reset state OFF) with Timer_B TB0.1 and LCD common output COM2 functions, and LCD segment S30 on this package. |
| 13 | P6.6/TB0.2/COM3/S29 | bidirectional | General-purpose I/O P6.6 (reset state OFF) with Timer_B TB0.2 and LCD common output COM3 functions, and LCD segment S29 on this package. |
| 14 | P3.0/UCB1CLK/S28 | bidirectional | General-purpose I/O P3.0 (reset state OFF) with UCB1CLK function and LCD segment S28; TA3.2 is not available on this 64-pin FR692x/FR682x package. |
| 15 | P3.1/UCB1SIMO/UCB1SDA/S27 | bidirectional | General-purpose I/O P3.1 (reset state OFF) with UCB1SIMO/UCB1SDA function and LCD segment S27; TA3.3 is not available on this 64-pin package. |
| 16 | P3.2/UCB1SOMI/UCB1SCL/S26 | bidirectional | General-purpose I/O P3.2 (reset state OFF) with UCB1SOMI/UCB1SCL function and LCD segment S26; TA3.4 is not available on this 64-pin package. |
| 17 | DVSS1 | power_in | Digital ground supply for the digital I/O and core; connect to system VSS. |
| 18 | DVCC1 | power_in | Digital power supply; VCC is specified from 1.8 V to 3.6 V at all DVCC and AVCC pins and should be decoupled per the layout guidance. |
| 19 | TEST/SBWTCK | input | TEST pin selects digital I/O on the JTAG pins and always has an internal pulldown enabled; SBWTCK is the Spy-Bi-Wire input clock. |
| 20 | RST/NMI/SBWTDIO | input | Active-low reset input RST (also NMI and Spy-Bi-Wire data I/O SBWTDIO); a 47 kΩ pullup or internal pullup with a 10 nF (2.2 nF in Spy-Bi-Wire) pulldown is recommended. |
| 21 | PJ.0/TDO/TB0OUTH/SMCLK/SRSCG1 | bidirectional | Port PJ.0 (reset state OFF) that is the JTAG test data output TDO, and also carries TB0OUTH, SMCLK output and SRSCG1 functions. |
| 22 | PJ.1/TDI/TCLK/MCLK/SRSCG0 | bidirectional | Port PJ.1 (reset state OFF) that is the JTAG test data input TDI/TCLK, and also carries MCLK output and SRSCG0 functions; leave open when used for JTAG. |
| 23 | PJ.2/TMS/ACLK/SROSCOFF | bidirectional | Port PJ.2 (reset state OFF) that is the JTAG test mode select TMS, and also carries ACLK output and SROSCOFF functions; leave open when used for JTAG. |
| 24 | PJ.3/TCK/COUT/SRCPUOFF | bidirectional | Port PJ.3 (reset state OFF) that is the JTAG test clock TCK, and also carries COUT and SRCPUOFF functions; leave open when used for JTAG. |
| 25 | P3.3/TA1.1/TB0CLK/S25 | bidirectional | General-purpose I/O P3.3 (reset state OFF) with Timer_A TA1.1, Timer_B TB0CLK and LCD segment S25 functions. |
| 26 | P3.4/UCA1SIMO/UCA1TXD/TB0.0/S24 | bidirectional | General-purpose I/O P3.4 (reset state OFF) with UCA1SIMO/UCA1TXD, Timer_B TB0.0 and LCD segment S24 functions. |
| 27 | P3.5/UCA1SOMI/UCA1RXD/TB0.1/S23 | bidirectional | General-purpose I/O P3.5 (reset state OFF) with UCA1SOMI/UCA1RXD, Timer_B TB0.1 and LCD segment S23 functions. |
| 28 | P3.6/UCA1CLK/TB0.2/S22 | bidirectional | General-purpose I/O P3.6 (reset state OFF) with UCA1CLK, Timer_B TB0.2 and LCD segment S22 functions. |
| 29 | P3.7/UCA1STE/TB0.3/S21 | bidirectional | General-purpose I/O P3.7 (reset state OFF) with UCA1STE, Timer_B TB0.3 and LCD segment S21 functions. |
| 30 | P2.3/UCA0STE/TB0OUTH/S20 | bidirectional | General-purpose I/O P2.3 (reset state OFF) with UCA0STE, TB0OUTH input (switches PWM outputs high impedance) and LCD segment S20 functions. |
| 31 | P2.2/UCA0CLK/TB0.4/RTCCLK/S19 | bidirectional | General-purpose I/O P2.2 (reset state OFF) with UCA0CLK, Timer_B TB0.4, RTC clock output RTCCLK and LCD segment S19 functions. |
| 32 | P2.1/UCA0SOMI/UCA0RXD/TB0.5/DMAE0/S18 | bidirectional | General-purpose I/O P2.1 (reset state OFF) with UCA0SOMI/UCA0RXD, TB0.5, DMA external trigger DMAE0 and LCD segment S18; on the UART-bootloader device this pin is BSL_RX. |
| 33 | P2.0/UCA0SIMO/UCA0TXD/TB0.6/TB0CLK/S17 | bidirectional | General-purpose I/O P2.0 (reset state OFF) with UCA0SIMO/UCA0TXD, TB0.6, TB0CLK and LCD segment S17 functions; on the UART-bootloader device this pin is BSL_TX. |
| 34 | P7.0/TA0CLK/S16 | bidirectional | General-purpose I/O P7.0 (reset state OFF) with Timer_A TA0CLK input and LCD segment S16 functions. |
| 35 | P7.1/TA0.0/ACLK/S15 | bidirectional | General-purpose I/O P7.1 (reset state OFF) with Timer_A TA0.0, ACLK output and LCD segment S15 functions. |
| 36 | P7.2/TA0.1/S14 | bidirectional | General-purpose I/O P7.2 (reset state OFF) with Timer_A TA0.1 and LCD segment S14 functions. |
| 37 | P7.3/TA0.2/S13 | bidirectional | General-purpose I/O P7.3 (reset state OFF) with Timer_A TA0.2 and LCD segment S13 functions. |
| 38 | P7.4/SMCLK/S12 | bidirectional | General-purpose I/O P7.4 (reset state OFF) with SMCLK output and LCD segment S12 functions. |
| 39 | DVSS2 | power_in | Digital ground supply; connect to system VSS. |
| 40 | DVCC2 | power_in | Digital power supply; VCC is specified from 1.8 V to 3.6 V at all DVCC and AVCC pins. |
| 41 | P1.3/TA1.2/A3/C3 | bidirectional | General-purpose I/O P1.3 (reset state OFF) with Timer_A TA1.2 function, ADC analog input A3 and comparator input C3. |
| 42 | P1.2/TA1.1/TA0CLK/COUT/A2/C2 | bidirectional | General-purpose I/O P1.2 (reset state OFF) with Timer_A TA1.1, TA0CLK, comparator output COUT, ADC input A2 and comparator input C2. |
| 43 | P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+ | bidirectional | General-purpose I/O P1.1 (reset state OFF) with Timer_A TA0.2, TA1CLK, COUT, ADC input A1, comparator input C1, reference output VREF+ and external positive reference input VeREF+. |
| 44 | P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/VREF-/VeREF- | bidirectional | General-purpose I/O P1.0 (reset state OFF) with Timer_A TA0.1, DMAE0, RTCCLK, ADC input A0, comparator input C0, reference output VREF- and external negative reference input VeREF-. |
| 45 | P9.4/A12/C12 | bidirectional | General-purpose I/O P9.4 (reset state OFF) with ADC analog input A12 and comparator input C12. |
| 46 | P9.5/A13/C13 | bidirectional | General-purpose I/O P9.5 (reset state OFF) with ADC analog input A13 and comparator input C13. |
| 47 | P9.6/A14/C14 | bidirectional | General-purpose I/O P9.6 (reset state OFF) with ADC analog input A14 and comparator input C14. |
| 48 | P9.7/A15/C15 | bidirectional | General-purpose I/O P9.7 (reset state OFF) with ADC analog input A15 and comparator input C15. |
| 49 | AVCC1 | power_in | Analog power supply; it should be sourced from the same supply as DVCC, and the AVCC-to-DVCC difference must stay within ±0.3 V. |
| 50 | AVSS1 | power_in | Analog ground supply; connect to system VSS. |
| 51 | PJ.4/LFXIN | bidirectional | Port PJ.4 that is the low-frequency crystal input LFXIN (32 kHz) in crystal mode or the bypass clock input in LFXTBYPASS mode, otherwise general-purpose I/O. |
| 52 | PJ.5/LFXOUT | bidirectional | Port PJ.5 that is the low-frequency crystal output LFXOUT in crystal mode, otherwise general-purpose I/O. |
| 53 | AVSS2 | power_in | Analog ground supply; connect to system VSS. |
| 54 | P5.4/UCA1SIMO/UCA1TXD/S11 | bidirectional | General-purpose I/O P5.4 (reset state OFF) with UCA1SIMO/UCA1TXD and LCD segment S11 functions. |
| 55 | P5.5/UCA1SOMI/UCA1RXD/S10 | bidirectional | General-purpose I/O P5.5 (reset state OFF) with UCA1SOMI/UCA1RXD and LCD segment S10 functions. |
| 56 | P5.6/UCA1CLK/S9 | bidirectional | General-purpose I/O P5.6 (reset state OFF) with UCA1CLK and LCD segment S9 functions. |
| 57 | P5.7/UCA1STE/TB0CLK/S8 | bidirectional | General-purpose I/O P5.7 (reset state OFF) with UCA1STE, TB0CLK and LCD segment S8 functions. |
| 58 | P4.4/UCB1STE/TA1CLK/S7 | bidirectional | General-purpose I/O P4.4 (reset state OFF) with UCB1STE, TA1CLK and LCD segment S7 functions. |
| 59 | P4.5/UCB1CLK/TA1.0/S6 | bidirectional | General-purpose I/O P4.5 (reset state OFF) with UCB1CLK, Timer_A TA1.0 and LCD segment S6 functions. |
| 60 | P4.6/UCB1SIMO/UCB1SDA/TA1.1/S5 | bidirectional | General-purpose I/O P4.6 (reset state OFF) with UCB1SIMO/UCB1SDA, Timer_A TA1.1 and LCD segment S5 functions. |
| 61 | P4.7/UCB1SOMI/UCB1SCL/TA1.2/S4 | bidirectional | General-purpose I/O P4.7 (reset state OFF) with UCB1SOMI/UCB1SCL, Timer_A TA1.2 and LCD segment S4 functions. |
| 62 | DVSS3 | power_in | Digital ground supply; connect to system VSS. |
| 63 | DVCC3 | power_in | Digital power supply; VCC is specified from 1.8 V to 3.6 V at all DVCC and AVCC pins. |
| 64 | P4.2/UCA0SIMO/UCA0TXD/UCB1CLK | bidirectional | General-purpose I/O P4.2 (reset state OFF) with UCA0SIMO/UCA0TXD and UCB1CLK functions; no LCD segment is assigned to this pin in the FR692x/FR682x 64-pin figure. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | LQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |
## CAD (KiCad official)
- Symbol: `MSP430FR6820IPMR`
- Footprint: `Package_QFP:LQFP-64_10x10mm_P0.5mm`
- 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files: `msp430fr6820ipmr-etched.step` / `msp430fr6820ipmr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `msp430fr6820ipmr.step` / `msp430fr6820ipmr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/msp430fr69721) (164 pp, sha256 `acfa8c28f070a26c`, retrieved 2026-10-11, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/msp430fr6820ipmr-datasheet.pdf)