component
MSP430FR5989IPMR
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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MSP430FR5989IPMR
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)
MSP430FR5989IPMR from Texas Instruments, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P4.3/UCA0SOMI/UCA0RXD/UCB1STE | bidirectional | Configurable digital I/O with secondary functions for eUSCI_A0 SOMI/RXD and eUSCI_B1 slave transmit enable. |
| 2 | P1.4/UCB0CLK/UCA0STE/TA1.0 | bidirectional | Configurable digital I/O with secondary functions for eUSCI_B0 clock, eUSCI_A0 STE, and Timer_A TA1 capture/compare. |
| 3 | P1.5/UCB0STE/UCA0CLK/TA0.0 | bidirectional | Configurable digital I/O with secondary functions for eUSCI_B0 STE, eUSCI_A0 clock, and Timer_A TA0 capture/compare. |
| 4 | P1.6/UCB0SIMO/UCB0SDA/TA0.1 | bidirectional | Configurable digital I/O with secondary functions for eUSCI_B0 I2C/SPI data and Timer_A TA0 CCR1 capture/compare. |
| 5 | P1.7/UCB0SOMI/UCB0SCL/TA0.2 | bidirectional | Configurable digital I/O with secondary functions for eUSCI_B0 I2C/SPI clock and Timer_A TA0 CCR2 capture/compare. |
| 6 | P2.4/TB0.3 | bidirectional | Configurable digital I/O with secondary function for Timer_B TB0 CCR3 capture/compare. |
| 7 | P2.5/TB0.4 | bidirectional | Configurable digital I/O with secondary function for Timer_B TB0 CCR4 capture/compare. |
| 8 | P2.6/TB0.5/ESIC1OUT | bidirectional | Configurable digital I/O with secondary functions for Timer_B TB0 CCR5 capture/compare and ESI Comparator 1 output. |
| 9 | P2.7/TB0.6/ESIC2OUT | bidirectional | Configurable digital I/O with secondary functions for Timer_B TB0 CCR6 capture/compare and ESI Comparator 2 output. |
| 10 | P5.0/TA1.1/MCLK | bidirectional | Configurable digital I/O with secondary functions for Timer_A TA1 CCR1 capture/compare and MCLK output. |
| 11 | P5.1/TA1.2 | bidirectional | Configurable digital I/O with secondary function for Timer_A TA1 CCR2 capture/compare. |
| 12 | P5.2/TA1.0/TA1CLK/ACLK | bidirectional | Configurable digital I/O with secondary functions for Timer_A TA1 capture/compare, TA1CLK input, and ACLK output. |
| 13 | P5.3/UCB1STE | bidirectional | Configurable digital I/O with secondary function for eUSCI_B1 slave transmit enable. |
| 14 | P3.0/UCB1CLK | bidirectional | Configurable digital I/O with secondary function for eUSCI_B1 clock input/output. |
| 15 | P3.1/UCB1SIMO/UCB1SDA | bidirectional | Configurable digital I/O with secondary functions for eUSCI_B1 I2C/SPI data mode. |
| 16 | P3.2/UCB1SOMI/UCB1SCL | bidirectional | Configurable digital I/O with secondary functions for eUSCI_B1 I2C/SPI clock mode. |
| 17 | DVSS1 | power_in | Digital ground supply. |
| 18 | DVCC1 | power_in | Digital power supply. |
| 19 | TEST/SBWTCK | input | Test mode selection pin with Spy-Bi-Wire clock input. |
| 20 | RST/NMI/SBWTDIO | input | Reset input (active low) with nonmaskable interrupt and Spy-Bi-Wire data input/output capability. |
| 21 | PJ.0/TDO/TB0OUTH/SMCLK/SRSCG1 | bidirectional | Configurable digital I/O with secondary functions for Timer_B TB0 PWM output, SMCLK, and low-power debug. |
| 22 | PJ.1/TDI/TCLK/MCLK/SRSCG0 | bidirectional | Configurable digital I/O with secondary functions for MCLK output and low-power debug. |
| 23 | PJ.2/TMS/ACLK/SROSCOFF | bidirectional | Configurable digital I/O with secondary functions for ACLK output and low-power debug. |
| 24 | PJ.3/TCK/COUT/SRCPUOFF | bidirectional | Configurable digital I/O with secondary functions for comparator output and low-power debug. |
| 25 | P3.3/TA1.1/TB0CLK | bidirectional | Configurable digital I/O with secondary functions for Timer_A TA1 CCR1 capture/compare and Timer_B TB0 clock. |
| 26 | P3.4/UCA1SIMO/UCA1TXD/TB0.0 | bidirectional | Configurable digital I/O with secondary functions for eUSCI_A1 TXD and Timer_B TB0 CCR0 capture/compare. |
| 27 | P3.5/UCA1SOMI/UCA1RXD/TB0.1 | bidirectional | Configurable digital I/O with secondary functions for eUSCI_A1 RXD and Timer_B TB0 CCR1 capture/compare. |
| 28 | P3.6/UCA1CLK/TB0.2 | bidirectional | Configurable digital I/O with secondary functions for eUSCI_A1 clock and Timer_B TB0 CCR2 capture/compare. |
| 29 | P3.7/UCA1STE/TB0.3 | bidirectional | Configurable digital I/O with secondary functions for eUSCI_A1 slave transmit enable and Timer_B TB0 CCR3 capture/compare. |
| 30 | P2.3/UCA0STE/TB0OUTH | bidirectional | Configurable digital I/O with secondary functions for eUSCI_A0 STE and Timer_B TB0 PWM output. |
| 31 | P2.2/UCA0CLK/TB0.4/RTCCLK | bidirectional | Configurable digital I/O with secondary functions for eUSCI_A0 clock, Timer_B TB0 CCR4 capture/compare, and RTC clock output. |
| 32 | P2.1/UCA0SOMI/UCA0RXD/TB0.5/DMAE0 | bidirectional | Configurable digital I/O with secondary functions for eUSCI_A0 SOMI/RXD, Timer_B TB0 CCR5 capture/compare, and DMA external trigger. |
| 33 | P2.0/UCA0SIMO/UCA0TXD/TB0.6/TB0CLK | bidirectional | Configurable digital I/O with secondary functions for eUSCI_A0 SIMO/TXD, Timer_B TB0 CCR6 capture/compare, and TB0CLK. |
| 34 | DVSS2 | power_in | Digital ground supply. |
| 35 | DVCC2 | power_in | Digital power supply. |
| 36 | P1.3/ESITEST4/TA1.2/A3/C3 | bidirectional | Configurable digital I/O with secondary functions for ESI test signal, Timer_A TA1 CCR2 capture/compare, and analog input A3/comparator input C3. |
| 37 | P1.2/TA1.1/TA0CLK/COUT/A2/C2 | bidirectional | Configurable digital I/O with secondary functions for Timer_A TA1/TA0 capture/compare, comparator output, and analog input A2/comparator input C2. |
| 38 | P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+ | bidirectional | Configurable digital I/O with secondary functions for Timer_A capture/compare, comparator output, analog input A1, and positive reference voltage. |
| 39 | P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/VREF-/VeREF- | bidirectional | Configurable digital I/O with secondary functions for Timer_A capture/compare, DMA external trigger, analog input A0, and negative reference voltage. |
| 40 | P9.0/ESICH0/ESITEST0/A8/C8 | bidirectional | Configurable digital I/O with secondary functions for ESI channel 0 sensor excitation output and analog input A8/comparator input C8. |
| 41 | P9.1/ESICH1/ESITEST1/A9/C9 | bidirectional | Configurable digital I/O with secondary functions for ESI channel 1 sensor excitation output and analog input A9/comparator input C9. |
| 42 | P9.2/ESICH2/ESITEST2/A10/C10 | bidirectional | Configurable digital I/O with secondary functions for ESI channel 2 sensor excitation output and analog input A10/comparator input C10. |
| 43 | P9.3/ESICH3/ESITEST3/A11/C11 | bidirectional | Configurable digital I/O with secondary functions for ESI channel 3 sensor excitation output and analog input A11/comparator input C11. |
| 44 | P9.4/ESICI0/A12/C12 | bidirectional | Configurable digital I/O with secondary functions for ESI channel 0 signal input to comparator and analog input A12/comparator input C12. |
| 45 | P9.5/ESICI1/A13/C13 | bidirectional | Configurable digital I/O with secondary functions for ESI channel 1 signal input to comparator and analog input A13/comparator input C13. |
| 46 | P9.6/ESICI2/A14/C14 | bidirectional | Configurable digital I/O with secondary functions for ESI channel 2 signal input to comparator and analog input A14/comparator input C14. |
| 47 | P9.7/ESICI3/A15/C15 | bidirectional | Configurable digital I/O with secondary functions for ESI channel 3 signal input to comparator and analog input A15/comparator input C15. |
| 48 | ESIDVCC | power_in | ESI power supply. |
| 49 | ESIDVSS | power_in | ESI ground supply. |
| 50 | ESICI | input | ESI Scan IF input to comparator module. |
| 51 | ESICOM | input | ESI common termination for Scan IF sensors. |
| 52 | AVCC1 | power_in | Analog power supply. |
| 53 | AVSS3 | power_in | Analog ground supply. |
| 54 | PJ.7/HFXOUT | output | High-frequency crystal oscillator output (XT2) or configurable digital I/O. |
| 55 | PJ.6/HFXIN | input | High-frequency crystal oscillator input (XT2) or configurable digital I/O. |
| 56 | AVSS1 | power_in | Analog ground supply. |
| 57 | PJ.4/LFXIN | input | Low-frequency crystal oscillator input (XT1) or configurable digital I/O. |
| 58 | PJ.5/LFXOUT | output | Low-frequency crystal oscillator output (XT1) or configurable digital I/O. |
| 59 | AVSS2 | power_in | Analog ground supply. |
| 60 | P4.0/UCB1SIMO/UCB1SDA/MCLK | bidirectional | Configurable digital I/O with secondary functions for eUSCI_B1 I2C/SPI data mode and MCLK output. |
| 61 | P4.1/UCB1SOMI/UCB1SCL/ACLK | bidirectional | Configurable digital I/O with secondary functions for eUSCI_B1 I2C/SPI clock mode and ACLK output. |
| 62 | DVSS3 | power_in | Digital ground supply. |
| 63 | DVCC3 | power_in | Digital power supply. |
| 64 | P4.2/UCA0SIMO/UCA0TXD/UCB1CLK | bidirectional | Configurable digital I/O with secondary functions for eUSCI_A0 SIMO/TXD and eUSCI_B1 clock. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | LQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |
CAD (KiCad official)
- Symbol:
MSP430FR5989IPMR - Footprint:
Package_QFP:LQFP-64_10x10mm_P0.5mm - 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files:
msp430fr5989ipmr-etched.step/msp430fr5989ipmr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);msp430fr5989ipmr.step/msp430fr5989ipmr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (190 pp, sha256
868055019a26de9e, retrieved 2026-10-07, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).