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MSP430FR5969IRGZR

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Texas Instruments TI MCU, VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MSP430FR5969IRGZR

Texas Instruments · TI MCU · VQFN-48-EP(7x7)

MSP430FR5969IRGZR from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/VREF-/VeREF- bidirectional General-purpose digital I/O with port interrupt and wakeup from LPMx.5, multiplexed with TA0 CCR1, DMA trigger, RTC clock output, ADC input A0, comparator input C0 and negative reference output/input.
2 P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+ bidirectional General-purpose digital I/O with port interrupt and wakeup from LPMx.5, multiplexed with TA0 CCR2, TA1 input clock, comparator output, ADC input A1, comparator input C1 and positive reference output/input.
3 P1.2/TA1.1/TA0CLK/COUT/A2/C2 bidirectional General-purpose digital I/O with port interrupt and wakeup from LPMx.5, multiplexed with TA1 CCR1, TA0 input clock, comparator output, ADC input A2 and comparator input C2.
4 P3.0/A12/C12 bidirectional General-purpose digital I/O with port interrupt and wakeup from LPMx.5, with ADC analog input A12 and comparator input C12.
5 P3.1/A13/C13 bidirectional General-purpose digital I/O with port interrupt and wakeup from LPMx.5, with ADC analog input A13 and comparator input C13.
6 P3.2/A14/C14 bidirectional General-purpose digital I/O with port interrupt and wakeup from LPMx.5, with ADC analog input A14 and comparator input C14.
7 P3.3/A15/C15 bidirectional General-purpose digital I/O with port interrupt and wakeup from LPMx.5, with ADC analog input A15 and comparator input C15.
8 P4.7 bidirectional General-purpose digital I/O with port interrupt and wakeup from LPMx.5.
9 P1.3/TA1.2/UCB0STE/A3/C3 bidirectional General-purpose digital I/O with port interrupt and wakeup from LPMx.5, multiplexed with TA1 CCR2, eUSCI_B0 SPI slave transmit enable, ADC input A3 and comparator input C3.
10 P1.4/TB0.1/UCA0STE/A4/C4 bidirectional General-purpose digital I/O multiplexed with TB0 CCR1, eUSCI_A0 SPI slave transmit enable, ADC input A4 and comparator input C4.
11 P1.5/TB0.2/UCA0CLK/A5/C5 bidirectional General-purpose digital I/O multiplexed with TB0 CCR2, eUSCI_A0 SPI clock, ADC input A5 and comparator input C5.
12 PJ.0/TDO/TB0OUTH/SMCLK/SRSCG1/C6 bidirectional General-purpose digital I/O or JTAG TDO, multiplexed with TB0OUTH, SMCLK output, CPU status bit SCG1 and comparator input C6.
13 PJ.1/TDI/TCLK/MCLK/SRSCG0/C7 bidirectional General-purpose digital I/O or JTAG TDI/TCLK, multiplexed with MCLK output, CPU status bit SCG0 and comparator input C7.
14 PJ.2/TMS/ACLK/SROSCOFF/C8 bidirectional General-purpose digital I/O or JTAG TMS, multiplexed with ACLK output, CPU status bit OSCOFF and comparator input C8.
15 PJ.3/TCK/SRCPUOFF/C9 bidirectional General-purpose digital I/O or JTAG TCK, multiplexed with CPU status bit CPUOFF and comparator input C9.
16 P4.0/A8 bidirectional General-purpose digital I/O with ADC analog input A8.
17 P4.1/A9 bidirectional General-purpose digital I/O with ADC analog input A9.
18 P4.2/A10 bidirectional General-purpose digital I/O with ADC analog input A10.
19 P4.3/A11 bidirectional General-purpose digital I/O with ADC analog input A11.
20 P2.5/TB0.0/UCA1TXD/UCA1SIMO bidirectional General-purpose digital I/O multiplexed with TB0 CCR0, eUSCI_A1 UART transmit data and SPI slave in/master out.
21 P2.6/TB0.1/UCA1RXD/UCA1SOMI bidirectional General-purpose digital I/O multiplexed with TB0 CCR1, eUSCI_A1 UART receive data and SPI slave out/master in.
22 TEST/SBWTCK input Test mode / Spy-Bi-Wire clock input; this pin always has an internal pulldown enabled and should be left open if unused.
23 RST/NMI/SBWTDIO bidirectional Reset input, non-maskable interrupt input and Spy-Bi-Wire data; if unused connect to DVCC with a 47-kΩ pullup or use internal pullup with a 2.2-nF (10-nF) pulldown capacitor.
24 P2.0/TB0.6/UCA0TXD/UCA0SIMO/TB0CLK/ACLK bidirectional General-purpose digital I/O multiplexed with TB0 CCR6, eUSCI_A0 UART transmit/SPI SIMO, TB0 clock input and ACLK output; BSLTX on UART BSL devices.
25 P2.1/TB0.0/UCA0RXD/UCA0SOMI/TB0.0 bidirectional General-purpose digital I/O multiplexed with TB0 CCR0 and eUSCI_A0 UART receive/SPI SOMI; BSLRX on UART BSL devices.
26 P2.2/TB0.2/UCB0CLK bidirectional General-purpose digital I/O multiplexed with TB0 CCR2 and eUSCI_B0 SPI clock.
27 P3.4/TB0.3/SMCLK bidirectional General-purpose digital I/O multiplexed with TB0 CCR3 and SMCLK output.
28 P3.5/TB0.4/COUT bidirectional General-purpose digital I/O multiplexed with TB0 CCR4 and comparator output.
29 P3.6/TB0.5 bidirectional General-purpose digital I/O multiplexed with TB0 CCR5.
30 P3.7/TB0.6 bidirectional General-purpose digital I/O multiplexed with TB0 CCR6.
31 P1.6/TB0.3/UCB0SIMO/UCB0SDA/TA0.0 bidirectional General-purpose digital I/O multiplexed with TB0 CCR3, eUSCI_B0 SPI SIMO / I2C data and TA0 CCR0; BSLSDA on I2C BSL devices.
32 P1.7/TB0.4/UCB0SOMI/UCB0SCL/TA1.0 bidirectional General-purpose digital I/O with port interrupt and wakeup from LPMx.5, multiplexed with TB0 CCR4, eUSCI_B0 SPI SOMI / I2C clock (BSL clock on I2C BSL) and TA1 CCR0.
33 P4.4/TB0.5 bidirectional General-purpose digital I/O with port interrupt and wakeup from LPMx.5, multiplexed with TB0 CCR5.
34 P4.5 bidirectional General-purpose digital I/O with port interrupt and wakeup from LPMx.5.
35 P4.6 bidirectional General-purpose digital I/O with port interrupt and wakeup from LPMx.5.
36 DVSS power_in Digital ground supply.
37 DVCC power_in Digital power supply, 1.8 V to 3.6 V, with a 1-µF plus 100-nF decoupling capacitor recommended.
38 P2.7 bidirectional General-purpose digital I/O with port interrupt and wakeup from LPMx.5.
39 P2.3/TA0.0/UCA1STE/A6/C10 bidirectional General-purpose digital I/O with port interrupt and wakeup from LPMx.5, multiplexed with TA0 CCR0, eUSCI_A1 SPI slave transmit enable, ADC input A6 and comparator input C10.
40 P2.4/TA1.0/UCA1CLK/A7/C11 bidirectional General-purpose digital I/O with port interrupt and wakeup from LPMx.5, multiplexed with TA1 CCR0, eUSCI_A1 SPI clock, ADC input A7 and comparator input C11.
41 AVSS power_in Analog ground supply.
42 PJ.6/HFXIN bidirectional General-purpose digital I/O or input for the high-frequency crystal oscillator HFXT.
43 PJ.7/HFXOUT bidirectional General-purpose digital I/O or output for the high-frequency crystal oscillator HFXT.
44 AVSS power_in Analog ground supply.
45 PJ.4/LFXIN bidirectional General-purpose digital I/O or input for the low-frequency crystal oscillator LFXT.
46 PJ.5/LFXOUT bidirectional General-purpose digital I/O or output of the low-frequency crystal oscillator LFXT.
47 AVSS power_in Analog ground supply.
48 AVCC power_in Analog power supply, 1.8 V to 3.6 V, kept within ±0.3 V of DVCC.
49 QFN Pad passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-48-EP(7x7)
Category Embedded Processors & Controllers
Pins 49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage range at DVCC and AVCC VCC 1.8 3.6 V 17
Operating free-air temperature TA -40 85 °C 17
Operating junction temperature TJ -40 85 °C 17
Processor frequency, no FRAM wait states fSYSTEM 0 8 MHz NWAITSx = 0 17
Processor frequency, with FRAM wait states fSYSTEM 0 16 MHz NWAITSx = 1 17
Maximum ACLK frequency fACLK 50 kHz 17
Maximum SMCLK frequency fSMCLK 16 MHz 17
Capacitor value at DVCC CDVCC -20 1 µF printed as 1 -20% 17
Voltage applied at DVCC and AVCC pins to VSS -0.3 4.1 V 17
Voltage difference between DVCC and AVCC pins -0.3 0.3 V printed ±0.3 V 17
Voltage applied to any pin -0.3 4.1 V VCC + 0.3 V (4.1 V max) 17
Diode current at any device pin -2 2 mA printed ±2 mA 17
Storage temperature Tstg -40 125 °C 17
ESD, human-body model V(ESD) -1000 1000 V HBM, ANSI/ESDA/JEDEC JS-001; printed ±1000 V 17
ESD, charged-device model V(ESD) -250 250 V CDM, JESD22-C101; printed ±250 V 17
Junction-to-ambient thermal resistance θJA 30.6 °C/W QFN-48 (RGZ), still air 23
Junction-to-case (top) thermal resistance θJC(TOP) 17.2 °C/W QFN-48 (RGZ) 23
Junction-to-board thermal resistance θJB 7.2 °C/W QFN-48 (RGZ) 23
Junction-to-board thermal characterization parameter ΨJB 7.2 °C/W QFN-48 (RGZ) 23
Junction-to-top thermal characterization parameter ΨJT 0.2 °C/W QFN-48 (RGZ) 23
Junction-to-case (bottom) thermal resistance θJC(BOTTOM) 1.2 °C/W QFN-48 (RGZ) 23
Brownout power-down level VVCC_BOR- 0.7 1.66 V /dDVCC/dt/ < 3 V/s 24
Brownout power-up level VVCC_BOR+ 0.79 1.68 V /dDVCC/dt/ < 3 V/s 24
SVSH power-down level VSVSH- 1.75 1.8 1.85 V 25
SVSH power-up level VSVSH+ 1.77 1.88 1.99 V 25
SVSH hysteresis VSVSH_hys 40 120 mV 25
SVSH current consumption, low power modes ISVSH,LPM 170 300 nA 25
External reset pulse duration on RST t(RST) 2 µs VCC = 2.2 V, 3.0 V 25
DCO frequency, 1 MHz trimmed fDCO1 -3.5 3.5 % Measured at SMCLK, divide by 1; nominal 1 MHz 29
DCO frequency, 16 MHz trimmed fDCO16 -3.5 3.5 % DCORSEL = 1, DCOFSEL = 4; nominal 16 MHz 29
DCO duty cycle fDCO,DC 48 50 52 % Measured at SMCLK, divide by 1 29
VLO frequency fVLO 6 9.4 14 kHz Measured at ACLK 30
MODOSC frequency fMODOSC 4 4.8 5.4 MHz 30
Positive-going input threshold voltage VIT+ 1.65 2.25 V VCC = 3.0 V 33
Negative-going input threshold voltage VIT- 0.75 1.35 V VCC = 3.0 V 33
Input voltage hysteresis Vhys 0.6 1.3 V VCC = 3.0 V 33
Pullup or pulldown resistor RPull 20 35 50 kΩ For pullup: VIN = VSS; for pulldown: VIN = VCC 33
High-impedance input leakage current Ilkg(Px.y) -20 20 nA VCC = 2.2 V, 3.0 V 33
Port output rise time, digital only port pins trise,dig 3 15 ns CL = 20 pF, VCC = 3.0 V 34
Port output fall time, digital only port pins tfall,dig 3 15 ns CL = 20 pF, VCC = 3.0 V 34
Low-power mode 3, VLO, excludes SVS, 85°C ILPM3,VLO 1.6 4.7 µA VCC = 3.0 V, 85°C 20
Low-power mode 4.5, excludes SVS, 85°C ILPM4.5 0.08 0.35 µA VCC = 3.0 V, 85°C 21
ADC12_B supply current, single-ended mode I(ADC12_B) 145 185 µA VCC = 3.0 V, ADC12DIF = 0, REFON = 0 44
ADC input capacitance CI 10 15 pF VCC = 2.2 V 44
ADC integral linearity error, single ended EI -2.2 2.2 LSB 1.2 V ≤ VR+, VR- ≤ AVCC; printed ±2.2 46
ADC differential linearity error ED -0.99 1 LSB 46
ADC offset error EO -1.5 1.5 mV ADC12VRSEL = 0x2 or 0x4 without TLV calibration; typ ±0.5 46

CAD (KiCad official)

  • Symbol: MSP430FR5969IRGZR
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: msp430fr5969irgzr-etched.step / msp430fr5969irgzr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); msp430fr5969irgzr.step / msp430fr5969irgzr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (144 pp, sha256 79b851fbdc63bcae, retrieved 2026-10-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF