component
MSP430FR5964IPMR
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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MSP430FR5964IPMR
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)
MSP430FR5964IPMR from Texas Instruments, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P1.0 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with port interrupt and LPMx.5 wake-up; alternates are TA0.1, DMAE0, RTCCLK, ADC/comparator input A0/C0, and VREF-/VeREF-; reset state OFF. |
| 2 | P1.1 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with port interrupt and LPMx.5 wake-up; alternates are TA0.2, TA1CLK, COUT, ADC/comparator input A1/C1, and VREF+/VeREF+; reset state OFF. |
| 3 | P1.2 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with port interrupt and LPMx.5 wake-up; alternates are TA1.1, TA0CLK, COUT, and ADC/comparator input A2/C2; reset state OFF. |
| 4 | P3.0 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with port interrupt and LPMx.5 wake-up, with analog/comparator input A12/C12; reset state OFF. |
| 5 | P3.1 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with port interrupt and LPMx.5 wake-up, with analog/comparator input A13/C13. |
| 6 | P3.2 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with port interrupt and LPMx.5 wake-up, with analog/comparator input A14/C14; reset state OFF. |
| 7 | P3.3 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with port interrupt and LPMx.5 wake-up, with analog/comparator input A15/C15; reset state OFF. |
| 8 | P4.7 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with port interrupt and LPMx.5 wake-up; reset state OFF. |
| 9 | P7.0 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternate eUSCI_B2 functions UCB2SIMO/UCB2SDA; reset state OFF. |
| 10 | P7.1 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternate eUSCI_B2 functions UCB2SOMI/UCB2SCL; reset state OFF. |
| 11 | P8.0 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with port interrupt and LPMx.5 wake-up; reset state OFF. |
| 12 | P1.3 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternates TA1.2, UCB0STE and ADC/comparator input A3/C3; reset state OFF. |
| 13 | P1.4 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternates TB0.1, UCA0STE and ADC/comparator input A4/C4; reset state OFF. |
| 14 | P1.5 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternates TB0.2, UCA0CLK and ADC/comparator input A5/C5; reset state OFF. |
| 15 | DVSS2 | power_in | Digital ground supply, 0 V reference for all DVSS pins. |
| 16 | DVCC2 | power_in | Digital power supply; VCC must be within 1.8 V to 3.6 V at all DVCC and AVCC pins, with a 1 µF plus 100 nF decoupling capacitor recommended per pin pair. |
| 17 | PJ.0 | bidirectional | General-purpose I/O (PJ.0) shared with JTAG TDO and alternates TB0OUTH, SMCLK, SRSCG1 and comparator input C6; when used as JTAG pin it should remain open. |
| 18 | PJ.1 | bidirectional | General-purpose I/O (PJ.1) shared with JTAG TDI/TCLK and alternates MCLK, SRSCG0 and comparator input C7; when used as JTAG pin it should remain open. |
| 19 | PJ.2 | bidirectional | General-purpose I/O (PJ.2) shared with JTAG TMS and alternates ACLK, SROSCOFF and comparator input C8; when used as JTAG pin it should remain open. |
| 20 | PJ.3 | bidirectional | General-purpose I/O (PJ.3) shared with JTAG TCK and alternates SRCPUOFF and comparator input C9; when used as JTAG pin it should remain open. |
| 21 | P7.2 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternate eUSCI_B2 function UCB2CLK. |
| 22 | P7.3 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternates UCB2STE and TA4.1. |
| 23 | P7.4 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternates TA4.0 and ADC input A16. |
| 24 | P4.0 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with ADC input A8. |
| 25 | P4.1 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with ADC input A9. |
| 26 | P4.2 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with ADC input A10. |
| 27 | P4.3 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with ADC input A11. |
| 28 | P2.5 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternates TB0.0 and eUSCI_A1 UCA1TXD/UCA1SIMO. |
| 29 | P2.6 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternates TB0.1 and eUSCI_A1 UCA1RXD/UCA1SOMI. |
| 30 | TEST | input | Test mode pin (TEST/SBWTCK) that enables Spy-Bi-Wire or JTAG debug connection and selects digital I/O on JTAG pins; it has an internal pulldown of 20 to 50 kΩ (35 kΩ typical). |
| 31 | RST/NMI/SBWTDIO | bidirectional | Active-low reset input (RST), alternatively configurable as nonmaskable interrupt input (NMI) or Spy-Bi-Wire data I/O (SBWTDIO); recommended termination is DVCC with a 47 kΩ pullup or internal pullup plus a 10 nF pulldown (2.2 nF in SBW/4-wire JTAG mode). |
| 32 | P2.0 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternates TB0.6, eUSCI_A0 UCA0TXD/UCA0SIMO, TB0CLK and ACLK; it is BSLTX on UART-BSL devices. |
| 33 | P2.1 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternates TB0.0 and eUSCI_A0 UCA0RXD/UCA0SOMI; it is BSLRX on UART-BSL devices. |
| 34 | P2.2 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternates TB0.2 and eUSCI_B0 UCB0CLK. |
| 35 | P3.4 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternates TB0.3 and SMCLK output. |
| 36 | P3.5 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternates TB0.4 and COUT comparator output. |
| 37 | P3.6 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternate TB0.5. |
| 38 | P3.7 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternate TB0.6. |
| 39 | P1.6 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternates TB0.3, eUSCI_B0 UCB0SIMO/UCB0SDA and TA0.0; it is BSLSDA on I2C-BSL devices. |
| 40 | P1.7 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternates TB0.4, eUSCI_B0 UCB0SOMI/UCB0SCL and TA1.0; it is BSLSCL on I2C-BSL devices. |
| 41 | P5.0 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternates eUSCI_B1 UCB1SIMO/UCB1SDA. |
| 42 | P5.1 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternates eUSCI_B1 UCB1SOMI/UCB1SCL. |
| 43 | P5.2 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternates eUSCI_B1 UCB1CLK and TA4CLK. |
| 44 | P5.3 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternate eUSCI_B1 UCB1STE. |
| 45 | P4.4 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternate TB0.5. |
| 46 | P4.5 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with port interrupt and LPMx.5 wake-up. |
| 47 | P4.6 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with port interrupt and LPMx.5 wake-up. |
| 48 | DVSS1 | power_in | Digital ground supply, 0 V reference for DVCC1. |
| 49 | DVCC1 | power_in | Digital power supply; VCC must be within 1.8 V to 3.6 V at all DVCC and AVCC pins. |
| 50 | P2.7 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with port interrupt and LPMx.5 wake-up. |
| 51 | P2.3 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternates TA0.0, eUSCI_A1 UCA1STE and ADC/comparator input A6/C10. |
| 52 | P2.4 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternates TA1.0, eUSCI_A1 UCA1CLK and ADC/comparator input A7/C11. |
| 53 | P5.4 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternates eUSCI_A2 UCA2TXD/UCA2SIMO and TB0OUTH. |
| 54 | P5.5 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternates eUSCI_A2 UCA2RXD/UCA2SOMI and ACLK. |
| 55 | P5.6 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternates eUSCI_A2 UCA2CLK, TA4.0 and SMCLK. |
| 56 | P5.7 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternates eUSCI_A2 UCA2STE, TA4.1 and MCLK. |
| 57 | AVSS3 | power_in | Analog ground supply, 0 V reference for AVCC. |
| 58 | PJ.6 | bidirectional | General-purpose I/O (PJ.6) shared with HFXIN, the high-frequency crystal oscillator input, which can alternatively take a digital clock in HFXTBYPASS mode. |
| 59 | PJ.7 | bidirectional | General-purpose I/O (PJ.7) shared with HFXOUT, the high-frequency crystal oscillator output; it becomes general-purpose I/O in HFXT bypass mode. |
| 60 | AVSS2 | power_in | Analog ground supply, 0 V reference for AVCC. |
| 61 | PJ.4 | bidirectional | General-purpose I/O (PJ.4) shared with LFXIN, the low-frequency (32 kHz) crystal oscillator input, which can alternatively take a digital clock in LFXTBYPASS mode. |
| 62 | PJ.5 | bidirectional | General-purpose I/O (PJ.5) shared with LFXOUT, the low-frequency (32 kHz) crystal oscillator output; it becomes general-purpose I/O in LFXT bypass mode. |
| 63 | AVSS1 | power_in | Analog ground supply, 0 V reference for AVCC. |
| 64 | AVCC1 | power_in | Analog power supply; VCC must be within 1.8 V to 3.6 V and should be powered from the same source as DVCC. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | LQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |
CAD (KiCad official)
- Symbol:
MSP430FR5964IPMR - Footprint:
Package_QFP:LQFP-64_10x10mm_P0.5mm - 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files:
msp430fr5964ipmr-etched.step/msp430fr5964ipmr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);msp430fr5964ipmr.step/msp430fr5964ipmr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (177 pp, sha256
305369231542d625, retrieved 2026-10-08, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# MSP430FR5964IPMR
**Texas Instruments** · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)
MSP430FR5964IPMR from Texas Instruments, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P1.0 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with port interrupt and LPMx.5 wake-up; alternates are TA0.1, DMAE0, RTCCLK, ADC/comparator input A0/C0, and VREF-/VeREF-; reset state OFF. |
| 2 | P1.1 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with port interrupt and LPMx.5 wake-up; alternates are TA0.2, TA1CLK, COUT, ADC/comparator input A1/C1, and VREF+/VeREF+; reset state OFF. |
| 3 | P1.2 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with port interrupt and LPMx.5 wake-up; alternates are TA1.1, TA0CLK, COUT, and ADC/comparator input A2/C2; reset state OFF. |
| 4 | P3.0 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with port interrupt and LPMx.5 wake-up, with analog/comparator input A12/C12; reset state OFF. |
| 5 | P3.1 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with port interrupt and LPMx.5 wake-up, with analog/comparator input A13/C13. |
| 6 | P3.2 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with port interrupt and LPMx.5 wake-up, with analog/comparator input A14/C14; reset state OFF. |
| 7 | P3.3 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with port interrupt and LPMx.5 wake-up, with analog/comparator input A15/C15; reset state OFF. |
| 8 | P4.7 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with port interrupt and LPMx.5 wake-up; reset state OFF. |
| 9 | P7.0 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternate eUSCI_B2 functions UCB2SIMO/UCB2SDA; reset state OFF. |
| 10 | P7.1 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternate eUSCI_B2 functions UCB2SOMI/UCB2SCL; reset state OFF. |
| 11 | P8.0 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with port interrupt and LPMx.5 wake-up; reset state OFF. |
| 12 | P1.3 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternates TA1.2, UCB0STE and ADC/comparator input A3/C3; reset state OFF. |
| 13 | P1.4 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternates TB0.1, UCA0STE and ADC/comparator input A4/C4; reset state OFF. |
| 14 | P1.5 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternates TB0.2, UCA0CLK and ADC/comparator input A5/C5; reset state OFF. |
| 15 | DVSS2 | power_in | Digital ground supply, 0 V reference for all DVSS pins. |
| 16 | DVCC2 | power_in | Digital power supply; VCC must be within 1.8 V to 3.6 V at all DVCC and AVCC pins, with a 1 µF plus 100 nF decoupling capacitor recommended per pin pair. |
| 17 | PJ.0 | bidirectional | General-purpose I/O (PJ.0) shared with JTAG TDO and alternates TB0OUTH, SMCLK, SRSCG1 and comparator input C6; when used as JTAG pin it should remain open. |
| 18 | PJ.1 | bidirectional | General-purpose I/O (PJ.1) shared with JTAG TDI/TCLK and alternates MCLK, SRSCG0 and comparator input C7; when used as JTAG pin it should remain open. |
| 19 | PJ.2 | bidirectional | General-purpose I/O (PJ.2) shared with JTAG TMS and alternates ACLK, SROSCOFF and comparator input C8; when used as JTAG pin it should remain open. |
| 20 | PJ.3 | bidirectional | General-purpose I/O (PJ.3) shared with JTAG TCK and alternates SRCPUOFF and comparator input C9; when used as JTAG pin it should remain open. |
| 21 | P7.2 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternate eUSCI_B2 function UCB2CLK. |
| 22 | P7.3 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternates UCB2STE and TA4.1. |
| 23 | P7.4 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternates TA4.0 and ADC input A16. |
| 24 | P4.0 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with ADC input A8. |
| 25 | P4.1 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with ADC input A9. |
| 26 | P4.2 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with ADC input A10. |
| 27 | P4.3 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with ADC input A11. |
| 28 | P2.5 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternates TB0.0 and eUSCI_A1 UCA1TXD/UCA1SIMO. |
| 29 | P2.6 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternates TB0.1 and eUSCI_A1 UCA1RXD/UCA1SOMI. |
| 30 | TEST | input | Test mode pin (TEST/SBWTCK) that enables Spy-Bi-Wire or JTAG debug connection and selects digital I/O on JTAG pins; it has an internal pulldown of 20 to 50 kΩ (35 kΩ typical). |
| 31 | RST/NMI/SBWTDIO | bidirectional | Active-low reset input (RST), alternatively configurable as nonmaskable interrupt input (NMI) or Spy-Bi-Wire data I/O (SBWTDIO); recommended termination is DVCC with a 47 kΩ pullup or internal pullup plus a 10 nF pulldown (2.2 nF in SBW/4-wire JTAG mode). |
| 32 | P2.0 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternates TB0.6, eUSCI_A0 UCA0TXD/UCA0SIMO, TB0CLK and ACLK; it is BSLTX on UART-BSL devices. |
| 33 | P2.1 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternates TB0.0 and eUSCI_A0 UCA0RXD/UCA0SOMI; it is BSLRX on UART-BSL devices. |
| 34 | P2.2 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternates TB0.2 and eUSCI_B0 UCB0CLK. |
| 35 | P3.4 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternates TB0.3 and SMCLK output. |
| 36 | P3.5 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternates TB0.4 and COUT comparator output. |
| 37 | P3.6 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternate TB0.5. |
| 38 | P3.7 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternate TB0.6. |
| 39 | P1.6 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternates TB0.3, eUSCI_B0 UCB0SIMO/UCB0SDA and TA0.0; it is BSLSDA on I2C-BSL devices. |
| 40 | P1.7 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternates TB0.4, eUSCI_B0 UCB0SOMI/UCB0SCL and TA1.0; it is BSLSCL on I2C-BSL devices. |
| 41 | P5.0 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternates eUSCI_B1 UCB1SIMO/UCB1SDA. |
| 42 | P5.1 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternates eUSCI_B1 UCB1SOMI/UCB1SCL. |
| 43 | P5.2 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternates eUSCI_B1 UCB1CLK and TA4CLK. |
| 44 | P5.3 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternate eUSCI_B1 UCB1STE. |
| 45 | P4.4 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternate TB0.5. |
| 46 | P4.5 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with port interrupt and LPMx.5 wake-up. |
| 47 | P4.6 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with port interrupt and LPMx.5 wake-up. |
| 48 | DVSS1 | power_in | Digital ground supply, 0 V reference for DVCC1. |
| 49 | DVCC1 | power_in | Digital power supply; VCC must be within 1.8 V to 3.6 V at all DVCC and AVCC pins. |
| 50 | P2.7 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with port interrupt and LPMx.5 wake-up. |
| 51 | P2.3 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternates TA0.0, eUSCI_A1 UCA1STE and ADC/comparator input A6/C10. |
| 52 | P2.4 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternates TA1.0, eUSCI_A1 UCA1CLK and ADC/comparator input A7/C11. |
| 53 | P5.4 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternates eUSCI_A2 UCA2TXD/UCA2SIMO and TB0OUTH. |
| 54 | P5.5 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternates eUSCI_A2 UCA2RXD/UCA2SOMI and ACLK. |
| 55 | P5.6 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternates eUSCI_A2 UCA2CLK, TA4.0 and SMCLK. |
| 56 | P5.7 | bidirectional | General-purpose LVCMOS I/O powered from DVCC with alternates eUSCI_A2 UCA2STE, TA4.1 and MCLK. |
| 57 | AVSS3 | power_in | Analog ground supply, 0 V reference for AVCC. |
| 58 | PJ.6 | bidirectional | General-purpose I/O (PJ.6) shared with HFXIN, the high-frequency crystal oscillator input, which can alternatively take a digital clock in HFXTBYPASS mode. |
| 59 | PJ.7 | bidirectional | General-purpose I/O (PJ.7) shared with HFXOUT, the high-frequency crystal oscillator output; it becomes general-purpose I/O in HFXT bypass mode. |
| 60 | AVSS2 | power_in | Analog ground supply, 0 V reference for AVCC. |
| 61 | PJ.4 | bidirectional | General-purpose I/O (PJ.4) shared with LFXIN, the low-frequency (32 kHz) crystal oscillator input, which can alternatively take a digital clock in LFXTBYPASS mode. |
| 62 | PJ.5 | bidirectional | General-purpose I/O (PJ.5) shared with LFXOUT, the low-frequency (32 kHz) crystal oscillator output; it becomes general-purpose I/O in LFXT bypass mode. |
| 63 | AVSS1 | power_in | Analog ground supply, 0 V reference for AVCC. |
| 64 | AVCC1 | power_in | Analog power supply; VCC must be within 1.8 V to 3.6 V and should be powered from the same source as DVCC. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | LQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |
## CAD (KiCad official)
- Symbol: `MSP430FR5964IPMR`
- Footprint: `Package_QFP:LQFP-64_10x10mm_P0.5mm`
- 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files: `msp430fr5964ipmr-etched.step` / `msp430fr5964ipmr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `msp430fr5964ipmr.step` / `msp430fr5964ipmr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/msp430fr5992) (177 pp, sha256 `305369231542d625`, retrieved 2026-10-08, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/msp430fr5964ipmr-datasheet.pdf)