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MSP430FR5962IRGZR
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Texas Instruments Microcontrollers (MCU/MPU/SOC), VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+86@@ -0,0 +1,86 @@+# MSP430FR5962IRGZR++**Texas Instruments** · Microcontrollers (MCU/MPU/SOC) · VQFN-48-EP(7x7)++MSP430FR5962IRGZR from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | P1.0 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with TA0.1, DMAE0, RTCCLK, ADC/comparator input A0/C0 and VREF-/VeREF- reference, LVCMOS buffer powered from DVCC. |+| 2 | P1.1 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with TA0.2, TA1CLK, COUT, ADC/comparator input A1/C1 and VREF+/VeREF+ reference, LVCMOS buffer powered from DVCC. |+| 3 | P1.2 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with TA1.1, TA0CLK, COUT and ADC/comparator input A2/C2, LVCMOS buffer powered from DVCC. |+| 4 | P3.0 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with ADC/comparator input A12/C12, LVCMOS buffer powered from DVCC. |+| 5 | P3.1 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with ADC/comparator input A13/C13, LVCMOS buffer powered from DVCC. |+| 6 | P3.2 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with ADC/comparator input A14/C14, LVCMOS buffer powered from DVCC. |+| 7 | P3.3 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with ADC/comparator input A15/C15, LVCMOS buffer powered from DVCC. |+| 8 | P4.7 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, LVCMOS buffer powered from DVCC. |+| 9 | P1.3 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with TA1.2, UCB0STE, ADC/comparator input A3/C3, LVCMOS buffer powered from DVCC. |+| 10 | P1.4 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with TB0.1, UCA0STE, ADC/comparator input A4/C4, LVCMOS buffer powered from DVCC. |+| 11 | P1.5 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with TB0.2, UCA0CLK, ADC/comparator input A5/C5, LVCMOS buffer powered from DVCC. |+| 12 | PJ.0 | bidirectional | General-purpose digital I/O (PJ.0) multiplexed with JTAG TDO, TB0OUTH, SMCLK, CPU status bit SCG1 and comparator input C6, LVCMOS buffer powered from DVCC; keep open when used as JTAG pin. |+| 13 | PJ.1 | bidirectional | General-purpose digital I/O (PJ.1) multiplexed with JTAG TDI/TCLK, MCLK, CPU status bit SCG0 and comparator input C7, LVCMOS buffer powered from DVCC; keep open when used as JTAG pin. |+| 14 | PJ.2 | bidirectional | General-purpose digital I/O (PJ.2) multiplexed with JTAG TMS, ACLK, CPU status bit OSCOFF and comparator input C8, LVCMOS buffer powered from DVCC; keep open when used as JTAG pin. |+| 15 | PJ.3 | bidirectional | General-purpose digital I/O (PJ.3) multiplexed with JTAG TCK, CPU status bit CPUOFF and comparator input C9, LVCMOS buffer powered from DVCC; keep open when used as JTAG pin. |+| 16 | P4.0 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with ADC input A8, powered from DVCC. |+| 17 | P4.1 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with ADC input A9, powered from DVCC. |+| 18 | P4.2 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with ADC input A10, powered from DVCC. |+| 19 | P4.3 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with ADC input A11, powered from DVCC. |+| 20 | P2.5 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with TB0.0 and eUSCI_A1 UCA1TXD/UCA1SIMO, powered from DVCC. |+| 21 | P2.6 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with TB0.1 and eUSCI_A1 UCA1RXD/UCA1SOMI, powered from DVCC. |+| 22 | TEST | input | Test mode pin that selects digital I/O on the JTAG pins and serves as SBWTCK for Spy-Bi-Wire; it always has an internal pulldown of 20 to 50 kΩ enabled, and should be left open. |+| 23 | RST | input | Active-low reset input, also multiplexed as NMI and SBWTDIO; if unused, connect to DVCC through a 47 kΩ pullup or use the internal pullup with a 10 nF pulldown (2.2 nF in Spy-Bi-Wire or 4-wire JTAG mode). |+| 24 | P2.0 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with TB0.6, eUSCI_A0 UCA0TXD/UCA0SIMO, TB0CLK and ACLK; this pin becomes BSLTX on devices with UART BSL. |+| 25 | P2.1 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with TB0.0 and eUSCI_A0 UCA0RXD/UCA0SOMI; this pin becomes BSLRX on devices with UART BSL. |+| 26 | P2.2 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with TB0.2 and eUSCI_B0 UCB0CLK, powered from DVCC. |+| 27 | P3.4 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with TB0.3 and SMCLK, powered from DVCC. |+| 28 | P3.5 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with TB0.4 and COUT, powered from DVCC. |+| 29 | P3.6 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with TB0.5, powered from DVCC. |+| 30 | P3.7 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with TB0.6, powered from DVCC. |+| 31 | P1.6 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with TB0.3, eUSCI_B0 UCB0SIMO/UCB0SDA and TA0.0; this pin becomes BSLSDA on devices with I2C BSL. |+| 32 | P1.7 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with TB0.4, eUSCI_B0 UCB0SOMI/UCB0SCL and TA1.0; this pin becomes BSLSCL on devices with I2C BSL. |+| 33 | P4.4 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with TB0.5, powered from DVCC. |+| 34 | P4.5 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, powered from DVCC. |+| 35 | P4.6 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, powered from DVCC. |+| 36 | DVSS1 | power_in | Digital ground supply (0 V) for the digital domain. |+| 37 | DVCC1 | power_in | Digital power supply; recommended supply range is 1.8 V to 3.6 V on all DVCC and AVCC pins, with 1 µF plus 100 nF low-ESR decoupling placed within a few millimeters of the pin. |+| 38 | P2.7 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, powered from DVCC. |+| 39 | P2.3 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with TA0.0, eUSCI_A1 UCA1STE, ADC/comparator input A6/C10, powered from DVCC. |+| 40 | P2.4 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with TA1.0, eUSCI_A1 UCA1CLK and ADC/comparator input A7/C11, powered from DVCC. |+| 41 | AVSS3 | power_in | Analog ground supply (0 V) for the analog domain. |+| 42 | PJ.6 | bidirectional | General-purpose digital I/O (PJ.6) that serves as HFXIN, the input for the high-frequency crystal oscillator HFXT or a digital clock in HFXTBYPASS mode. |+| 43 | PJ.7 | bidirectional | General-purpose digital I/O (PJ.7) that serves as HFXOUT, the output of the high-frequency crystal oscillator HFXT; it is free for general-purpose use when HFXT is bypassed. |+| 44 | AVSS2 | power_in | Analog ground supply (0 V) for the analog domain. |+| 45 | PJ.4 | bidirectional | General-purpose digital I/O (PJ.4) that serves as LFXIN, the input for the low-frequency crystal oscillator LFXT or a digital clock in LFXTBYPASS mode. |+| 46 | PJ.5 | bidirectional | General-purpose digital I/O (PJ.5) that serves as LFXOUT, the output of the low-frequency crystal oscillator LFXT; it is free for general-purpose use when LFXT is bypassed. |+| 47 | AVSS1 | power_in | Analog ground supply (0 V) for the analog domain. |+| 48 | AVCC1 | power_in | Analog power supply; recommended supply range is 1.8 V to 3.6 V, and the voltage difference between AVCC and DVCC must not exceed the absolute maximum limit of ±0.3 V. |+| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-48-EP(7x7) |+| Category | Embedded Processors & Controllers |+| Pins | 49 |++## CAD (KiCad official)++- Symbol: `MSP430FR5962IRGZR`+- Footprint: `Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm`+- 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)+- 3D model files: `msp430fr5962irgzr-etched.step` / `msp430fr5962irgzr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `msp430fr5962irgzr.step` / `msp430fr5962irgzr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/msp430fr5992) (177 pp, sha256 `305369231542d625`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/msp430fr5962irgzr-datasheet.pdf)
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keep open when used as JTAG pin."+ },+ {+ "number": "13",+ "name": "PJ.1",+ "type": "bidirectional",+ "description": "General-purpose digital I/O (PJ.1) multiplexed with JTAG TDI/TCLK, MCLK, CPU status bit SCG0 and comparator input C7, LVCMOS buffer powered from DVCC; keep open when used as JTAG pin."+ },+ {+ "number": "14",+ "name": "PJ.2",+ "type": "bidirectional",+ "description": "General-purpose digital I/O (PJ.2) multiplexed with JTAG TMS, ACLK, CPU status bit OSCOFF and comparator input C8, LVCMOS buffer powered from DVCC; keep open when used as JTAG pin."+ },+ {+ "number": "15",+ "name": "PJ.3",+ "type": "bidirectional",+ "description": "General-purpose digital I/O (PJ.3) multiplexed with JTAG TCK, CPU status bit CPUOFF and comparator input C9, LVCMOS buffer powered from DVCC; keep open when used as JTAG pin."+ },+ {+ "number": "16",+ "name": "P4.0",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with ADC input A8, powered from DVCC."+ },+ {+ "number": "17",+ "name": "P4.1",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with ADC input A9, powered from DVCC."+ },+ {+ "number": "18",+ "name": "P4.2",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with ADC input A10, powered from DVCC."+ },+ {+ "number": "19",+ "name": "P4.3",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with ADC input A11, powered from DVCC."+ },+ {+ "number": "20",+ "name": "P2.5",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with TB0.0 and eUSCI_A1 UCA1TXD/UCA1SIMO, powered from DVCC."+ },+ {+ "number": "21",+ "name": "P2.6",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with TB0.1 and eUSCI_A1 UCA1RXD/UCA1SOMI, powered from DVCC."+ },+ {+ "number": "22",+ "name": "TEST",+ "type": "input",+ "description": "Test mode pin that selects digital I/O on the JTAG pins and serves as SBWTCK for Spy-Bi-Wire; it always has an internal pulldown of 20 to 50 kΩ enabled, and should be left open."+ },+ {+ "number": "23",+ "name": "RST",+ "type": "input",+ "description": "Active-low reset input, also multiplexed as NMI and SBWTDIO; if unused, connect to DVCC through a 47 kΩ pullup or use the internal pullup with a 10 nF pulldown (2.2 nF in Spy-Bi-Wire or 4-wire JTAG mode)."+ },+ {+ "number": "24",+ "name": "P2.0",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with TB0.6, eUSCI_A0 UCA0TXD/UCA0SIMO, TB0CLK and ACLK; this pin becomes BSLTX on devices with UART BSL."+ },+ {+ "number": "25",+ "name": "P2.1",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with TB0.0 and eUSCI_A0 UCA0RXD/UCA0SOMI; this pin becomes BSLRX on devices with UART BSL."+ },+ {+ "number": "26",+ "name": "P2.2",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with TB0.2 and eUSCI_B0 UCB0CLK, powered from DVCC."+ },+ {+ "number": "27",+ "name": "P3.4",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with TB0.3 and SMCLK, powered from DVCC."+ },+ {+ "number": "28",+ "name": "P3.5",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with TB0.4 and COUT, powered from DVCC."+ },+ {+ "number": "29",+ "name": "P3.6",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with TB0.5, powered from DVCC."+ },+ {+ "number": "30",+ "name": "P3.7",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with TB0.6, powered from DVCC."+ },+ {+ "number": "31",+ "name": "P1.6",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with TB0.3, eUSCI_B0 UCB0SIMO/UCB0SDA and TA0.0; this pin becomes BSLSDA on devices with I2C BSL."+ },+ {+ "number": "32",+ "name": "P1.7",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with TB0.4, eUSCI_B0 UCB0SOMI/UCB0SCL and TA1.0; this pin becomes BSLSCL on devices with I2C BSL."+ },+ {+ "number": "33",+ "name": "P4.4",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with TB0.5, powered from DVCC."+ },+ {+ "number": "34",+ "name": "P4.5",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt and wake-up from LPMx.5, powered from DVCC."+ },+ {+ "number": "35",+ "name": "P4.6",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt and wake-up from LPMx.5, powered from DVCC."+ },+ {+ "number": "36",+ "name": "DVSS1",+ "type": "power_in",+ "description": "Digital ground supply (0 V) for the digital domain."+ },+ {+ "number": "37",+ "name": "DVCC1",+ "type": "power_in",+ "description": "Digital power supply; recommended supply range is 1.8 V to 3.6 V on all DVCC and AVCC pins, with 1 µF plus 100 nF low-ESR decoupling placed within a few millimeters of the pin."+ },+ {+ "number": "38",+ "name": "P2.7",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt and wake-up from LPMx.5, powered from DVCC."+ },+ {+ "number": "39",+ "name": "P2.3",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with TA0.0, eUSCI_A1 UCA1STE, ADC/comparator input A6/C10, powered from DVCC."+ },+ {+ "number": "40",+ "name": "P2.4",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with TA1.0, eUSCI_A1 UCA1CLK and ADC/comparator input A7/C11, powered from DVCC."+ },+ {+ "number": "41",+ "name": "AVSS3",+ "type": "power_in",+ "description": "Analog ground supply (0 V) for the analog domain."+ },+ {+ "number": "42",+ "name": "PJ.6",+ "type": "bidirectional",+ "description": "General-purpose digital I/O (PJ.6) that serves as HFXIN, the input for the high-frequency crystal oscillator HFXT or a digital clock in HFXTBYPASS mode."+ },+ {+ "number": "43",+ "name": "PJ.7",+ "type": "bidirectional",+ "description": "General-purpose digital I/O (PJ.7) that serves as HFXOUT, the output of the high-frequency crystal oscillator HFXT; it is free for general-purpose use when HFXT is bypassed."+ },+ {+ "number": "44",+ "name": "AVSS2",+ "type": "power_in",+ "description": "Analog ground supply (0 V) for the analog domain."+ },+ {+ "number": "45",+ "name": "PJ.4",+ "type": "bidirectional",+ "description": "General-purpose digital I/O (PJ.4) that serves as LFXIN, the input for the low-frequency crystal oscillator LFXT or a digital clock in LFXTBYPASS mode."+ },+ {+ "number": "46",+ "name": "PJ.5",+ "type": "bidirectional",+ "description": "General-purpose digital I/O (PJ.5) that serves as LFXOUT, the output of the low-frequency crystal oscillator LFXT; it is free for general-purpose use when LFXT is bypassed."+ },+ {+ "number": "47",+ "name": "AVSS1",+ "type": "power_in",+ "description": "Analog ground supply (0 V) for the analog domain."+ },+ {+ "number": "48",+ "name": "AVCC1",+ "type": "power_in",+ "description": "Analog power supply; recommended supply range is 1.8 V to 3.6 V, and the voltage difference between AVCC and DVCC must not exceed the absolute maximum limit of ±0.3 V."+ },+ {+ "number": "49",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The supplied text omits PDF pages 15-17, which hold the RGZ rows of Table 4-1 for pins 23-40. Pins 1; The QFN exposed thermal pad (named 'Pad' in Table 4-1, with no printed number) is not included in pi; Pins DGND (A1, K2, K10, L1, L11), AGND (A11, B10), DVSS2 (A2), DVCC2 (A3), DVSS3 (J1) and DVCC3 (K1)",+ "exposed pad 49 added from the footprint"+ ],+ "pages_sent": 79,+ "cost_usd": 0.3914,+ "at": "2026-10-08T04:48:56"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/msp430fr5992",+ "pages": 177,+ "sha256": "305369231542d625",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 49,+ "described": 49,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "msp430fr5962irgzr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 7,+ 7,+ 0.77+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "f2b38b0b4bf967c77e683e8d4599608b9f0503055ec535b93c4ebb5d0163e916",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "msp430fr5962irgzr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 7,+ 7,+ 0.77+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "9fef775a3d636e3a2322cbdc5bac5835baeed02ae1259bec0fd39b797508b988",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}