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MSP430FR5962IRGZR
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMSP430FR5962IRGZR
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · VQFN-48-EP(7x7)
MSP430FR5962IRGZR from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P1.0 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with TA0.1, DMAE0, RTCCLK, ADC/comparator input A0/C0 and VREF-/VeREF- reference, LVCMOS buffer powered from DVCC. |
| 2 | P1.1 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with TA0.2, TA1CLK, COUT, ADC/comparator input A1/C1 and VREF+/VeREF+ reference, LVCMOS buffer powered from DVCC. |
| 3 | P1.2 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with TA1.1, TA0CLK, COUT and ADC/comparator input A2/C2, LVCMOS buffer powered from DVCC. |
| 4 | P3.0 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with ADC/comparator input A12/C12, LVCMOS buffer powered from DVCC. |
| 5 | P3.1 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with ADC/comparator input A13/C13, LVCMOS buffer powered from DVCC. |
| 6 | P3.2 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with ADC/comparator input A14/C14, LVCMOS buffer powered from DVCC. |
| 7 | P3.3 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with ADC/comparator input A15/C15, LVCMOS buffer powered from DVCC. |
| 8 | P4.7 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, LVCMOS buffer powered from DVCC. |
| 9 | P1.3 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with TA1.2, UCB0STE, ADC/comparator input A3/C3, LVCMOS buffer powered from DVCC. |
| 10 | P1.4 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with TB0.1, UCA0STE, ADC/comparator input A4/C4, LVCMOS buffer powered from DVCC. |
| 11 | P1.5 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with TB0.2, UCA0CLK, ADC/comparator input A5/C5, LVCMOS buffer powered from DVCC. |
| 12 | PJ.0 | bidirectional | General-purpose digital I/O (PJ.0) multiplexed with JTAG TDO, TB0OUTH, SMCLK, CPU status bit SCG1 and comparator input C6, LVCMOS buffer powered from DVCC; keep open when used as JTAG pin. |
| 13 | PJ.1 | bidirectional | General-purpose digital I/O (PJ.1) multiplexed with JTAG TDI/TCLK, MCLK, CPU status bit SCG0 and comparator input C7, LVCMOS buffer powered from DVCC; keep open when used as JTAG pin. |
| 14 | PJ.2 | bidirectional | General-purpose digital I/O (PJ.2) multiplexed with JTAG TMS, ACLK, CPU status bit OSCOFF and comparator input C8, LVCMOS buffer powered from DVCC; keep open when used as JTAG pin. |
| 15 | PJ.3 | bidirectional | General-purpose digital I/O (PJ.3) multiplexed with JTAG TCK, CPU status bit CPUOFF and comparator input C9, LVCMOS buffer powered from DVCC; keep open when used as JTAG pin. |
| 16 | P4.0 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with ADC input A8, powered from DVCC. |
| 17 | P4.1 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with ADC input A9, powered from DVCC. |
| 18 | P4.2 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with ADC input A10, powered from DVCC. |
| 19 | P4.3 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with ADC input A11, powered from DVCC. |
| 20 | P2.5 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with TB0.0 and eUSCI_A1 UCA1TXD/UCA1SIMO, powered from DVCC. |
| 21 | P2.6 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with TB0.1 and eUSCI_A1 UCA1RXD/UCA1SOMI, powered from DVCC. |
| 22 | TEST | input | Test mode pin that selects digital I/O on the JTAG pins and serves as SBWTCK for Spy-Bi-Wire; it always has an internal pulldown of 20 to 50 kΩ enabled, and should be left open. |
| 23 | RST | input | Active-low reset input, also multiplexed as NMI and SBWTDIO; if unused, connect to DVCC through a 47 kΩ pullup or use the internal pullup with a 10 nF pulldown (2.2 nF in Spy-Bi-Wire or 4-wire JTAG mode). |
| 24 | P2.0 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with TB0.6, eUSCI_A0 UCA0TXD/UCA0SIMO, TB0CLK and ACLK; this pin becomes BSLTX on devices with UART BSL. |
| 25 | P2.1 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with TB0.0 and eUSCI_A0 UCA0RXD/UCA0SOMI; this pin becomes BSLRX on devices with UART BSL. |
| 26 | P2.2 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with TB0.2 and eUSCI_B0 UCB0CLK, powered from DVCC. |
| 27 | P3.4 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with TB0.3 and SMCLK, powered from DVCC. |
| 28 | P3.5 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with TB0.4 and COUT, powered from DVCC. |
| 29 | P3.6 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with TB0.5, powered from DVCC. |
| 30 | P3.7 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with TB0.6, powered from DVCC. |
| 31 | P1.6 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with TB0.3, eUSCI_B0 UCB0SIMO/UCB0SDA and TA0.0; this pin becomes BSLSDA on devices with I2C BSL. |
| 32 | P1.7 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with TB0.4, eUSCI_B0 UCB0SOMI/UCB0SCL and TA1.0; this pin becomes BSLSCL on devices with I2C BSL. |
| 33 | P4.4 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with TB0.5, powered from DVCC. |
| 34 | P4.5 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, powered from DVCC. |
| 35 | P4.6 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, powered from DVCC. |
| 36 | DVSS1 | power_in | Digital ground supply (0 V) for the digital domain. |
| 37 | DVCC1 | power_in | Digital power supply; recommended supply range is 1.8 V to 3.6 V on all DVCC and AVCC pins, with 1 µF plus 100 nF low-ESR decoupling placed within a few millimeters of the pin. |
| 38 | P2.7 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, powered from DVCC. |
| 39 | P2.3 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with TA0.0, eUSCI_A1 UCA1STE, ADC/comparator input A6/C10, powered from DVCC. |
| 40 | P2.4 | bidirectional | General-purpose digital I/O with port interrupt and wake-up from LPMx.5, multiplexed with TA1.0, eUSCI_A1 UCA1CLK and ADC/comparator input A7/C11, powered from DVCC. |
| 41 | AVSS3 | power_in | Analog ground supply (0 V) for the analog domain. |
| 42 | PJ.6 | bidirectional | General-purpose digital I/O (PJ.6) that serves as HFXIN, the input for the high-frequency crystal oscillator HFXT or a digital clock in HFXTBYPASS mode. |
| 43 | PJ.7 | bidirectional | General-purpose digital I/O (PJ.7) that serves as HFXOUT, the output of the high-frequency crystal oscillator HFXT; it is free for general-purpose use when HFXT is bypassed. |
| 44 | AVSS2 | power_in | Analog ground supply (0 V) for the analog domain. |
| 45 | PJ.4 | bidirectional | General-purpose digital I/O (PJ.4) that serves as LFXIN, the input for the low-frequency crystal oscillator LFXT or a digital clock in LFXTBYPASS mode. |
| 46 | PJ.5 | bidirectional | General-purpose digital I/O (PJ.5) that serves as LFXOUT, the output of the low-frequency crystal oscillator LFXT; it is free for general-purpose use when LFXT is bypassed. |
| 47 | AVSS1 | power_in | Analog ground supply (0 V) for the analog domain. |
| 48 | AVCC1 | power_in | Analog power supply; recommended supply range is 1.8 V to 3.6 V, and the voltage difference between AVCC and DVCC must not exceed the absolute maximum limit of ±0.3 V. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-48-EP(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 49 |
CAD (KiCad official)
- Symbol:
MSP430FR5962IRGZR - Footprint:
Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm - 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
- 3D model files:
msp430fr5962irgzr-etched.step/msp430fr5962irgzr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);msp430fr5962irgzr.step/msp430fr5962irgzr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (177 pp, sha256
305369231542d625, retrieved 2026-10-08, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).