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MSP430FR5730IRGER
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), VQFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+62@@ -0,0 +1,62 @@+# MSP430FR5730IRGER++**Texas Instruments** · Microcontrollers (MCU/MPU/SOC) · VQFN-24-EP(4x4)++MSP430FR5730IRGER from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | P1.0/TA0.1/DMAE0/RTCCLK/A0/CD0/VeREF- | bidirectional | General-purpose digital I/O with port interrupt and LPMx.5 wake-up, multiplexed with TA0 CCR1, external DMA trigger, RTC clock calibration output, ADC input A0, Comparator_D input CD0 and external reference VeREF-. |+| 2 | P1.1/TA0.2/TA1CLK/CDOUT/A1/CD1/VeREF+ | bidirectional | General-purpose digital I/O with port interrupt and LPMx.5 wake-up, multiplexed with TA0 CCR2, TA1 input clock, Comparator_D output, ADC input A1, Comparator_D input CD1 and external reference VeREF+. |+| 3 | P1.2/TA1.1/TA0CLK/CDOUT/A2/CD2 | bidirectional | General-purpose digital I/O with port interrupt and LPMx.5 wake-up, multiplexed with TA1 CCR1, TA0 input clock, Comparator_D output, ADC input A2 and Comparator_D input CD2. |+| 4 | P1.3/TA1.2/UCB0STE/A3/CD3 | bidirectional | General-purpose digital I/O with port interrupt and LPMx.5 wake-up, multiplexed with TA1 CCR2, eUSCI_B0 SPI slave transmit enable, ADC input A3 and Comparator_D input CD3. |+| 5 | P1.4/TB0.1/UCA0STE/A4/CD4 | bidirectional | General-purpose digital I/O with port interrupt and LPMx.5 wake-up, multiplexed with TB0 CCR1, eUSCI_A0 SPI slave transmit enable, ADC input A4 and Comparator_D input CD4. |+| 6 | P1.5/TB0.2/UCA0CLK/A5/CD5 | bidirectional | General-purpose digital I/O with port interrupt and LPMx.5 wake-up, multiplexed with TB0 CCR2, eUSCI_A0 SPI clock (input in slave, output in master), ADC input A5 and Comparator_D input CD5. |+| 7 | PJ.0/TDO/TB0OUTH/SMCLK/CD6 | bidirectional | General-purpose digital I/O multiplexed with JTAG test data output, TB0 switch-all-PWM-outputs-high-impedance input, SMCLK output and Comparator_D input CD6. |+| 8 | PJ.1/TDI/TCLK/TB1OUTH/MCLK/CD7 | bidirectional | General-purpose digital I/O multiplexed with JTAG test data input or test clock input, TB1 high-impedance input, MCLK output and Comparator_D input CD7. |+| 9 | PJ.2/TMS/TB2OUTH/ACLK/CD8 | bidirectional | General-purpose digital I/O multiplexed with JTAG test mode select, TB2 high-impedance input, ACLK output and Comparator_D input CD8. |+| 10 | PJ.3/TCK/CD9 | bidirectional | General-purpose digital I/O multiplexed with JTAG test clock and Comparator_D input CD9. |+| 11 | TEST/SBWTCK | input | Test mode pin that enables the JTAG pins, also the Spy-Bi-Wire input clock. |+| 12 | RST/NMI/SBWTDIO | bidirectional | Active-low reset input, non-maskable interrupt input and Spy-Bi-Wire data input/output. |+| 13 | P2.0/TB2.0/UCA0TXD/UCA0SIMO/TB0CLK/ACLK | bidirectional | General-purpose digital I/O with port interrupt and LPMx.5 wake-up, multiplexed with TB2 CCR0, eUSCI_A0 UART transmit data / SPI slave in master out, TB0 clock input and ACLK output. |+| 14 | P2.1/TB2.1/UCA0RXD/UCA0SOMI/TB0.0 | bidirectional | General-purpose digital I/O with port interrupt and LPMx.5 wake-up, multiplexed with TB2 CCR1, eUSCI_A0 UART receive data / SPI slave out master in, and TB0 CCR0. |+| 15 | P2.2/TB2.2/UCB0CLK/TB1.0 | bidirectional | General-purpose digital I/O with port interrupt and LPMx.5 wake-up, multiplexed with TB2 CCR2, eUSCI_B0 SPI clock (input in slave, output in master) and TB1 CCR0. |+| 16 | P1.6/TB1.1/UCB0SIMO/UCB0SDA/TA0.0 | bidirectional | General-purpose digital I/O with port interrupt and LPMx.5 wake-up, multiplexed with TB1 CCR1, eUSCI_B0 SPI slave in master out / I2C data, and TA0 CCR0. |+| 17 | P1.7/TB1.2/UCB0SOMI/UCB0SCL/TA1.0 | bidirectional | General-purpose digital I/O with port interrupt and LPMx.5 wake-up, multiplexed with TB1 CCR2, eUSCI_B0 SPI slave out master in / I2C clock, and TA1 CCR0. |+| 18 | VCORE | power_in | Regulated core power supply for internal use only with no external current loading possible; connect only to the recommended capacitor CVCORE. |+| 19 | DVSS | power_in | Digital ground supply. |+| 20 | DVCC | power_in | Digital power supply. |+| 21 | PJ.4/XIN | bidirectional | General-purpose digital I/O and input terminal for crystal oscillator XT1. |+| 22 | PJ.5/XOUT | bidirectional | General-purpose digital I/O and output terminal of crystal oscillator XT1. |+| 23 | AVSS | power_in | Analog ground supply. |+| 24 | AVCC | power_in | Analog power supply. |+| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-24-EP(4x4) |+| Category | Embedded Processors & Controllers |+| Pins | 25 |++## CAD (KiCad official)++- Symbol: `MSP430FR5730IRGER`+- Footprint: `Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm`+- 3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)+- 3D model files: `msp430fr5730irger-etched.step` / `msp430fr5730irger-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `msp430fr5730irger.step` / `msp430fr5730irger.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/msp430fr5730) (127 pp, sha256 `977283ebe184e278`, retrieved 2026-10-05, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/msp430fr5730irger-datasheet.pdf)
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Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "embedded processors & controllers",+ "msp430fr5730irger",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "msp430fr5730irger.kicad_sym",+ "msp430fr5730irger.kicad_mod",+ "msp430fr5730irger.glb",+ "msp430fr5730irger.step",+ "msp430fr5730irger.lbr",+ "docs/hero.png",+ "docs/msp430fr5730irger-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "msp430fr5730irger-hero.glb",+ "msp430fr5730irger-hero.overlay.json"+ ],+ "component": {+ "mpn": "MSP430FR5730IRGER",+ "manufacturer": "Texas Instruments",+ "package": "VQFN-24-EP(4x4)",+ "pin_count": 25,+ "category": "Embedded Processors & Controllers",+ "subcategory": "Microcontrollers (MCU/MPU/SOC)",+ "datasheet": "https://www.ti.com/cn/lit/gpn/msp430fr5730",+ "parts": {+ "symbol": "msp430fr5730irger.kicad_sym",+ "footprint": "msp430fr5730irger.kicad_mod",+ "model_3d": "msp430fr5730irger-hero.glb",+ "model_3d_plain": "msp430fr5730irger.glb",+ "model_3d_step": "msp430fr5730irger-etched.step",+ "model_3d_step_plain": "msp430fr5730irger.step",+ "lbr": "msp430fr5730irger.lbr"+ },+ "distributor_links": {+ "lcsc": 2053451,+ "digikey": "296-29228-2-ND",+ "mouser": "595-SP430FR5730IRGER"+ },+ "distributor_check": {+ "checked_at": "2026-10-05T21:38:50Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-29228-2-ND",+ "status": "found"+ },+ "mouser": {+ "pn": "595-SP430FR5730IRGER",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "P1.0/TA0.1/DMAE0/RTCCLK/A0/CD0/VeREF-",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt and LPMx.5 wake-up, multiplexed with TA0 CCR1, external DMA trigger, RTC clock calibration output, ADC input A0, Comparator_D input CD0 and external reference VeREF-."+ },+ {+ "number": "2",+ "name": "P1.1/TA0.2/TA1CLK/CDOUT/A1/CD1/VeREF+",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt and LPMx.5 wake-up, multiplexed with TA0 CCR2, TA1 input clock, Comparator_D output, ADC input A1, Comparator_D input CD1 and external reference VeREF+."+ },+ {+ "number": "3",+ "name": "P1.2/TA1.1/TA0CLK/CDOUT/A2/CD2",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt and LPMx.5 wake-up, multiplexed with TA1 CCR1, TA0 input clock, Comparator_D output, ADC input A2 and Comparator_D input CD2."+ },+ {+ "number": "4",+ "name": "P1.3/TA1.2/UCB0STE/A3/CD3",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt and LPMx.5 wake-up, multiplexed with TA1 CCR2, eUSCI_B0 SPI slave transmit enable, ADC input A3 and Comparator_D input CD3."+ },+ {+ "number": "5",+ "name": "P1.4/TB0.1/UCA0STE/A4/CD4",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt and LPMx.5 wake-up, multiplexed with TB0 CCR1, eUSCI_A0 SPI slave transmit enable, ADC input A4 and Comparator_D input CD4."+ },+ {+ "number": "6",+ "name": "P1.5/TB0.2/UCA0CLK/A5/CD5",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt and LPMx.5 wake-up, multiplexed with TB0 CCR2, eUSCI_A0 SPI clock (input in slave, output in master), ADC input A5 and Comparator_D input CD5."+ },+ {+ "number": "7",+ "name": "PJ.0/TDO/TB0OUTH/SMCLK/CD6",+ "type": "bidirectional",+ "description": "General-purpose digital I/O multiplexed with JTAG test data output, TB0 switch-all-PWM-outputs-high-impedance input, SMCLK output and Comparator_D input CD6."+ },+ {+ "number": "8",+ "name": "PJ.1/TDI/TCLK/TB1OUTH/MCLK/CD7",+ "type": "bidirectional",+ "description": "General-purpose digital I/O multiplexed with JTAG test data input or test clock input, TB1 high-impedance input, MCLK output and Comparator_D input CD7."+ },+ {+ "number": "9",+ "name": "PJ.2/TMS/TB2OUTH/ACLK/CD8",+ "type": "bidirectional",+ "description": "General-purpose digital I/O multiplexed with JTAG test mode select, TB2 high-impedance input, ACLK output and Comparator_D input CD8."+ },+ {+ "number": "10",+ "name": "PJ.3/TCK/CD9",+ "type": "bidirectional",+ "description": "General-purpose digital I/O multiplexed with JTAG test clock and Comparator_D input CD9."+ },+ {+ "number": "11",+ "name": "TEST/SBWTCK",+ "type": "input",+ "description": "Test mode pin that enables the JTAG pins, also the Spy-Bi-Wire input clock."+ },+ {+ "number": "12",+ "name": "RST/NMI/SBWTDIO",+ "type": "bidirectional",+ "description": "Active-low reset input, non-maskable interrupt input and Spy-Bi-Wire data input/output."+ },+ {+ "number": "13",+ "name": "P2.0/TB2.0/UCA0TXD/UCA0SIMO/TB0CLK/ACLK",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt and LPMx.5 wake-up, multiplexed with TB2 CCR0, eUSCI_A0 UART transmit data / SPI slave in master out, TB0 clock input and ACLK output."+ },+ {+ "number": "14",+ "name": "P2.1/TB2.1/UCA0RXD/UCA0SOMI/TB0.0",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt and LPMx.5 wake-up, multiplexed with TB2 CCR1, eUSCI_A0 UART receive data / SPI slave out master in, and TB0 CCR0."+ },+ {+ "number": "15",+ "name": "P2.2/TB2.2/UCB0CLK/TB1.0",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt and LPMx.5 wake-up, multiplexed with TB2 CCR2, eUSCI_B0 SPI clock (input in slave, output in master) and TB1 CCR0."+ },+ {+ "number": "16",+ "name": "P1.6/TB1.1/UCB0SIMO/UCB0SDA/TA0.0",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt and LPMx.5 wake-up, multiplexed with TB1 CCR1, eUSCI_B0 SPI slave in master out / I2C data, and TA0 CCR0."+ },+ {+ "number": "17",+ "name": "P1.7/TB1.2/UCB0SOMI/UCB0SCL/TA1.0",+ "type": "bidirectional",+ "description": "General-purpose digital I/O with port interrupt and LPMx.5 wake-up, multiplexed with TB1 CCR2, eUSCI_B0 SPI slave out master in / I2C clock, and TA1 CCR0."+ },+ {+ "number": "18",+ "name": "VCORE",+ "type": "power_in",+ "description": "Regulated core power supply for internal use only with no external current loading possible; connect only to the recommended capacitor CVCORE."+ },+ {+ "number": "19",+ "name": "DVSS",+ "type": "power_in",+ "description": "Digital ground supply."+ },+ {+ "number": "20",+ "name": "DVCC",+ "type": "power_in",+ "description": "Digital power supply."+ },+ {+ "number": "21",+ "name": "PJ.4/XIN",+ "type": "bidirectional",+ "description": "General-purpose digital I/O and input terminal for crystal oscillator XT1."+ },+ {+ "number": "22",+ "name": "PJ.5/XOUT",+ "type": "bidirectional",+ "description": "General-purpose digital I/O and output terminal of crystal oscillator XT1."+ },+ {+ "number": "23",+ "name": "AVSS",+ "type": "power_in",+ "description": "Analog ground supply."+ },+ {+ "number": "24",+ "name": "AVCC",+ "type": "power_in",+ "description": "Analog power supply."+ },+ {+ "number": "25",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: MSP430FR5730 has only Timer_B0 available; TB1OUTH, TB2OUTH, TB2.x, TB1.x, and TB1CLK functions liste; Exposed thermal pad (QFN pad) shown in package diagram with recommended connection to VSS/DVSS; not ; ADC functionality (A0-A7) is only available on devices that include ADC10_B module; verify device va",+ "exposed pad 25 added from the footprint"+ ],+ "pages_sent": 49,+ "cost_usd": 0.446,+ "at": "2026-10-05T21:38:35"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/msp430fr5730",+ "pages": 127,+ "sha256": "977283ebe184e278",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 25,+ "described": 25,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}