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MSP430FR5730IRGER
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), VQFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMSP430FR5730IRGER
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · VQFN-24-EP(4x4)
MSP430FR5730IRGER from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P1.0/TA0.1/DMAE0/RTCCLK/A0/CD0/VeREF- | bidirectional | General-purpose digital I/O with port interrupt and LPMx.5 wake-up, multiplexed with TA0 CCR1, external DMA trigger, RTC clock calibration output, ADC input A0, Comparator_D input CD0 and external reference VeREF-. |
| 2 | P1.1/TA0.2/TA1CLK/CDOUT/A1/CD1/VeREF+ | bidirectional | General-purpose digital I/O with port interrupt and LPMx.5 wake-up, multiplexed with TA0 CCR2, TA1 input clock, Comparator_D output, ADC input A1, Comparator_D input CD1 and external reference VeREF+. |
| 3 | P1.2/TA1.1/TA0CLK/CDOUT/A2/CD2 | bidirectional | General-purpose digital I/O with port interrupt and LPMx.5 wake-up, multiplexed with TA1 CCR1, TA0 input clock, Comparator_D output, ADC input A2 and Comparator_D input CD2. |
| 4 | P1.3/TA1.2/UCB0STE/A3/CD3 | bidirectional | General-purpose digital I/O with port interrupt and LPMx.5 wake-up, multiplexed with TA1 CCR2, eUSCI_B0 SPI slave transmit enable, ADC input A3 and Comparator_D input CD3. |
| 5 | P1.4/TB0.1/UCA0STE/A4/CD4 | bidirectional | General-purpose digital I/O with port interrupt and LPMx.5 wake-up, multiplexed with TB0 CCR1, eUSCI_A0 SPI slave transmit enable, ADC input A4 and Comparator_D input CD4. |
| 6 | P1.5/TB0.2/UCA0CLK/A5/CD5 | bidirectional | General-purpose digital I/O with port interrupt and LPMx.5 wake-up, multiplexed with TB0 CCR2, eUSCI_A0 SPI clock (input in slave, output in master), ADC input A5 and Comparator_D input CD5. |
| 7 | PJ.0/TDO/TB0OUTH/SMCLK/CD6 | bidirectional | General-purpose digital I/O multiplexed with JTAG test data output, TB0 switch-all-PWM-outputs-high-impedance input, SMCLK output and Comparator_D input CD6. |
| 8 | PJ.1/TDI/TCLK/TB1OUTH/MCLK/CD7 | bidirectional | General-purpose digital I/O multiplexed with JTAG test data input or test clock input, TB1 high-impedance input, MCLK output and Comparator_D input CD7. |
| 9 | PJ.2/TMS/TB2OUTH/ACLK/CD8 | bidirectional | General-purpose digital I/O multiplexed with JTAG test mode select, TB2 high-impedance input, ACLK output and Comparator_D input CD8. |
| 10 | PJ.3/TCK/CD9 | bidirectional | General-purpose digital I/O multiplexed with JTAG test clock and Comparator_D input CD9. |
| 11 | TEST/SBWTCK | input | Test mode pin that enables the JTAG pins, also the Spy-Bi-Wire input clock. |
| 12 | RST/NMI/SBWTDIO | bidirectional | Active-low reset input, non-maskable interrupt input and Spy-Bi-Wire data input/output. |
| 13 | P2.0/TB2.0/UCA0TXD/UCA0SIMO/TB0CLK/ACLK | bidirectional | General-purpose digital I/O with port interrupt and LPMx.5 wake-up, multiplexed with TB2 CCR0, eUSCI_A0 UART transmit data / SPI slave in master out, TB0 clock input and ACLK output. |
| 14 | P2.1/TB2.1/UCA0RXD/UCA0SOMI/TB0.0 | bidirectional | General-purpose digital I/O with port interrupt and LPMx.5 wake-up, multiplexed with TB2 CCR1, eUSCI_A0 UART receive data / SPI slave out master in, and TB0 CCR0. |
| 15 | P2.2/TB2.2/UCB0CLK/TB1.0 | bidirectional | General-purpose digital I/O with port interrupt and LPMx.5 wake-up, multiplexed with TB2 CCR2, eUSCI_B0 SPI clock (input in slave, output in master) and TB1 CCR0. |
| 16 | P1.6/TB1.1/UCB0SIMO/UCB0SDA/TA0.0 | bidirectional | General-purpose digital I/O with port interrupt and LPMx.5 wake-up, multiplexed with TB1 CCR1, eUSCI_B0 SPI slave in master out / I2C data, and TA0 CCR0. |
| 17 | P1.7/TB1.2/UCB0SOMI/UCB0SCL/TA1.0 | bidirectional | General-purpose digital I/O with port interrupt and LPMx.5 wake-up, multiplexed with TB1 CCR2, eUSCI_B0 SPI slave out master in / I2C clock, and TA1 CCR0. |
| 18 | VCORE | power_in | Regulated core power supply for internal use only with no external current loading possible; connect only to the recommended capacitor CVCORE. |
| 19 | DVSS | power_in | Digital ground supply. |
| 20 | DVCC | power_in | Digital power supply. |
| 21 | PJ.4/XIN | bidirectional | General-purpose digital I/O and input terminal for crystal oscillator XT1. |
| 22 | PJ.5/XOUT | bidirectional | General-purpose digital I/O and output terminal of crystal oscillator XT1. |
| 23 | AVSS | power_in | Analog ground supply. |
| 24 | AVCC | power_in | Analog power supply. |
| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-24-EP(4x4) |
| Category | Embedded Processors & Controllers |
| Pins | 25 |
CAD (KiCad official)
- Symbol:
MSP430FR5730IRGER - Footprint:
Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm - 3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)
- 3D model files:
msp430fr5730irger-etched.step/msp430fr5730irger-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);msp430fr5730irger.step/msp430fr5730irger.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (127 pp, sha256
977283ebe184e278, retrieved 2026-10-05, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).