component
MSP430FR5726IRGER
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), VQFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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{
"schema_version": 1,
"type": "component",
"slug": "msp430fr5726irger",
"title": "MSP430FR5726IRGER",
"brief": "Texas Instruments Microcontrollers (MCU/MPU/SOC), VQFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"version": "0.1.0",
"license": "CC-BY-SA-4.0",
"tags": [
"component",
"embedded processors & controllers",
"msp430fr5726irger",
"factory-2.0.0",
"extractor-text"
],
"component": {
"mpn": "MSP430FR5726IRGER",
"manufacturer": "Texas Instruments",
"package": "VQFN-24-EP(4x4)",
"pin_count": 25,
"category": "Embedded Processors & Controllers",
"subcategory": "Microcontrollers (MCU/MPU/SOC)",
"datasheet": "https://www.ti.com/cn/lit/gpn/msp430fr5721",
"parts": {
"symbol": "msp430fr5726irger.kicad_sym",
"footprint": "msp430fr5726irger.kicad_mod",
"model_3d": "msp430fr5726irger-hero.glb",
"model_3d_plain": "msp430fr5726irger.glb",
"model_3d_step": "msp430fr5726irger-etched.step",
"model_3d_step_plain": "msp430fr5726irger.step",
"lbr": "msp430fr5726irger.lbr"
},
"distributor_links": {
"lcsc": "C2056390",
"digikey": "MSP430FR5726IRGER-ND",
"mouser": "595-SP430FR5726IRGER"
},
"distributor_check": {
"checked_at": "2026-10-08T22:30:44Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": "MSP430FR5726IRGER-ND",
"status": "found"
},
"mouser": {
"pn": "595-SP430FR5726IRGER",
"status": "found"
}
},
"pins": [
{
"number": "1",
"name": "P1.0/TA0.1/DMAE0/RTCCLK/A0/CD0/VeREF-",
"type": "bidirectional",
"description": "General-purpose digital I/O with port interrupt and wake-up from LPMx.5, also selectable as TA0.1, external DMA trigger DMAE0, RTC clock calibration output, ADC input A0, Comparator_D input CD0, or external reference VeREF-."
},
{
"number": "2",
"name": "P1.1/TA0.2/TA1CLK/CDOUT/A1/CD1/VeREF+",
"type": "bidirectional",
"description": "General-purpose digital I/O with port interrupt and wake-up from LPMx.5, also selectable as TA0.2, TA1 input clock, Comparator_D output, ADC input A1, Comparator_D input CD1, or external ADC reference VeREF+."
},
{
"number": "3",
"name": "P1.2/TA1.1/TA0CLK/CDOUT/A2/CD2",
"type": "bidirectional",
"description": "General-purpose digital I/O with port interrupt and wake-up from LPMx.5, also selectable as TA1.1, TA0 input clock, Comparator_D output, ADC input A2, or Comparator_D input CD2."
},
{
"number": "4",
"name": "P1.3/TA1.2/UCB0STE/A3/CD3",
"type": "bidirectional",
"description": "General-purpose digital I/O with port interrupt and wake-up from LPMx.5, also selectable as TA1.2, eUSCI_B0 SPI slave transmit enable, ADC input A3, or Comparator_D input CD3."
},
{
"number": "5",
"name": "P1.4/TB0.1/UCA0STE/A4/CD4",
"type": "bidirectional",
"description": "General-purpose digital I/O with port interrupt and wake-up from LPMx.5, also selectable as TB0.1, eUSCI_A0 SPI slave transmit enable, ADC input A4, or Comparator_D input CD4."
},
{
"number": "6",
"name": "P1.5/TB0.2/UCA0CLK/A5/CD5",
"type": "bidirectional",
"description": "General-purpose digital I/O with port interrupt and wake-up from LPMx.5, also selectable as TB0.2, eUSCI_A0 clock (SPI slave input / master output), ADC input A5, or Comparator_D input CD5."
},
{
"number": "7",
"name": "PJ.0/TDO/TB0OUTH/SMCLK/CD6",
"type": "bidirectional",
"description": "General-purpose digital I/O, also selectable as JTAG test data output TDO, TB0 high-impedance switch input, SMCLK output, or Comparator_D input CD6."
},
{
"number": "8",
"name": "PJ.1/TDI/TCLK/TB1OUTH/MCLK/CD7",
"type": "bidirectional",
"description": "General-purpose digital I/O, also selectable as JTAG test data input or test clock TDI/TCLK, TB1 high-impedance switch input, MCLK output, or Comparator_D input CD7."
},
{
"number": "9",
"name": "PJ.2/TMS/TB2OUTH/ACLK/CD8",
"type": "bidirectional",
"description": "General-purpose digital I/O, also selectable as JTAG test mode select TMS, TB2 high-impedance switch input, ACLK output, or Comparator_D input CD8."
},
{
"number": "10",
"name": "PJ.3/TCK/CD9",
"type": "bidirectional",
"description": "General-purpose digital I/O, also selectable as JTAG test clock TCK or Comparator_D input CD9."
},
{
"number": "11",
"name": "TEST/SBWTCK",
"type": "input",
"description": "Test mode pin that enables the JTAG pins, and serves as the Spy-Bi-Wire input clock."
},
{
"number": "12",
"name": "RST/NMI/SBWTDIO",
"type": "bidirectional",
"description": "Active-low reset input, non-maskable interrupt input, and Spy-Bi-Wire data input/output."
},
{
"number": "13",
"name": "P2.0/TB2.0/UCA0TXD/UCA0SIMO/TB0CLK/ACLK",
"type": "bidirectional",
"description": "General-purpose digital I/O with port interrupt and wake-up from LPMx.5, also selectable as TB2.0, eUSCI_A0 UART transmit data or SPI slave-in/master-out, TB0 clock input, or ACLK output."
},
{
"number": "14",
"name": "P2.1/TB2.1/UCA0RXD/UCA0SOMI/TB0.0",
"type": "bidirectional",
"description": "General-purpose digital I/O with port interrupt and wake-up from LPMx.5, also selectable as TB2.1, eUSCI_A0 UART receive data or SPI slave-out/master-in, or TB0.0."
},
{
"number": "15",
"name": "P2.2/TB2.2/UCB0CLK/TB1.0",
"type": "bidirectional",
"description": "General-purpose digital I/O with port interrupt and wake-up from LPMx.5, also selectable as TB2.2, eUSCI_B0 clock (SPI slave input / master output), or TB1.0."
},
{
"number": "16",
"name": "P1.6/TB1.1/UCB0SIMO/UCB0SDA/TA0.0",
"type": "bidirectional",
"description": "General-purpose digital I/O with port interrupt and wake-up from LPMx.5, also selectable as TB1.1, eUSCI_B0 SPI slave-in/master-out or I2C data, or TA0.0."
},
{
"number": "17",
"name": "P1.7/TB1.2/UCB0SOMI/UCB0SCL/TA1.0",
"type": "bidirectional",
"description": "General-purpose digital I/O with port interrupt and wake-up from LPMx.5, also selectable as TB1.2, eUSCI_B0 SPI slave-out/master-in or I2C clock, or TA1.0."
},
{
"number": "18",
"name": "VCORE",
"type": "power_out",
"description": "Regulated core power supply for internal use only; no external current loading is possible and it should only be connected to the recommended capacitor CVCORE."
},
{
"number": "19",
"name": "DVSS",
"type": "power_in",
"description": "Digital ground supply."
},
{
"number": "20",
"name": "DVCC",
"type": "power_in",
"description": "Digital power supply."
},
{
"number": "21",
"name": "PJ.4/XIN",
"type": "bidirectional",
"description": "General-purpose digital I/O, or input terminal for crystal oscillator XT1 (or external clock in bypass mode)."
},
{
"number": "22",
"name": "PJ.5/XOUT",
"type": "bidirectional",
"description": "General-purpose digital I/O, or output terminal of crystal oscillator XT1."
},
{
"number": "23",
"name": "AVSS",
"type": "power_in",
"description": "Analog ground supply."
},
{
"number": "24",
"name": "AVCC",
"type": "power_in",
"description": "Analog power supply."
},
{
"number": "25",
"name": "EP",
"type": "passive",
"description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: The pin diagram figure for the RGE package (Figure 4-3, page 8) is not reliably extractable from the; The QFN exposed thermal pad is not given a printed pin number (listed as 'QFN Pad'). It is omitted f; Table 4-1 notes that P2.3, P2.4, P2.7, P3.x, P4.x and P2.5/P2.6 are not available on the RGE package",
"exposed pad 25 added from the footprint"
],
"pages_sent": 48,
"cost_usd": 0.2845,
"at": "2026-10-08T22:30:14"
},
"datasheet": {
"url": "https://www.ti.com/cn/lit/gpn/msp430fr5721",
"pages": 127,
"sha256": "6a2750fecbf4b926",
"source_tier": "lcsc"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 25,
"described": 25,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
"symbol": "viewers/symbol.html",
"footprint": "viewers/footprint.html"
},
"models_3d": [
{
"file": "msp430fr5726irger.step",
"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
4,
4,
0.77
],
"zmin_mm": 0,
"centre_offset_mm": 0,
"footprint_binding": "identity",
"sha256": "f7d256794c4147daf24dcae0554fae18510315e565ad1e239b475be7fef80d8b",
"checked": "2026-10-08",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "msp430fr5726irger-etched.step",
"role": "eda",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
4,
4,
0.77
],
"zmin_mm": 0,
"centre_offset_mm": 0,
"footprint_binding": "identity",
"sha256": "2b451365e1db33810061c786b385d6eff73b116b5a35999c0be69ec698947d2b",
"checked": "2026-10-08",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
]
},
"metadata": {
"specs": {
"Manufacturer": "Texas Instruments",
"Package": "VQFN-24-EP(4x4)",
"Category": "Embedded Processors & Controllers",
"Pins": "25"
}
},
"variants": [],
"sections": [
"hero",
"viewers",
"readme",
"breadcrumbs",
"info"
],
"discovery_triggers": [
"msp430fr5726irger"
],
"discovery_pitch": "MSP430FR5726IRGER (Texas Instruments) component page: datasheet pinout, KiCad symbol, footprint and 3D.",
"author": {
"name": "Ray",
"email": "[email protected]"
},
"dependencies": {},
"hero": {
"type": "image",
"path": "docs/hero.png"
},
"files": [
"page.json",
"README.md",
"msp430fr5726irger.kicad_sym",
"msp430fr5726irger.kicad_mod",
"msp430fr5726irger.glb",
"msp430fr5726irger.step",
"msp430fr5726irger.lbr",
"docs/hero.png",
"docs/msp430fr5726irger-datasheet.pdf",
"viewers/symbol.html",
"viewers/footprint.html",
"msp430fr5726irger-hero.glb",
"msp430fr5726irger-hero.overlay.json"
],
"visibility": {
"public": true
}
}