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MSP430FR5720IRGER
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), QFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMSP430FR5720IRGER
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · QFN-24-EP(4x4)
MSP430FR5720IRGER from Texas Instruments, in a QFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P1.0/TA0.1/DMAE0/RTCCLK/A0/CD0/VeREF- | bidirectional | General-purpose digital I/O with port interrupt and LPMx.5 wake-up; TA0 CCR1 capture/compare, external DMA trigger, RTC clock calibration output, ADC input A0, Comparator_D input CD0, external reference voltage (not available on devices without ADC). |
| 2 | P1.1/TA0.2/TA1CLK/CDOUT/A1/CD1/VeREF+ | bidirectional | General-purpose digital I/O with port interrupt and LPMx.5 wake-up; TA0 CCR2 capture/compare, TA1 input clock, Comparator_D output, ADC input A1, Comparator_D input CD1, input for external reference voltage (not available on devices without ADC). |
| 3 | P1.2/TA1.1/TA0CLK/CDOUT/A2/CD2 | bidirectional | General-purpose digital I/O with port interrupt and LPMx.5 wake-up; TA1 CCR1 capture/compare, TA0 input clock, Comparator_D output, ADC input A2 (not available on devices without ADC), Comparator_D input CD2. |
| 4 | P1.3/TA1.2/UCB0STE/A3/CD3 | bidirectional | General-purpose digital I/O with port interrupt and LPMx.5 wake-up; TA1 CCR2 capture/compare, eUSCI_B0 SPI slave transmit enable, ADC input A3 (not available on devices without ADC), Comparator_D input CD3. |
| 5 | P1.4/TB0.1/UCA0STE/A4/CD4 | bidirectional | General-purpose digital I/O with port interrupt and LPMx.5 wake-up; TB0 CCR1 capture/compare, eUSCI_A0 SPI slave transmit enable, ADC input A4 (not available on devices without ADC), Comparator_D input CD4. |
| 6 | P1.5/TB0.2/UCA0CLK/A5/CD5 | bidirectional | General-purpose digital I/O with port interrupt and LPMx.5 wake-up; TB0 CCR2 capture/compare, eUSCI_A0 SPI clock signal (input in slave mode, output in master mode), ADC input A5 (not available on devices without ADC), Comparator_D input CD5. |
| 7 | PJ.0/TDO/TB0OUTH/SMCLK/CD6 | bidirectional | General-purpose digital I/O; JTAG test data output; switch all TB0 PWM outputs to high impedance; SMCLK clock output; Comparator_D input CD6. |
| 8 | PJ.1/TDI/TCLK/TB1OUTH/MCLK/CD7 | bidirectional | General-purpose digital I/O; JTAG test data or test clock input; switch all TB1 PWM outputs to high impedance (not available on MSP430FR5720); MCLK clock output; Comparator_D input CD7. |
| 9 | PJ.2/TMS/TB2OUTH/ACLK/CD8 | bidirectional | General-purpose digital I/O; JTAG test mode select; switch all TB2 PWM outputs to high impedance (not available on MSP430FR5720); ACLK clock output; Comparator_D input CD8. |
| 10 | PJ.3/TCK/CD9 | bidirectional | General-purpose digital I/O; JTAG test clock input; Comparator_D input CD9. |
| 11 | TEST/SBWTCK | input | Test mode enable pin to activate JTAG signals; Spy-Bi-Wire input clock for serial programming and debugging. |
| 12 | RST/NMI/SBWTDIO | bidirectional | Reset input (active low); non-maskable interrupt input; Spy-Bi-Wire data input/output for JTAG debugging and BSL programming. |
| 13 | P2.0/TB2.0/UCA0TXD/UCA0SIMO/TB0CLK/ACLK | bidirectional | General-purpose digital I/O with port interrupt and LPMx.5 wake-up; TB2 CCR0 capture/compare (not available on MSP430FR5720); eUSCI_A0 UART transmit data or SPI slave-in-master-out; TB0 clock input; ACLK clock output. |
| 14 | P2.1/TB2.1/UCA0RXD/UCA0SOMI/TB0.0 | bidirectional | General-purpose digital I/O with port interrupt and LPMx.5 wake-up; TB2 CCR1 capture/compare (not available on MSP430FR5720); eUSCI_A0 UART receive data or SPI slave-out-master-in; TB0 CCR0 capture/compare. |
| 15 | P2.2/TB2.2/UCB0CLK/TB1.0 | bidirectional | General-purpose digital I/O with port interrupt and LPMx.5 wake-up; TB2 CCR2 capture/compare (not available on MSP430FR5720); eUSCI_B0 SPI clock (input in slave mode, output in master mode); TB1 CCR0 capture/compare (not available on MSP430FR5720). |
| 16 | P1.6/TB1.1/UCB0SIMO/UCB0SDA/TA0.0 | bidirectional | General-purpose digital I/O with port interrupt and LPMx.5 wake-up; TB1 CCR1 capture/compare (not available on MSP430FR5720); eUSCI_B0 SPI slave-in-master-out or I2C SDA; TA0 CCR0 capture/compare. |
| 17 | P1.7/TB1.2/UCB0SOMI/UCB0SCL/TA1.0 | bidirectional | General-purpose digital I/O with port interrupt and LPMx.5 wake-up; TB1 CCR2 capture/compare (not available on MSP430FR5720); eUSCI_B0 SPI slave-out-master-in or I2C SCL; TA1 CCR0 capture/compare. |
| 18 | VCORE | power_in | Regulated core power supply for internal CPU use only; no external DC loading permissible; connect 470 nF capacitor to VSS for decoupling. |
| 19 | DVSS | power_in | Digital ground supply; reference point for all digital circuits and measurements. |
| 20 | DVCC | power_in | Digital power supply; voltage range 2.0 V to 3.6 V recommended for program execution and FRAM write operations. |
| 21 | PJ.4/XIN | bidirectional | General-purpose digital I/O; crystal oscillator XT1 input terminal for low-frequency (32 kHz) or high-frequency crystal operation; bypass input when XT1BYPASS enabled. |
| 22 | PJ.5/XOUT | bidirectional | General-purpose digital I/O; crystal oscillator XT1 output terminal for low-frequency or high-frequency crystal operation; configurable as GPIO when XT1BYPASS enabled. |
| 23 | AVSS | power_in | Analog ground supply; reference point for all analog circuits, ADC, comparator, and reference module; connect to DVSS. |
| 24 | AVCC | power_in | Analog power supply; voltage range 2.0 V to 3.6 V; connect to DVCC with maximum 0.3 V difference during operation. |
| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | QFN-24-EP(4x4) |
| Category | Embedded Processors & Controllers |
| Pins | 25 |
CAD (KiCad official)
- Symbol:
MSP430FR5720IRGER - Footprint:
Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm - 3D model: QFN-24-EP(4x4) (KiCad packages3D, STEP)
- 3D model files:
msp430fr5720irger-etched.step/msp430fr5720irger-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);msp430fr5720irger.step/msp430fr5720irger.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (121 pp, sha256
b5aa02b1a6c2f458, retrieved 2026-09-22, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).