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MSP430FR5043IRGCT

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TEXAS INSTRUMENTS Global Sourcing Parts, VQFN-64(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentglobal sourcing partsmsp430fr5043irgctfactory-2.0.0extractor-text

Changed since verified MSP430FR5043IRGCT

by Ray · last 30 Oct 2026 · 1 record · files changed since
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Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 65 pinschanged since
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  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: MSP430FR5043IRGCT · VQFN-64(9x9) · 65 pins
  • ✓copper: 65 copper pads, none touching another net
  • ✓datasheet: all 65 pin names found in the 196-page datasheet
  • ✓distributor: lcsc C5218420, digikey 296-MSP430FR5043IRGTR-ND, mouser 595-SP430FR5043IRGCT
  • ✓family: QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-_qs_1qrr/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 65 pins = 65 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 65 pins agree
  • ✓visibility: public, source open
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verification.json Verified: Published by the parts factory: tier mfr, 65 pins · Ray 6d ago

MSP430FR5043IRGCT

TEXAS INSTRUMENTS · Global Sourcing Parts · VQFN-64(9x9)

MSP430FR5043IRGCT from TEXAS INSTRUMENTS, in a VQFN-64(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AVCC1 power_in Analog power supply; AVCC and DVCC must be supplied within 1.8 V to 3.6 V and should come from the same source.
2 P2.2/COUT/UCA0CLK/A14/C14 bidirectional General-purpose digital I/O with port interrupt and wakeup from LPMx.5, also serving as comparator output COUT and ADC input A14.
3 P1.0/UCA1CLK/TA1.0/A0/C0/VREF-/VeREF- bidirectional General-purpose digital I/O with port interrupt and wakeup from LPMx.5, also serving as ADC analog input A0 and negative reference VREF- output.
4 P1.1/UCA1STE/TA4.0/A1/C1/VREF+/VeREF+ bidirectional General-purpose digital I/O with port interrupt and wakeup from LPMx.5, also serving as ADC analog input A1 and positive reference VREF+ output.
5 AVSS2 power_in Analog ground supply, 0 V reference for the analog circuitry.
6 PJ.4/LFXIN input General-purpose digital I/O or input to the low-frequency crystal oscillator LFXT.
7 PJ.5/LFXOUT output General-purpose digital I/O or output of the low-frequency crystal oscillator LFXT.
8 AVSS3 power_in Analog ground supply, 0 V reference for the analog circuitry.
9 PJ.6/HFXIN/USSXT_BOUT bidirectional General-purpose digital I/O or input to the high-frequency crystal oscillator HFXT, also buffered USSXT clock output.
10 PJ.7/HFXOUT output General-purpose digital I/O or output of the high-frequency crystal oscillator HFXT.
11 TEST/SBWCLK input Test mode pin that selects digital I/O on the JTAG pins; it always has an internal pulldown enabled and is also the Spy-Bi-Wire input clock.
12 RST/NMI/SBWTDIO bidirectional Reset input, active low, which can also be configured as nonmaskable interrupt input NMI or Spy-Bi-Wire data input/output.
13 PJ.0/UAC2CLK/SRSCG1/DMAE0/C10/TDO bidirectional General-purpose digital I/O that serves as JTAG test data output TDO, with comparator input C10 and DMA trigger DMAE0 as alternate functions.
14 PJ.1/UCA2STE/SRSCG0/TA4CLK/C11/TDI/TCLK bidirectional General-purpose digital I/O that serves as JTAG test data input TDI and test clock TCLK, with comparator input C11 as an alternate function.
15 PJ.2/UCA2SIMO/UCA2TXD/SROSCOFF/TB0OUTH/C12/TMS bidirectional General-purpose digital I/O that serves as JTAG test mode select TMS, with comparator input C12 as an alternate function.
16 PJ.3/UCA2SOMI/UCA2RXD/SRCPUOFF/TB0.6/C13/TCK bidirectional General-purpose digital I/O that serves as JTAG test clock TCK, with comparator input C13 as an alternate function.
17 DVSS1 power_in Digital ground supply, 0 V reference for the digital circuitry.
18 DVCC1 power_in Digital power supply; DVCC must be supplied within 1.8 V to 3.6 V and decoupled with 100 nF close to the pin.
19 P1.2/UCA1SIMO/UCA1TXD/TA1.0/A8/C8 bidirectional General-purpose digital I/O with port interrupt and wakeup from LPMx.5, also serving as ADC analog input A8 and comparator input C8.
20 P1.3/UCA1SOMI/UCA1RXD/TA1.1/A9/C9 bidirectional General-purpose digital I/O with port interrupt and wakeup from LPMx.5, also serving as ADC analog input A9 and comparator input C9.
21 P2.0/UCA1CLK/UCA3SIMO/UCA3TXD bidirectional General-purpose digital I/O with port interrupt and wakeup from LPMx.5; on devices with UART BSL this pin is BSLTX.
22 P2.1/UCA1STE/UCA3SOMI/UCA3RXD bidirectional General-purpose digital I/O with port interrupt and wakeup from LPMx.5; on devices with UART BSL this pin is BSLRX.
23 P1.6/UCA3STE/UCB0SIMO/UCB0SDA bidirectional General-purpose digital I/O with port interrupt and wakeup from LPMx.5; on devices with I2C BSL this pin is BSLSDA.
24 P1.7/USSTRG/UCA3CLK/UCB0SOMI/UCB0SCL bidirectional General-purpose digital I/O with port interrupt and wakeup from LPMx.5, also serving as USS trigger USSTRG; on devices with I2C BSL this pin is BSLSCL.
25 P1.4/TB0.4/UCB0STE/A2/C2 bidirectional General-purpose digital I/O with port interrupt and wakeup from LPMx.5, also serving as ADC analog input A2 and comparator input C2.
26 P1.5/TB0.5/UCB0CLK/A3/C3 bidirectional General-purpose digital I/O with port interrupt and wakeup from LPMx.5, also serving as ADC analog input A3 and comparator input C3.
27 P3.1/TA1CLK/TB0.1/MTIF_OUT_IN bidirectional General-purpose digital I/O with port interrupt and wakeup from LPMx.5, also serving as Meter Test Interface input/output MTIF_OUT_IN.
28 P4.0/RTCCLK/TA4.1/MTIF_PIN_EN bidirectional General-purpose digital I/O with port interrupt and wakeup from LPMx.5, also serving as RTC clock calibration output RTCCLK and Meter Test Interface pin enable.
29 P4.1/UCA0CLK/TB0.4/UCA3SOMI/UCA3RXD bidirectional General-purpose digital I/O with port interrupt and wakeup from LPMx.5, also serving as eUSCI_A0 clock signal.
30 P4.2/UCA0STE/TB0.5/UCA3SIMO/UCA3TXD bidirectional General-purpose digital I/O with port interrupt and wakeup from LPMx.5, also serving as eUSCI_A0 slave transmit enable.
31 P4.3/UCA0SIMO/UCA0TXD bidirectional General-purpose digital I/O with port interrupt and wakeup from LPMx.5, also serving as eUSCI_A0 SPI slave-in/master-out or UART transmit data.
32 P4.4/UCA0SOMI/UCA0RXD bidirectional General-purpose digital I/O with port interrupt and wakeup from LPMx.5, also serving as eUSCI_A0 SPI slave-out/master-in or UART receive data.
33 DVSS2 power_in Digital ground supply, 0 V reference for the digital circuitry.
34 P5.0/TB0.0/UCA2SIMO/UCA2TXD bidirectional General-purpose digital I/O with port interrupt and wakeup from LPMx.5, also serving as Timer_B0 CCR0 and eUSCI_A2 SPI/UART transmit function.
35 P5.1/TB0.1/UCA2SOMI/UCA2RXD bidirectional General-purpose digital I/O with port interrupt and wakeup from LPMx.5, also serving as Timer_B0 CCR1 and eUSCI_A2 SPI/UART receive function.
36 P5.2/TB0.2/UAC2CLK bidirectional General-purpose digital I/O with port interrupt and wakeup from LPMx.5, also serving as Timer_B0 CCR2 and eUSCI_A2 clock signal.
37 P5.3/TB0.3/UCA2STE bidirectional General-purpose digital I/O with port interrupt and wakeup from LPMx.5, also serving as Timer_B0 CCR3 and eUSCI_A2 slave transmit enable.
38 P5.4/TA0.0/UCB1CLK/TA4.0 bidirectional General-purpose digital I/O with port interrupt and wakeup from LPMx.5, also serving as Timer_A0 CCR0 and eUSCI_B1 clock signal.
39 P5.5/TA4.1/UCB1SIMO/UCB1SDA bidirectional General-purpose digital I/O with port interrupt and wakeup from LPMx.5, also serving as Timer_A4 CCR1 and eUSCI_B1 I2C data.
40 P5.6/TB0OUTH/UCB1SOMI/UCB1SCL bidirectional General-purpose digital I/O with port interrupt and wakeup from LPMx.5, also serving as Timer_B0 output-high-impedance input TB0OUTH and eUSCI_B1 I2C clock.
41 P5.7/TA0.2/UCB1STE bidirectional General-purpose digital I/O with port interrupt and wakeup from LPMx.5, also serving as Timer_A0 CCR2 and eUSCI_B1 slave transmit enable.
42 P6.0/TA0CLK/COUT bidirectional General-purpose digital I/O with port interrupt and wakeup from LPMx.5, also serving as Timer_A0 input clock and comparator output COUT.
43 P6.4/MCLK bidirectional General-purpose digital I/O with port interrupt and wakeup from LPMx.5, also serving as MCLK output.
44 P6.5/SMCLK bidirectional General-purpose digital I/O with port interrupt and wakeup from LPMx.5, also serving as SMCLK output.
45 P6.6/ACLK bidirectional General-purpose digital I/O with port interrupt and wakeup from LPMx.5, also serving as ACLK output.
46 P7.0/TA1.0/TA1.2/XPB0 bidirectional General-purpose digital I/O with port interrupt and wakeup from LPMx.5, also serving as Timer_A1 CCR0/CCR2 output and external bias output XPB0.
47 P6.2/TB0CLK bidirectional General-purpose digital I/O with port interrupt and wakeup from LPMx.5, also serving as Timer_B0 input clock TB0CLK.
48 DVSS3 power_in Digital ground supply, 0 V reference for the digital circuitry.
49 DVCC3 power_in Digital power supply; DVCC must be supplied within 1.8 V to 3.6 V and decoupled with 100 nF close to the pin.
50 P3.3/MCLK/TB0.3/XPB1 bidirectional General-purpose digital I/O with port interrupt and wakeup from LPMx.5, also serving as MCLK output and external bias output XPB1.
51 P3.4/SMCLK/DMAE0 bidirectional General-purpose digital I/O with port interrupt and wakeup from LPMx.5, also serving as SMCLK output and external DMA trigger DMAE0.
52 P3.5/ACLK/COUT bidirectional General-purpose digital I/O with port interrupt and wakeup from LPMx.5, also serving as ACLK output and comparator output COUT.
53 CH1_IN input USS Channel 1 receive input; voltage applied must not exceed 1.65 V (1.8 V for 10% duty cycle over 1 ms) per the absolute maximum ratings.
54 CH1_OUT bidirectional USS Channel 1 transmit output, powered from PVCC; diode current at any device pin is limited to ±2 mA.
55 PVSS power_in USS ground supply; PVSS is connected to ground at 0 V.
56 PVCC power_in USS power supply, 2.2 V to 3.6 V; a 22-µF low-ESR ceramic capacitor is recommended close to the PVCC/PVSS pair.
57 PVCC power_in USS power supply, 2.2 V to 3.6 V; a 22-µF low-ESR ceramic capacitor is recommended close to the PVCC/PVSS pair.
58 PVSS power_in USS ground supply; PVSS is connected to ground at 0 V.
59 CH0_OUT bidirectional USS Channel 0 transmit output, powered from PVCC; ESD rating ±1000 V HBM and ±250 V CDM.
60 CH0_IN input USS Channel 0 receive input; voltage applied must not exceed 1.65 V (1.8 V for 10% duty cycle over 1 ms) per the absolute maximum ratings.
61 AVSS4 power_in Analog ground supply, 0 V reference for the analog circuitry.
62 USSXTIN input Input for the USSXT oscillator; must not be connected to AVCC or DVCC, and an external clock must not be driven into it.
63 USSXTOUT output Output for the USSXT oscillator; must not be connected to AVCC or DVCC.
64 AVSS1 power_in Analog ground supply, 0 V reference for the analog circuitry.
65 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer TEXAS INSTRUMENTS
Package VQFN-64(9x9)
Category Global Sourcing Parts
Pins 65

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Voltage applied at DVCC and AVCC pins to VSS -0.3 4.1 V 29
Voltage applied at DVCC, AVCC, and PVCC pins to VSS -0.3 4.1 V 29
Voltage difference between DVCC and AVCC pins -0.3 0.3 V 29
Voltage difference between DVCC, AVCC, and PVCC pins -0.3 0.3 V 29
Voltage applied to CHx_IN -0.3 1.65 V 29
Voltage applied to CHx_IN -0.3 1.8 V duty cycle of 10% over 1ms 29
Voltage applied to USSXTIN (USSXTOUT) -0.3 1.5 V 29
Voltage applied to any other pin -0.3 V max printed as VCC + 0.3 V (4.1 V Max) 29
Diode current at any device pin -2 2 mA 29
Storage temperature Tstg -40 125 °C 29
Supply voltage range applied at all DVCC and AVCC pins VCC 1.8 3.6 V 30
Supply voltage range applied at PVCC pin VCC 2.2 3.6 V 30
Operating free-air temperature TA -40 85 °C 30
Processor frequency (maximum MCLK frequency) fSYSTEM 0 8 MHz No FRAM wait states (NWAITSx = 0) 30
Processor frequency (maximum MCLK frequency) fSYSTEM 0 16 MHz With FRAM wait states (NWAITSx = 1) 30
LEA processor frequency fLEA 0 16 MHz 30
Maximum ACLK frequency fACLK 50 kHz 30
Maximum SMCLK frequency fSMCLK 16 MHz 30
Capacitor value at DVCC CDVCC 1 µF printed tolerance -20% 30
Positive-going input threshold voltage VIT+ 1.2 1.65 V VCC = 2.2 V 46
Positive-going input threshold voltage VIT+ 1.65 2.25 V VCC = 3.0 V 46
Negative-going input threshold voltage VIT- 0.55 1 V VCC = 2.2 V 46
Negative-going input threshold voltage VIT- 0.75 1.35 V VCC = 3.0 V 46
Input voltage hysteresis (VIT+, VIT-) Vhys 0.44 0.98 V VCC = 2.2 V 46
Input voltage hysteresis (VIT+, VIT-) Vhys 0.6 1.3 V VCC = 3.0 V 46
Pullup or pulldown resistor RPull 20 35 50 kΩ For pullup: VIN = VSS; for pulldown: VIN = VCC 46
High-impedance input leakage current Ilkg(Px.y) -20 20 nA VCC 2.2 V, 3.0 V; refer to notes (2) and (3) 46
LFXT oscillator logic-level square-wave input frequency fLFXT,SW 10.5 32.768 50 kHz LFXTBYPASS = 1 39
DCO frequency range 1 MHz, trimmed fDCO1 -3.5 3.5 % DCORSEL = 0, DCOFSEL = 0; DCORSEL = 1, DCOFSEL = 0 42
DCO frequency range 4 MHz, trimmed fDCO4 -3.5 3.5 % DCORSEL = 0, DCOFSEL = 3 42
DCO frequency range 5.3 MHz, trimmed fDCO5.3 -3.5 3.5 % DCORSEL = 0, DCOFSEL = 4; DCORSEL = 1, DCOFSEL = 1 42
DCO frequency range 7 MHz, trimmed fDCO7 -3.5 3.5 % DCORSEL = 0, DCOFSEL = 5; DCORSEL = 1, DCOFSEL = 2 42
DCO frequency range 8 MHz, trimmed fDCO8 -3.5 3.5 % DCORSEL = 0, DCOFSEL = 6; DCORSEL = 1, DCOFSEL = 3 42
DCO frequency range 16 MHz, trimmed fDCO16 -3.5 3.5 % DCORSEL = 1, DCOFSEL = 4 42
DCO frequency range 21 MHz, trimmed fDCO21 -3.5 3.5 % DCORSEL = 1, DCOFSEL = 5 42
DCO frequency range 24 MHz, trimmed fDCO24 -3.5 3.5 % DCORSEL = 1, DCOFSEL = 6 42
DCO duty cycle fDCO,DC 48 50 52 % Measured at SMCLK, divide by 1 42
DCO temperature drift dfDCO/dT 0.01 %/°C 3.0 V 42
VLO frequency fVLO 6 9.4 14 kHz Measured at ACLK 42
MODOSC frequency fMODOSC 4 4.8 5.4 MHz 43
Brownout power-down level VVCC_BOR- 0.7 1.66 V /dDVCC/dt/ < 3 V/s 38
Brownout power-up level VVCC_BOR+ 0.79 1.68 V /dDVCC/dt/ < 3 V/s 38
SVSH power-down level VSVSH- 1.75 1.8 1.85 V 38
SVSH power-up level VSVSH+ 1.77 1.88 1.99 V 38
LCD supply voltage range, charge pump enabled, VLCD ≤ 3.6 V VCC,LCD_C,CPen,3.6 2.2 3.6 V LCDCPEN = 1, 0000b < VLCDx ≤ 1111b 56
External LCD reference voltage applied at LCDREF VLCDREF 0.8 1 1.2 V VLCDREFx = 01 56
LCD voltage VLCD,15 3.32 3.44 3.6 V LCDCPEN = 1, VLCDx = 1111b, 2.2 V to 3.6 V 57
Positive built-in reference voltage output VREF+ -1.5 1.5 % REFVSEL = {2} for 2.5 V, REFON = 1 63
Positive built-in reference voltage output VREF+ -1.8 1.8 % REFVSEL = {0} for 1.2 V, REFON = 1 63
Reference voltage level VREF 1.152 1.2 1.248 V CERSx = 11, CEREFLx = 01, CEREFACC = 0, VCC 1.8 V 64
Input offset voltage VOFFSET -16 16 mV CEPWRMD = 00 64
Junction-to-ambient thermal resistance, still air, RGC-64 RθJA 24.7 °C/W 37
Junction-to-case (top) thermal resistance, RGC-64 RθJC(TOP) 12.3 °C/W 37
Junction-to-board thermal resistance, RGC-64 RθJB 8.8 °C/W 37

CAD (KiCad official)

  • Symbol: MSP430FR5043IRGCT
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: VQFN-64(9x9) (KiCad packages3D, STEP)
  • 3D model files: msp430fr5043irgct-etched.step / msp430fr5043irgct-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); msp430fr5043irgct.step / msp430fr5043irgct.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TEXAS INSTRUMENTS datasheet (196 pp, sha256 fa67b9472dc353be, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF