component
MSP430FR2676TRHAR
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), VQFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownMSP430FR2676TRHAR
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · VQFN-40-EP(6x6)
MSP430FR2676TRHAR from Texas Instruments, in a VQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DVCC | power_in | Main supply for the digital and analog modules, with recommended 4.7 µF to 10 µF bulk and 0.1 µF decoupling; VCC is 1.8 V to 3.6 V in CapTIvate VREG mode (default) or 2.7 V to 3.6 V in DVCC electrode charge mode, with an absolute maximum of -0.3 V to 4.1 V. |
| 2 | RST/NMI/SBWTDIO | input | Reset input (pull-up enabled after BOR) that can alternatively be configured as NMI or as the Spy-Bi-Wire data pin SBWTDIO; if unused, connect to DVCC through a 47 kΩ pull-up or internal pull-up with a 10 nF (or 1.1 nF) pull-down. |
| 3 | TEST/SBWTCK | input | Test-mode pin that doubles as the Spy-Bi-Wire clock SBWTCK; it always has an internal pull-down enabled and should be left open if unused. |
| 4 | P1.4/UCA0TXD/UCA0SIMO/TA1.2/TCK/A4/VREF+ | bidirectional | General-purpose I/O (OFF after BOR) with eUSCI_A0 TXD/SIMO, Timer TA1.2, JTAG TCK, ADC input A4 and VREF+ output; when A4 is used the 1.2 V PMM reference can be measured on this pin. |
| 5 | P1.5/UCA0RXD/UCA0SOMI/TA1.1/TMS/A5 | bidirectional | General-purpose I/O (OFF after BOR) with eUSCI_A0 RXD/SOMI, Timer TA1.1, JTAG TMS and ADC input A5. |
| 6 | P1.6/UCA0CLK/TA1CLK/TDI/TCLK/A6 | bidirectional | General-purpose I/O (OFF after BOR) with eUSCI_A0 CLK, Timer TA1CLK, JTAG TDI/TCLK and ADC input A6. |
| 7 | P1.7/UCA0STE/SMCLK/TDO/A7 | bidirectional | General-purpose I/O (OFF after BOR) with eUSCI_A0 STE, SMCLK output, JTAG TDO and ADC input A7. |
| 8 | P4.3/UCB1SOMI/UCB1SCL/TB0.5/A8 | bidirectional | General-purpose I/O (OFF after BOR) with eUSCI_B1 SOMI/SCL, Timer_B TB0.5 and ADC input A8. |
| 9 | P4.4/UCB1SIMO/UCB1SDA/TB0.6/A9 | bidirectional | General-purpose I/O (OFF after BOR) with eUSCI_B1 SIMO/SDA, Timer_B TB0.6 and ADC input A9. |
| 10 | P1.0/UCB0STE/TA0CLK/A0/Veref+ | bidirectional | General-purpose I/O with eUSCI_B0 STE, Timer TA0CLK, ADC input A0 and ADC positive reference Veref+. |
| 11 | P1.1/UCB0CLK/TA0.1/COMP0.0/A1 | bidirectional | General-purpose I/O with eUSCI_B0 CLK, Timer TA0.1, eCOMP0 input COMP0.0 and ADC input A1. |
| 12 | P1.2/UCB0SIMO/UCB0SDA/TA0.2/A2/Veref- | bidirectional | General-purpose I/O with eUSCI_B0 SIMO/SDA, Timer TA0.2, ADC input A2 and ADC negative reference Veref-. |
| 13 | P1.3/UCB0SOMI/UCB0SCL/MCLK/A3 | bidirectional | General-purpose I/O with eUSCI_B0 SOMI/SCL, MCLK output and ADC input A3. |
| 14 | P2.2/SYNC/ACLK/COMP0.1 | bidirectional | General-purpose I/O with CapTIvate synchronous trigger input SYNC, ACLK output and eCOMP0 input COMP0.1. |
| 15 | P4.5/UCB0SOMI/UCB0SCL/TA3.2 | bidirectional | Remapped eUSCI_B0 SOMI/SCL and Timer TA3.2 function (selected by the USCIBxRMP and TAxRMP bits) on a general-purpose I/O. |
| 16 | P4.6/UCB0SIMO/UCB0SDA/TA3.1 | bidirectional | Remapped eUSCI_B0 SIMO/SDA and Timer TA3.1 function (selected by the USCIBxRMP and TAxRMP bits) on a general-purpose I/O. |
| 17 | P3.0/TA2.2/CAP0.0 | bidirectional | General-purpose I/O with default Timer TA2.2 function and CapTIvate channel CAP0.0. |
| 18 | P3.3/TA2.1/CAP0.1 | bidirectional | General-purpose I/O with default Timer TA2.1 function and CapTIvate channel CAP0.1. |
| 19 | P2.3/TA2.0/CAP0.2 | bidirectional | General-purpose I/O with default Timer TA2.0 function and CapTIvate channel CAP0.2. |
| 20 | P3.4/TA2CLK/COMP0OUT/CAP0.3 | bidirectional | General-purpose I/O with default Timer TA2CLK input, eCOMP0 output COMP0OUT and CapTIvate channel CAP0.3. |
| 21 | P3.1/UCA1STE/CAP1.0 | bidirectional | General-purpose I/O with eUSCI_A1 STE and CapTIvate channel CAP1.0. |
| 22 | P2.4/UCA1CLK/CAP1.1 | bidirectional | General-purpose I/O with eUSCI_A1 CLK and CapTIvate channel CAP1.1. |
| 23 | P2.5/UCA1RXD/UCA1SOMI/CAP1.2 | bidirectional | General-purpose I/O with eUSCI_A1 RXD/SOMI and CapTIvate channel CAP1.2. |
| 24 | P2.6/UCA1TXD/UCA1SIMO/CAP1.3 | bidirectional | General-purpose I/O with eUSCI_A1 TXD/SIMO and CapTIvate channel CAP1.3. |
| 25 | VREG | power_out | Decoupling pin for the CapTIvate regulator, recommended 1 µF with maximum ESR of 200 mΩ. |
| 26 | P3.7/TA3.2/CAP2.0 | bidirectional | General-purpose I/O with default Timer TA3.2 function and CapTIvate channel CAP2.0. |
| 27 | P4.0/TA3.1/CAP2.1 | bidirectional | General-purpose I/O with default Timer TA3.1 function and CapTIvate channel CAP2.1. |
| 28 | P4.1/TA3.0/CAP2.2 | bidirectional | General-purpose I/O (OFF after BOR) with default Timer TA3.0 function and CapTIvate channel CAP2.2. |
| 29 | P4.2/TA3CLK/CAP2.3 | bidirectional | General-purpose I/O (OFF after BOR) with default Timer TA3CLK input and CapTIvate channel CAP2.3. |
| 30 | P2.7/UCB1STE/CAP3.0 | bidirectional | General-purpose I/O (OFF after BOR) with eUSCI_B1 STE and CapTIvate channel CAP3.0. |
| 31 | P3.5/UCB1CLK/TB0TRG/CAP3.1 | bidirectional | General-purpose I/O (OFF after BOR) with eUSCI_B1 CLK, Timer_B external trigger input TB0TRG and CapTIvate channel CAP3.1. |
| 32 | P3.2/UCB1SIMO/UCB1SDA/CAP3.2 | bidirectional | General-purpose I/O (OFF after BOR) with eUSCI_B1 SIMO/SDA and CapTIvate channel CAP3.2. |
| 33 | P3.6/UCB1SOMI/UCB1SCL/CAP3.3 | bidirectional | General-purpose I/O (OFF after BOR) with eUSCI_B1 SOMI/SCL and CapTIvate channel CAP3.3. |
| 34 | P4.7/UCA0STE/TB0.1 | bidirectional | General-purpose I/O (OFF after BOR) with eUSCI_A0 STE and Timer_B TB0.1. |
| 35 | P5.0/UCA0CLK/TB0.2 | bidirectional | General-purpose I/O (OFF after BOR) with eUSCI_A0 CLK and Timer_B TB0.2. |
| 36 | P5.1/UCA0RXD/UCA0SOMI/TB0.3 | bidirectional | General-purpose I/O (OFF after BOR) with eUSCI_A0 RXD/SOMI and Timer_B TB0.3. |
| 37 | P5.2/UCA0TXD/UCA0SIMO/TB0.4 | bidirectional | General-purpose I/O (OFF after BOR) with eUSCI_A0 TXD/SIMO and Timer_B TB0.4. |
| 38 | P2.0/XOUT | bidirectional | General-purpose I/O (OFF after BOR) that serves as the output terminal XOUT of the 32 kHz crystal oscillator. |
| 39 | P2.1/XIN | bidirectional | General-purpose I/O (OFF after BOR) that serves as the input terminal XIN of the 32 kHz crystal oscillator; digital clock input is possible in XT1BYPASS mode. |
| 40 | DVSS | power_in | Ground reference for the digital and analog modules; all voltages are referenced to VSS. |
| 41 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-40-EP(6x6) |
| Category | Embedded Processors & Controllers |
| Pins | 41 |
CAD (KiCad official)
- Symbol:
MSP430FR2676TRHAR - Footprint:
Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm - 3D model: VQFN-40-EP(6x6) (KiCad packages3D, STEP)
- 3D model files:
msp430fr2676trhar-etched.step/msp430fr2676trhar-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);msp430fr2676trhar.step/msp430fr2676trhar.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (129 pp, sha256
98b202cd0699eba3, retrieved 2026-10-12, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).