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MSP430FR2675TRHBR
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), VQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMSP430FR2675TRHBR
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · VQFN-32-EP(5x5)
MSP430FR2675TRHBR from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RST/NMI/SBWTDIO | bidirectional | Multiplexed reset (RST, input, pullup enabled after BOR), NMI input and Spy-Bi-Wire data I/O; for an unused pin, use a 47-kΩ pullup or the internal pullup with a 10-nF (or 1.1-nF) pulldown. |
| 2 | TEST/SBWTCK | input | Test-mode input that carries the Spy-Bi-Wire clock (SBWTCK); it always has an internal pulldown enabled, and it can be left open when unused. |
| 3 | P1.4/UCA0TXD/UCA0SIMO/TA1.2/TCK/A4/VREF+ | bidirectional | General-purpose I/O P1.4 (high-impedance with Schmitt trigger after BOR) that is also eUSCI_A0 UART TXD or SPI SIMO, Timer TA1.2, JTAG TCK, ADC input A4 and VREF+ output. |
| 4 | P1.5/UCA0RXD/UCA0SOMI/TA1.1/TMS/A5 | bidirectional | General-purpose I/O P1.5 (high-impedance after BOR) that is also eUSCI_A0 UART RXD or SPI SOMI, Timer TA1.1, JTAG TMS and ADC input A5. |
| 5 | P1.6/UCA0CLK/TA1CLK/TDI/TCLK/A6 | bidirectional | General-purpose I/O P1.6 (high-impedance after BOR) that is also eUSCI_A0 clock, Timer TA1CLK input, JTAG TDI/TCLK and ADC input A6. |
| 6 | P1.7/UCA0STE/SMCLK/TDO/A7 | bidirectional | General-purpose I/O P1.7 (high-impedance after BOR) that is also eUSCI_A0 STE, SMCLK output, JTAG TDO and ADC input A7. |
| 7 | P1.0/UCB0STE/TA0CLK/A0/Veref+ | bidirectional | General-purpose I/O P1.0 that is also eUSCI_B0 STE, Timer TA0CLK input, ADC input A0 and ADC positive reference Veref+. |
| 8 | P1.1/UCB0CLK/TA0.1/COMP0.0/A1 | bidirectional | General-purpose I/O P1.1 that is also eUSCI_B0 clock, Timer TA0.1, eCOMP0 input channel COMP0.0 and ADC input A1. |
| 9 | P1.2/UCB0SIMO/UCB0SDA/TA0.2/A2/Veref- | bidirectional | General-purpose I/O P1.2 that is also eUSCI_B0 SIMO or SDA, Timer TA0.2, ADC input A2 and ADC negative reference Veref-. |
| 10 | P1.3/UCB0SOMI/UCB0SCL/MCLK/A3 | bidirectional | General-purpose I/O P1.3 that is also eUSCI_B0 SOMI or SCL, MCLK output and ADC input A3. |
| 11 | P2.2/SYNC/ACLK/COMP0.1 | bidirectional | General-purpose I/O P2.2 that is also CapTIvate synchronous trigger input SYNC, ACLK output and eCOMP0 input channel COMP0.1. |
| 12 | P3.0/TA2.2/CAP0.0 | bidirectional | General-purpose I/O P3.0 that is also Timer TA2.2 and CapTIvate channel CAP0.0. |
| 13 | P3.3/TA2.1/CAP0.1 | bidirectional | General-purpose I/O P3.3 that is also Timer TA2.1 and CapTIvate channel CAP0.1. |
| 14 | P2.3/TA2.0/CAP0.2 | bidirectional | General-purpose I/O P2.3 that is also Timer TA2.0 and CapTIvate channel CAP0.2. |
| 15 | P3.4/TA2CLK/COMP0OUT/CAP0.3 | bidirectional | General-purpose I/O P3.4 that is also Timer TA2CLK input, eCOMP0 output COMP0OUT and CapTIvate channel CAP0.3. |
| 16 | P3.1/UCA1STE/CAP1.0 | bidirectional | General-purpose I/O P3.1 that is also eUSCI_A1 STE and CapTIvate channel CAP1.0. |
| 17 | P2.4/UCA1CLK/CAP1.1 | bidirectional | General-purpose I/O P2.4 that is also eUSCI_A1 clock and CapTIvate channel CAP1.1. |
| 18 | P2.5/UCA1RXD/UCA1SOMI/CAP1.2 | bidirectional | General-purpose I/O P2.5 that is also eUSCI_A1 UART RXD or SPI SOMI and CapTIvate channel CAP1.2. |
| 19 | P2.6/UCA1TXD/UCA1SIMO/CAP1.3 | bidirectional | General-purpose I/O P2.6 that is also eUSCI_A1 UART TXD or SPI SIMO and CapTIvate channel CAP1.3. |
| 20 | VREG | power_out | CapTIvate regulator output that requires a decoupling capacitor of 1 µF with ESR ≤ 200 mΩ. |
| 21 | P3.7/TA3.2/CAP2.0 | bidirectional | General-purpose I/O P3.7 that is also Timer TA3.2 and CapTIvate channel CAP2.0. |
| 22 | P4.0/TA3.1/CAP2.1 | bidirectional | General-purpose I/O P4.0 that is also Timer TA3.1 and CapTIvate channel CAP2.1. |
| 23 | P4.1/TA3.0/CAP2.2 | bidirectional | General-purpose I/O P4.1 that is also Timer TA3.0 and CapTIvate channel CAP2.2. |
| 24 | P4.2/TA3CLK/CAP2.3 | bidirectional | General-purpose I/O P4.2 that is also Timer TA3CLK input and CapTIvate channel CAP2.3. |
| 25 | P2.7/UCB1STE/CAP3.0 | bidirectional | General-purpose I/O P2.7 that is also eUSCI_B1 STE and CapTIvate channel CAP3.0. |
| 26 | P3.5/UCB1CLK/TB0TRG/CAP3.1 | bidirectional | General-purpose I/O P3.5 that is also eUSCI_B1 clock, Timer TB0 external trigger TB0TRG (for TB0OUTH high-impedance) and CapTIvate channel CAP3.1. |
| 27 | P3.2/UCB1SIMO/UCB1SDA/CAP3.2 | bidirectional | General-purpose I/O P3.2 that is also eUSCI_B1 SIMO or SDA and CapTIvate channel CAP3.2. |
| 28 | P3.6/UCB1SOMI/UCB1SCL/CAP3.3 | bidirectional | General-purpose I/O P3.6 that is also eUSCI_B1 SOMI or SCL and CapTIvate channel CAP3.3. |
| 29 | P2.0/XOUT | output | Output terminal of the 32-kHz crystal oscillator (XOUT), which can be used for other purposes when a digital clock is applied to XIN in XT1BYPASS mode. |
| 30 | P2.1/XIN | input | Input terminal of the low-frequency (32-kHz) crystal oscillator (XIN), which also accepts a digital clock in XT1BYPASS mode. |
| 31 | DVSS | power_in | Ground reference for the digital and analog modules, to be connected to the system ground. |
| 32 | DVCC | power_in | Main supply input for the digital and analog modules, with a recommended supply of 1.8 V to 3.6 V in CapTIvate VREG charge mode and a recommended 4.7-µF to 10-µF capacitor. |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-32-EP(5x5) |
| Category | Embedded Processors & Controllers |
| Pins | 33 |
CAD (KiCad official)
- Symbol:
MSP430FR2675TRHBR - Footprint:
Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm - 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
- 3D model files:
msp430fr2675trhbr-etched.step/msp430fr2675trhbr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);msp430fr2675trhbr.step/msp430fr2675trhbr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (129 pp, sha256
98b202cd0699eba3, retrieved 2026-10-10, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).