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MSP430FR2675TRHAR
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Texas Instruments Microcontrollers (MCU/MPU/SOC), VQFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+78@@ -0,0 +1,78 @@+# MSP430FR2675TRHAR++**Texas Instruments** · Microcontrollers (MCU/MPU/SOC) · VQFN-40-EP(6x6)++MSP430FR2675TRHAR from Texas Instruments, in a VQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | DVCC | power_in | Supply voltage for the digital and analog modules, specified 1.8 V to 3.6 V in CapTIvate VREG electrode charge mode and 2.7 V to 3.6 V in DVCC electrode charge mode, with 4.7 µF to 10 µF recommended at DVCC. |+| 2 | RST/NMI/SBWTDIO | bidirectional | Reset input (RST, pullup enabled after BOR), NMI input, or Spy-Bi-Wire data I/O (SBWTDIO); an unused pin should be tied to DVCC through a 47-kΩ pullup or internal pullup with a 10-nF (or 1.1-nF) pulldown. |+| 3 | TEST/SBWTCK | input | Test mode pin that always has an internal pulldown enabled, and Spy-Bi-Wire clock input (SBWTCK); leave open if unused. |+| 4 | P1.4/UCA0TXD/UCA0SIMO/TA1.2/TCK/A4/VREF+ | bidirectional | General-purpose I/O P1.4 with alternate eUSCI_A0 TXD/SIMO, TA1.2, JTAG TCK, ADC input A4, and VREF+; when A4 is used the 1.2-V PMM reference can be output here. |+| 5 | P1.5/UCA0RXD/UCA0SOMI/TA1.1/TMS/A5 | bidirectional | General-purpose I/O P1.5 with alternate eUSCI_A0 RXD/SOMI, TA1.1, JTAG TMS, and ADC input A5. |+| 6 | P1.6/UCA0CLK/TA1CLK/TDI/TCLK/A6 | bidirectional | General-purpose I/O P1.6 with alternate eUSCI_A0 CLK, TA1CLK, JTAG TDI/TCLK, and ADC input A6. |+| 7 | P1.7/UCA0STE/SMCLK/TDO/A7 | bidirectional | General-purpose I/O P1.7 with alternate eUSCI_A0 STE, SMCLK output, JTAG TDO, and ADC input A7. |+| 8 | P4.3/UCB1SOMI/UCB1SCL/TB0.5/A8 | bidirectional | General-purpose I/O P4.3 with alternate eUSCI_B1 SOMI/SCL, TB0.5, and ADC input A8. |+| 9 | P4.4/UCB1SIMO/UCB1SDA/TB0.6/A9 | bidirectional | General-purpose I/O P4.4 with alternate eUSCI_B1 SIMO/SDA, TB0.6, and ADC input A9. |+| 10 | P1.0/UCB0STE/TA0CLK/A0/Veref+ | bidirectional | General-purpose I/O P1.0 with alternate eUSCI_B0 STE, TA0CLK, ADC input A0, and ADC positive reference Veref+. |+| 11 | P1.1/UCB0CLK/TA0.1/COMP0.0/A1 | bidirectional | General-purpose I/O P1.1 with alternate eUSCI_B0 CLK, TA0.1, eCOMP0 input COMP0.0, and ADC input A1. |+| 12 | P1.2/UCB0SIMO/UCB0SDA/TA0.2/A2/Veref- | bidirectional | General-purpose I/O P1.2 with alternate eUSCI_B0 SIMO/SDA, TA0.2, ADC input A2, and ADC negative reference Veref-. |+| 13 | P1.3/UCB0SOMI/UCB0SCL/MCLK/A3 | bidirectional | General-purpose I/O P1.3 with alternate eUSCI_B0 SOMI/SCL, MCLK output, and ADC input A3. |+| 14 | P2.2/SYNC/ACLK/COMP0.1 | bidirectional | General-purpose I/O P2.2 with alternate CapTIvate synchronous trigger input SYNC, ACLK output, and eCOMP0 input COMP0.1. |+| 15 | P4.5/UCB0SOMI/UCB0SCL/TA3.2 | bidirectional | General-purpose I/O P4.5 with remapped eUSCI_B0 SOMI/SCL and remapped Timer_A3 TA3.2 function. |+| 16 | P4.6/UCB0SIMO/UCB0SDA/TA3.1 | bidirectional | General-purpose I/O P4.6 with remapped eUSCI_B0 SIMO/SDA and remapped Timer_A3 TA3.1 function. |+| 17 | P3.0/TA2.2/CAP0.0 | bidirectional | General-purpose I/O P3.0 with alternate Timer_A2 TA2.2 and CapTIvate channel CAP0.0. |+| 18 | P3.3/TA2.1/CAP0.1 | bidirectional | General-purpose I/O P3.3 with alternate Timer_A2 TA2.1 and CapTIvate channel CAP0.1. |+| 19 | P2.3/TA2.0/CAP0.2 | bidirectional | General-purpose I/O P2.3 with alternate Timer_A2 TA2.0 and CapTIvate channel CAP0.2. |+| 20 | P3.4/TA2CLK/COMP0OUT/CAP0.3 | bidirectional | General-purpose I/O P3.4 with alternate Timer_A2 TA2CLK, eCOMP0 output COMP0OUT, and CapTIvate channel CAP0.3. |+| 21 | P3.1/UCA1STE/CAP1.0 | bidirectional | General-purpose I/O P3.1 with alternate eUSCI_A1 STE and CapTIvate channel CAP1.0. |+| 22 | P2.4/UCA1CLK/CAP1.1 | bidirectional | General-purpose I/O P2.4 with alternate eUSCI_A1 CLK and CapTIvate channel CAP1.1. |+| 23 | P2.5/UCA1RXD/UCA1SOMI/CAP1.2 | bidirectional | General-purpose I/O P2.5 with alternate eUSCI_A1 RXD/SOMI and CapTIvate channel CAP1.2. |+| 24 | P2.6/UCA1TXD/UCA1SIMO/CAP1.3 | bidirectional | General-purpose I/O P2.6 with alternate eUSCI_A1 TXD/SIMO and CapTIvate channel CAP1.3. |+| 25 | VREG | power_out | Decoupling pin for the CapTIvate regulator, which requires a recommended 1-µF capacitor with ESR ≤ 200 mΩ. |+| 26 | P3.7/TA3.2/CAP2.0 | bidirectional | General-purpose I/O P3.7 with alternate Timer_A3 TA3.2 and CapTIvate channel CAP2.0. |+| 27 | P4.0/TA3.1/CAP2.1 | bidirectional | General-purpose I/O P4.0 with alternate Timer_A3 TA3.1 and CapTIvate channel CAP2.1. |+| 28 | P4.1/TA3.0/CAP2.2 | bidirectional | General-purpose I/O P4.1 with alternate Timer_A3 TA3.0 and CapTIvate channel CAP2.2 (CapTIvate analog pad, powered from VREG). |+| 29 | P4.2/TA3CLK/CAP2.3 | bidirectional | General-purpose I/O P4.2 with alternate Timer_A3 TA3CLK and CapTIvate channel CAP2.3 (CapTIvate analog pad, powered from VREG). |+| 30 | P2.7/UCB1STE/CAP3.0 | bidirectional | General-purpose I/O P2.7 with alternate eUSCI_B1 STE and CapTIvate channel CAP3.0. |+| 31 | P3.5/UCB1CLK/TB0TRG/CAP3.1 | bidirectional | General-purpose I/O P3.5 with alternate eUSCI_B1 CLK, Timer_B TB0TRG trigger input, and CapTIvate channel CAP3.1. |+| 32 | P3.2/UCB1SIMO/UCB1SDA/CAP3.2 | bidirectional | General-purpose I/O P3.2 with alternate eUSCI_B1 SIMO/SDA and CapTIvate channel CAP3.2. |+| 33 | P3.6/UCB1SOMI/UCB1SCL/CAP3.3 | bidirectional | General-purpose I/O P3.6 with alternate eUSCI_B1 SOMI/SCL and CapTIvate channel CAP3.3. |+| 34 | P4.7/UCA0STE/TB0.1 | bidirectional | General-purpose I/O P4.7 with alternate eUSCI_A0 STE (remapped) and Timer_B TB0.1. |+| 35 | P5.0/UCA0CLK/TB0.2 | bidirectional | General-purpose I/O P5.0 with alternate eUSCI_A0 CLK (remapped) and Timer_B TB0.2. |+| 36 | P5.1/UCA0RXD/UCA0SOMI/TB0.3 | bidirectional | General-purpose I/O P5.1 with alternate eUSCI_A0 RXD/SOMI (remapped) and Timer_B TB0.3. |+| 37 | P5.2/UCA0TXD/UCA0SIMO/TB0.4 | bidirectional | General-purpose I/O P5.2 with alternate eUSCI_A0 TXD/SIMO (remapped) and Timer_B TB0.4. |+| 38 | P2.0/XOUT | output | Output terminal of the 32-kHz crystal oscillator; when XIN is driven by an external clock in XT1BYPASS mode, this pin can be used for other purposes. |+| 39 | P2.1/XIN | input | Input terminal of the low-frequency 32-kHz crystal oscillator, which also accepts a digital clock signal when XT1BYPASS mode is selected. |+| 40 | DVSS | power_in | Ground reference (VSS) for the digital and analog modules; TI recommends separated grounds with a single-point connection for analog accuracy. |+| 41 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-40-EP(6x6) |+| Category | Embedded Processors & Controllers |+| Pins | 41 |++## CAD (KiCad official)++- Symbol: `MSP430FR2675TRHAR`+- Footprint: `Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm`+- 3D model: VQFN-40-EP(6x6) (KiCad packages3D, STEP)+- 3D model files: `msp430fr2675trhar-etched.step` / `msp430fr2675trhar-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `msp430fr2675trhar.step` / `msp430fr2675trhar.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/msp430fr2676) (129 pp, sha256 `98b202cd0699eba3`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/msp430fr2675trhar-datasheet.pdf)
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Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "embedded processors & controllers",+ "msp430fr2675trhar",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "msp430fr2675trhar.kicad_sym",+ "msp430fr2675trhar.kicad_mod",+ "msp430fr2675trhar.glb",+ "msp430fr2675trhar.step",+ "msp430fr2675trhar.lbr",+ "docs/hero.png",+ "docs/msp430fr2675trhar-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "msp430fr2675trhar-hero.glb",+ "msp430fr2675trhar-hero.overlay.json"+ ],+ "component": {+ "mpn": "MSP430FR2675TRHAR",+ "manufacturer": "Texas Instruments",+ "package": "VQFN-40-EP(6x6)",+ "pin_count": 41,+ "category": "Embedded Processors & Controllers",+ "subcategory": "Microcontrollers (MCU/MPU/SOC)",+ "datasheet": "https://www.ti.com/cn/lit/gpn/msp430fr2676",+ "parts": {+ "symbol": "msp430fr2675trhar.kicad_sym",+ "footprint": "msp430fr2675trhar.kicad_mod",+ "model_3d": "msp430fr2675trhar-hero.glb",+ "model_3d_plain": "msp430fr2675trhar.glb",+ "model_3d_step": "msp430fr2675trhar-etched.step",+ "model_3d_step_plain": "msp430fr2675trhar.step",+ "lbr": "msp430fr2675trhar.lbr"+ },+ "distributor_links": {+ "lcsc": "C2053034",+ "digikey": "296-MSP430FR2675TRHARTR-ND",+ "mouser": "595-SP430FR2675TRHAR"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T14:53:15Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-MSP430FR2675TRHARTR-ND",+ "status": "found"+ },+ "mouser": {+ "pn": "595-SP430FR2675TRHAR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "DVCC",+ "type": "power_in",+ "description": "Supply voltage for the digital and analog modules, specified 1.8 V to 3.6 V in CapTIvate VREG electrode charge mode and 2.7 V to 3.6 V in DVCC electrode charge mode, with 4.7 µF to 10 µF recommended at DVCC."+ },+ {+ "number": "2",+ "name": "RST/NMI/SBWTDIO",+ "type": "bidirectional",+ "description": "Reset input (RST, pullup enabled after BOR), NMI input, or Spy-Bi-Wire data I/O (SBWTDIO); an unused pin should be tied to DVCC through a 47-kΩ pullup or internal pullup with a 10-nF (or 1.1-nF) pulldown."+ },+ {+ "number": "3",+ "name": "TEST/SBWTCK",+ "type": "input",+ "description": "Test mode pin that always has an internal pulldown enabled, and Spy-Bi-Wire clock input (SBWTCK); leave open if unused."+ },+ {+ "number": "4",+ "name": "P1.4/UCA0TXD/UCA0SIMO/TA1.2/TCK/A4/VREF+",+ "type": "bidirectional",+ "description": "General-purpose I/O P1.4 with alternate eUSCI_A0 TXD/SIMO, TA1.2, JTAG TCK, ADC input A4, and VREF+; when A4 is used the 1.2-V PMM reference can be output here."+ },+ {+ "number": "5",+ "name": "P1.5/UCA0RXD/UCA0SOMI/TA1.1/TMS/A5",+ "type": "bidirectional",+ "description": "General-purpose I/O P1.5 with alternate eUSCI_A0 RXD/SOMI, TA1.1, JTAG TMS, and ADC input A5."+ },+ {+ "number": "6",+ "name": "P1.6/UCA0CLK/TA1CLK/TDI/TCLK/A6",+ "type": "bidirectional",+ "description": "General-purpose I/O P1.6 with alternate eUSCI_A0 CLK, TA1CLK, JTAG TDI/TCLK, and ADC input A6."+ },+ {+ "number": "7",+ "name": "P1.7/UCA0STE/SMCLK/TDO/A7",+ "type": "bidirectional",+ "description": "General-purpose I/O P1.7 with alternate eUSCI_A0 STE, SMCLK output, JTAG TDO, and ADC input A7."+ },+ {+ "number": "8",+ "name": "P4.3/UCB1SOMI/UCB1SCL/TB0.5/A8",+ "type": "bidirectional",+ "description": "General-purpose I/O P4.3 with alternate eUSCI_B1 SOMI/SCL, TB0.5, and ADC input A8."+ },+ {+ "number": "9",+ "name": "P4.4/UCB1SIMO/UCB1SDA/TB0.6/A9",+ "type": "bidirectional",+ "description": "General-purpose I/O P4.4 with alternate eUSCI_B1 SIMO/SDA, TB0.6, and ADC input A9."+ },+ {+ "number": "10",+ "name": "P1.0/UCB0STE/TA0CLK/A0/Veref+",+ "type": "bidirectional",+ "description": "General-purpose I/O P1.0 with alternate eUSCI_B0 STE, TA0CLK, ADC input A0, and ADC positive reference Veref+."+ },+ {+ "number": "11",+ "name": "P1.1/UCB0CLK/TA0.1/COMP0.0/A1",+ "type": "bidirectional",+ "description": "General-purpose I/O P1.1 with alternate eUSCI_B0 CLK, TA0.1, eCOMP0 input COMP0.0, and ADC input A1."+ },+ {+ "number": "12",+ "name": "P1.2/UCB0SIMO/UCB0SDA/TA0.2/A2/Veref-",+ "type": "bidirectional",+ "description": "General-purpose I/O P1.2 with alternate eUSCI_B0 SIMO/SDA, TA0.2, ADC input A2, and ADC negative reference Veref-."+ },+ {+ "number": "13",+ "name": "P1.3/UCB0SOMI/UCB0SCL/MCLK/A3",+ "type": "bidirectional",+ "description": "General-purpose I/O P1.3 with alternate eUSCI_B0 SOMI/SCL, MCLK output, and ADC input A3."+ },+ {+ "number": "14",+ "name": "P2.2/SYNC/ACLK/COMP0.1",+ "type": "bidirectional",+ "description": "General-purpose I/O P2.2 with alternate CapTIvate synchronous trigger input SYNC, ACLK output, and eCOMP0 input COMP0.1."+ },+ {+ "number": "15",+ "name": "P4.5/UCB0SOMI/UCB0SCL/TA3.2",+ "type": "bidirectional",+ "description": "General-purpose I/O P4.5 with remapped eUSCI_B0 SOMI/SCL and remapped Timer_A3 TA3.2 function."+ },+ {+ "number": "16",+ "name": "P4.6/UCB0SIMO/UCB0SDA/TA3.1",+ "type": "bidirectional",+ "description": "General-purpose I/O P4.6 with remapped eUSCI_B0 SIMO/SDA and remapped Timer_A3 TA3.1 function."+ },+ {+ "number": "17",+ "name": "P3.0/TA2.2/CAP0.0",+ "type": "bidirectional",+ "description": "General-purpose I/O P3.0 with alternate Timer_A2 TA2.2 and CapTIvate channel CAP0.0."+ },+ {+ "number": "18",+ "name": "P3.3/TA2.1/CAP0.1",+ "type": "bidirectional",+ "description": "General-purpose I/O P3.3 with alternate Timer_A2 TA2.1 and CapTIvate channel CAP0.1."+ },+ {+ "number": "19",+ "name": "P2.3/TA2.0/CAP0.2",+ "type": "bidirectional",+ "description": "General-purpose I/O P2.3 with alternate Timer_A2 TA2.0 and CapTIvate channel CAP0.2."+ },+ {+ "number": "20",+ "name": "P3.4/TA2CLK/COMP0OUT/CAP0.3",+ "type": "bidirectional",+ "description": "General-purpose I/O P3.4 with alternate Timer_A2 TA2CLK, eCOMP0 output COMP0OUT, and CapTIvate channel CAP0.3."+ },+ {+ "number": "21",+ "name": "P3.1/UCA1STE/CAP1.0",+ "type": "bidirectional",+ "description": "General-purpose I/O P3.1 with alternate eUSCI_A1 STE and CapTIvate channel CAP1.0."+ },+ {+ "number": "22",+ "name": "P2.4/UCA1CLK/CAP1.1",+ "type": "bidirectional",+ "description": "General-purpose I/O P2.4 with alternate eUSCI_A1 CLK and CapTIvate channel CAP1.1."+ },+ {+ "number": "23",+ "name": "P2.5/UCA1RXD/UCA1SOMI/CAP1.2",+ "type": "bidirectional",+ "description": "General-purpose I/O P2.5 with alternate eUSCI_A1 RXD/SOMI and CapTIvate channel CAP1.2."+ },+ {+ "number": "24",+ "name": "P2.6/UCA1TXD/UCA1SIMO/CAP1.3",+ "type": "bidirectional",+ "description": "General-purpose I/O P2.6 with alternate eUSCI_A1 TXD/SIMO and CapTIvate channel CAP1.3."+ },+ {+ "number": "25",+ "name": "VREG",+ "type": "power_out",+ "description": "Decoupling pin for the CapTIvate regulator, which requires a recommended 1-µF capacitor with ESR ≤ 200 mΩ."+ },+ {+ "number": "26",+ "name": "P3.7/TA3.2/CAP2.0",+ "type": "bidirectional",+ "description": "General-purpose I/O P3.7 with alternate Timer_A3 TA3.2 and CapTIvate channel CAP2.0."+ },+ {+ "number": "27",+ "name": "P4.0/TA3.1/CAP2.1",+ "type": "bidirectional",+ "description": "General-purpose I/O P4.0 with alternate Timer_A3 TA3.1 and CapTIvate channel CAP2.1."+ },+ {+ "number": "28",+ "name": "P4.1/TA3.0/CAP2.2",+ "type": "bidirectional",+ "description": "General-purpose I/O P4.1 with alternate Timer_A3 TA3.0 and CapTIvate channel CAP2.2 (CapTIvate analog pad, powered from VREG)."+ },+ {+ "number": "29",+ "name": "P4.2/TA3CLK/CAP2.3",+ "type": "bidirectional",+ "description": "General-purpose I/O P4.2 with alternate Timer_A3 TA3CLK and CapTIvate channel CAP2.3 (CapTIvate analog pad, powered from VREG)."+ },+ {+ "number": "30",+ "name": "P2.7/UCB1STE/CAP3.0",+ "type": "bidirectional",+ "description": "General-purpose I/O P2.7 with alternate eUSCI_B1 STE and CapTIvate channel CAP3.0."+ },+ {+ "number": "31",+ "name": "P3.5/UCB1CLK/TB0TRG/CAP3.1",+ "type": "bidirectional",+ "description": "General-purpose I/O P3.5 with alternate eUSCI_B1 CLK, Timer_B TB0TRG trigger input, and CapTIvate channel CAP3.1."+ },+ {+ "number": "32",+ "name": "P3.2/UCB1SIMO/UCB1SDA/CAP3.2",+ "type": "bidirectional",+ "description": "General-purpose I/O P3.2 with alternate eUSCI_B1 SIMO/SDA and CapTIvate channel CAP3.2."+ },+ {+ "number": "33",+ "name": "P3.6/UCB1SOMI/UCB1SCL/CAP3.3",+ "type": "bidirectional",+ "description": "General-purpose I/O P3.6 with alternate eUSCI_B1 SOMI/SCL and CapTIvate channel CAP3.3."+ },+ {+ "number": "34",+ "name": "P4.7/UCA0STE/TB0.1",+ "type": "bidirectional",+ "description": "General-purpose I/O P4.7 with alternate eUSCI_A0 STE (remapped) and Timer_B TB0.1."+ },+ {+ "number": "35",+ "name": "P5.0/UCA0CLK/TB0.2",+ "type": "bidirectional",+ "description": "General-purpose I/O P5.0 with alternate eUSCI_A0 CLK (remapped) and Timer_B TB0.2."+ },+ {+ "number": "36",+ "name": "P5.1/UCA0RXD/UCA0SOMI/TB0.3",+ "type": "bidirectional",+ "description": "General-purpose I/O P5.1 with alternate eUSCI_A0 RXD/SOMI (remapped) and Timer_B TB0.3."+ },+ {+ "number": "37",+ "name": "P5.2/UCA0TXD/UCA0SIMO/TB0.4",+ "type": "bidirectional",+ "description": "General-purpose I/O P5.2 with alternate eUSCI_A0 TXD/SIMO (remapped) and Timer_B TB0.4."+ },+ {+ "number": "38",+ "name": "P2.0/XOUT",+ "type": "output",+ "description": "Output terminal of the 32-kHz crystal oscillator; when XIN is driven by an external clock in XT1BYPASS mode, this pin can be used for other purposes."+ },+ {+ "number": "39",+ "name": "P2.1/XIN",+ "type": "input",+ "description": "Input terminal of the low-frequency 32-kHz crystal oscillator, which also accepts a digital clock signal when XT1BYPASS mode is selected."+ },+ {+ "number": "40",+ "name": "DVSS",+ "type": "power_in",+ "description": "Ground reference (VSS) for the digital and analog modules; TI recommends separated grounds with a single-point connection for analog accuracy."+ },+ {+ "number": "41",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Pin-attribute rows for RHA pins 10-27 are on pages 14-15, which are absent from the supplied text. T; Pin 25 is inferred as VREG: it is the only RHA number not assigned to a signal in the text, and the ; Pins 15 and 16 use the remapped eUSCI_B0 and Timer_A3 functions (P4.5/P4.6). These were confirmed th",+ "exposed pad 41 added from the footprint",+ "dropped thermal pad ['EP'] absent from footprint"+ ],+ "pages_sent": 52,+ "cost_usd": 0.3111,+ "at": "2026-10-08T14:52:52"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/msp430fr2676",+ "pages": 129,+ "sha256": "98b202cd0699eba3",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 41,+ "described": 41,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "msp430fr2675trhar.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 6,+ 1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "e5b4286c2329085d9ef7f90d5eb5bf41a435241ecc1baaf1383823b6d6a946ae",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "msp430fr2675trhar-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 6,+ 1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "40186c1d1e900d3a70dd3030ddd978224625fa8dbf423692bb07de0de9decb33",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}