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MSP430FR2675TPTR

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Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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MSP430FR2675TPTR

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)

MSP430FR2675TPTR from Texas Instruments, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DVCC power_in Digital and I/O supply input; recommended 4.7 µF to 10 µF bulk capacitor at DVCC, with 100 nF low-ESR ceramic placed within a few millimeters of the pin pair, and DVCC is 1.8 V to 3.6 V in VREG electrode charge mode (2.7 V to 3.6 V in DVCC electrode charge mode).
2 RST/NMI/SBWTDIO bidirectional Reset pin (RST, pullup by default), with NMI and Spy-Bi-Wire data (SBWTDIO) as alternate functions; when unused, use a 47 kΩ pullup to DVCC or the internal pullup with a 10 nF (or 1.1 nF with Spy-Bi-Wire tools) pulldown.
3 TEST/SBWTCK input TEST pin for JTAG/Spy-Bi-Wire access, with an internal pulldown that is always enabled and SBWTCK as the Spy-Bi-Wire clock; leave open when unused.
4 P1.4/UCA0TXD/UCA0SIMO/TA1.2/TCK/A4/VREF+ bidirectional General-purpose I/O P1.4 (LVCMOS, DVCC-powered, high impedance at reset) that also carries eUSCI_A0 TXD/SIMO, Timer_A1 CCR2, JTAG TCK, and ADC input A4 or VREF+.
5 P1.5/UCA0RXD/UCA0SOMI/TA1.1/TMS/A5 bidirectional General-purpose I/O P1.5 (LVCMOS, DVCC-powered, high impedance at reset) that also carries eUSCI_A0 RXD/SOMI, Timer_A1 CCR1, JTAG TMS, and ADC input A5.
6 P1.6/UCA0CLK/TA1CLK/TDI/TCLK/A6 bidirectional General-purpose I/O P1.6 (LVCMOS, DVCC-powered, high impedance at reset) that also carries eUSCI_A0 CLK, Timer_A1 clock input, JTAG TDI/TCLK, and ADC input A6.
7 P1.7/UCA0STE/SMCLK/TDO/A7 bidirectional General-purpose I/O P1.7 (LVCMOS, DVCC-powered, high impedance at reset) that also carries eUSCI_A0 STE, SMCLK output, JTAG TDO, and ADC input A7.
8 P4.3/UCB1SOMI/UCB1SCL/TB0.5/A8 bidirectional General-purpose I/O P4.3 (LVCMOS, DVCC-powered) that also carries eUSCI_B1 SOMI/SCL (remapped), Timer_B0 CCR5 (TB0.5), and ADC input A8.
9 P4.4/UCB1SIMO/UCB1SDA/TB0.6/A9 bidirectional General-purpose I/O P4.4 (LVCMOS, DVCC-powered) that also carries eUSCI_B1 SIMO/SDA (remapped), Timer_B0 CCR6 (TB0.6), and ADC input A9.
10 P5.3/UCB1CLK/TA3.0/A10 bidirectional General-purpose I/O P5.3 that also carries eUSCI_B1 CLK (remapped), Timer_A3 CCR0 (TA3.0 remapped), and ADC input A10.
11 P5.4/UCB1STE/TA3CLK/A11 bidirectional General-purpose I/O P5.4 that also carries eUSCI_B1 STE (remapped), Timer_A3 clock input (TA3CLK remapped), and ADC input A11.
12 P1.0/UCB0STE/TA0CLK/A0/Veref+ bidirectional General-purpose I/O P1.0 that also carries eUSCI_B0 STE, Timer_A0 clock input, ADC input A0, and the ADC positive reference Veref+.
13 P1.1/UCB0CLK/TA0.1/COMP0.0/A1 bidirectional General-purpose I/O P1.1 that also carries eUSCI_B0 CLK, Timer_A0 CCR1 (TA0.1), eCOMP0 input COMP0.0, and ADC input A1.
14 P1.2/UCB0SIMO/UCB0SDA/TA0.2/A2/Veref- bidirectional General-purpose I/O P1.2 that also carries eUSCI_B0 SIMO/SDA, Timer_A0 CCR2 (TA0.2), ADC input A2, and the ADC negative reference Veref-.
15 P1.3/UCB0SOMI/UCB0SCL/MCLK/A3 bidirectional General-purpose I/O P1.3 that also carries eUSCI_B0 SOMI/SCL, MCLK output, and ADC input A3.
16 P2.2/SYNC/ACLK/COMP0.1 bidirectional General-purpose I/O P2.2 that also carries the CapTIvate synchronization trigger input SYNC, ACLK output, and eCOMP0 input COMP0.1.
17 P4.5/UCB0SOMI/UCB0SCL/TA3.2 bidirectional General-purpose I/O P4.5 that also carries eUSCI_B0 SOMI/SCL (remapped) and Timer_A3 CCR2 (TA3.2 remapped).
18 P4.6/UCB0SIMO/UCB0SDA/TA3.1 bidirectional General-purpose I/O P4.6 that also carries eUSCI_B0 SIMO/SDA (remapped) and Timer_A3 CCR1 (TA3.1 remapped).
19 P5.5/UCB0CLK/TA2CLK bidirectional General-purpose I/O P5.5 that also carries eUSCI_B0 CLK (remapped) and the Timer_A2 clock input (TA2CLK remapped).
20 P5.6/UCB0STE/TA2.0 bidirectional General-purpose I/O P5.6 that also carries eUSCI_B0 STE (remapped) and Timer_A2 CCR0 (TA2.0 remapped).
21 P5.7/TA2.1/COMP0.2 bidirectional General-purpose I/O P5.7 that also carries Timer_A2 CCR1 (TA2.1 remapped) and eCOMP0 input COMP0.2.
22 P6.0/TA2.2/COMP0.3 bidirectional General-purpose I/O P6.0 that also carries Timer_A2 CCR2 (TA2.2 remapped) and eCOMP0 input COMP0.3.
23 P3.0/TA2.2/CAP0.0 bidirectional General-purpose I/O P3.0 that also carries Timer_A2 CCR2 (TA2.2 default) and CapTIvate channel CAP0.0.
24 P3.3/TA2.1/CAP0.1 bidirectional General-purpose I/O P3.3 that also carries Timer_A2 CCR1 (TA2.1 default) and CapTIvate channel CAP0.1.
25 P2.3/TA2.0/CAP0.2 bidirectional General-purpose I/O P2.3 that also carries Timer_A2 CCR0 (TA2.0 default) and CapTIvate channel CAP0.2.
26 P3.4/TA2CLK/COMP0OUT/CAP0.3 bidirectional General-purpose I/O P3.4 that also carries the Timer_A2 clock input (TA2CLK default), eCOMP0 output COMP0OUT, and CapTIvate channel CAP0.3.
27 P3.1/UCA1STE/CAP1.0 bidirectional General-purpose I/O P3.1 that also carries eUSCI_A1 STE and CapTIvate channel CAP1.0.
28 P2.4/UCA1CLK/CAP1.1 bidirectional General-purpose I/O P2.4 that also carries eUSCI_A1 CLK and CapTIvate channel CAP1.1.
29 P2.5/UCA1RXD/UCA1SOMI/CAP1.2 bidirectional General-purpose I/O P2.5 that also carries eUSCI_A1 RXD/SOMI and CapTIvate channel CAP1.2.
30 P2.6/UCA1TXD/UCA1SIMO/CAP1.3 bidirectional General-purpose I/O P2.6 that also carries eUSCI_A1 TXD/SIMO and CapTIvate channel CAP1.3.
31 VREG power_out CapTIvate regulator output that requires a decoupling capacitor of 1 µF (recommended) with maximum ESR of 200 mΩ.
32 P3.7/TA3.2/CAP2.0 bidirectional General-purpose I/O P3.7 that also carries Timer_A3 CCR2 (TA3.2 default) and CapTIvate channel CAP2.0.
33 P4.0/TA3.1/CAP2.1 bidirectional General-purpose I/O P4.0 that also carries Timer_A3 CCR1 (TA3.1 default) and CapTIvate channel CAP2.1.
34 P4.1/TA3.0/CAP2.2 bidirectional General-purpose I/O P4.1 (reset state OFF) that also carries Timer_A3 CCR0 (TA3.0 default) and CapTIvate channel CAP2.2 powered from VREG.
35 P4.2/TA3CLK/CAP2.3 bidirectional General-purpose I/O P4.2 (reset state OFF) that also carries the Timer_A3 clock input (TA3CLK default) and CapTIvate channel CAP2.3 powered from VREG.
36 P2.7/UCB1STE/CAP3.0 bidirectional General-purpose I/O P2.7 (reset state OFF) that also carries eUSCI_B1 STE and CapTIvate channel CAP3.0 powered from VREG.
37 P3.5/UCB1CLK/TB0TRG/CAP3.1 bidirectional General-purpose I/O P3.5 (reset state OFF) that also carries eUSCI_B1 CLK, the Timer_B0 external trigger input TB0TRG, and CapTIvate channel CAP3.1 powered from VREG.
38 P3.2/UCB1SIMO/UCB1SDA/CAP3.2 bidirectional General-purpose I/O P3.2 (reset state OFF) that also carries eUSCI_B1 SIMO/SDA and CapTIvate channel CAP3.2 powered from VREG.
39 P3.6/UCB1SOMI/UCB1SCL/CAP3.3 bidirectional General-purpose I/O P3.6 (reset state OFF) that also carries eUSCI_B1 SOMI/SCL and CapTIvate channel CAP3.3 powered from VREG.
40 P6.1/TB0CLK bidirectional General-purpose I/O P6.1 (reset state OFF) that also carries the Timer_B0 clock input TB0CLK.
41 P6.2/TB0.0 bidirectional General-purpose I/O P6.2 (reset state OFF) that also carries Timer_B0 CCR0 (TB0.0).
42 P4.7/UCA0STE/TB0.1 bidirectional General-purpose I/O P4.7 (reset state OFF) that also carries eUSCI_A0 STE (remapped) and Timer_B0 CCR1 (TB0.1).
43 P5.0/UCA0CLK/TB0.2 bidirectional General-purpose I/O P5.0 (reset state OFF) that also carries eUSCI_A0 CLK (remapped) and Timer_B0 CCR2 (TB0.2).
44 P5.1/UCA0RXD/UCA0SOMI/TB0.3 bidirectional General-purpose I/O P5.1 (reset state OFF) that also carries eUSCI_A0 RXD/SOMI (remapped) and Timer_B0 CCR3 (TB0.3).
45 P5.2/UCA0TXD/UCA0SIMO/TB0.4 bidirectional General-purpose I/O P5.2 (reset state OFF) that also carries eUSCI_A0 TXD/SIMO (remapped) and Timer_B0 CCR4 (TB0.4).
46 P2.0/XOUT bidirectional General-purpose I/O P2.0 (reset state OFF) that also serves as XOUT, the output terminal of the 32-kHz crystal oscillator.
47 P2.1/XIN bidirectional General-purpose I/O P2.1 (reset state OFF) that also serves as XIN, the input terminal of the 32-kHz crystal oscillator; the device supports only a low-frequency (32 kHz) crystal here.
48 DVSS power_in Ground reference for the digital and analog modules; the datasheet calls for separated grounds with a single-point connection to reduce noise.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-48(7x7)
Category Embedded Processors & Controllers
Pins 48

CAD (KiCad official)

  • Symbol: MSP430FR2675TPTR
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: msp430fr2675tptr-etched.step / msp430fr2675tptr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); msp430fr2675tptr.step / msp430fr2675tptr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (129 pp, sha256 98b202cd0699eba3, retrieved 2026-10-11, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF